US3691403A

US3691403A - Optically coupled logic circuit

Info

Publication number: US3691403A
Application number: US183965A
Authority: US
Inventors: Reed A Newmeyer
Original assignee: Solid State Devices Inc
Current assignee: Display Technologies LLC
Priority date: 1971-09-27
Filing date: 1971-09-27
Publication date: 1972-09-12
Anticipated expiration: 1989-09-12

Abstract

A full-wave bridge rectifier, an optical coupler, and a delay circuit provide electrical noise isolation between a pair of signal-input terminals and a pair of output terminals. Output signals are provided at the output terminals whenever a full-wave a.c. input signal or a half-wave signal is applied to either signal-input terminal.

Description

[1s] 3,691,403 1 Sept. 12,1972

United States Patent Newmeyer [56] References Cited OTHER PUBLICATIONS Optical Link Isolates Low-cost Solid-state Relay" Mail 197??8; Q91.

[ OPTICALLY COUPLED LOGIC CIRCUIT [72] Inventor: Reed A. Newmeyer, Glendale,

Primary ExaminerJohn Zazworsky Attorney-Herbert E. Haynes, Jr.

Ariz. 85301 Assignee: Solid State Devices, Inc., Tempe,

Ariz.

Sept. 27, 1971 [21] Appl.No.:183,965

[22] Fil'edz ABSTRACT A full-wave bridge rectifier, an optical coupler, and a delay circuit provide electrical noise isolation between a pair of signal-input terminals and a pair of output 7 terminals. Output signals are provided at the output terminals whenever a full-wave a.c. input signal or a half-wave signal is applied to either signal-input ter- 2 mmm 131 3 3 W W 5 5 2H2 l mb l "3 3 2 w n a 0 NH 3 m3 ,u/ 107 3 no 2 "3 7 mm 0 u" M "u mmhw "6 HM L mi 0 d 5mm UIF 1]] 218 555 [.III.

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6 Claims, 2 Drawing Figures OPTICALLY COUPLED LOGIC CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to electronic circuits and more particularly to a circuit which provides an output signal whenever a full-wave a.c. signal or a half-wave signal is applied to either one of a pair of signal-input terminals.

2. Description of the Prior Art Electric signaling systems are in common use at roadway intersections to control the flow of vehicular and pedestrian traffic. These systems, as any electrical apparatus, are subject to failures or malfunctions due to burned out components, worn mechanical relays, electrical interference and the like.

With the ever increasing traffic handling problems, accidents, and the legal problems resulting from the latter, it has become essential that a fail-safe traffic signaling system be devised.

Some failures or malfunctions of traffic signaling systems result in conflicting proceed signals appearing at the signal heads or semaphores. A conflicting condition or signal may be defined as one which results in intersecting traffic patterns being signaled to proceed simultaneously. For example, one type of a conflicting condition would be when the semaphores of two or more intersecting roads are simultaneously displaying green lights or any other type of proceed signal such as turn arrows, amber lights, pedestrian walk and the like.

For fail-safe operation of the semaphore system when a conflict in the proceed signals occurs, it is necessary to monitor the proceed signals, detect when a conflict occurs and take appropriate action such as switching the system to a flashing mode of operation.

Monitoring devices for this purpose have been developed, one particular monitor, in which the circuit of the present invention is employed, is disclosed in a copending US. Pat. applicator entitled Semaphore Conflict Monitor filed July 23, I971, Ser. No. 165,528, by Michael F. Jarco et al. This referenced US. Pat. application describes in detail the environment in which the circuit of the present invention is employed.

The above referenced monitor and someprior art monitors are coupled to the semaphore system by a wire being connected to each buss which applies power to the proceed signals of the semaphore. Each time a proceed signal receives power it is sensed by the monitor and the sensed signals are employed therein to detect conflicts.

The circuit of the present invention is adapted to sense when the proceed signals are receiving power and relay the sensed data to the monitoring circuits.

Some prior art circuits for this purpose employ mechanical relays and relay circuits. Since these devices are electromechanical the useful life of these relays is relatively short, they are inherently electrically noisy and relatively slow acting.

The present invention alleviates some of the disadvantages of the prior art by providing a circuit which uses solid state devices including transistors and an optical coupler. The useful life of these solid state devices is much longer than the electromechanical devices and they are relatively trouble-free, electrically quiet and fast acting.

One hundred and ten V.A.C. is applied through triacs to the power busses of the semaphore system. In

the event that one of the diodes of a triac fails, halfwave a.c. results. Half-wave a.c. is sufficient to illuminate a semaphore signal at a reduced intensity. However, half-wave a.c. will not operate the circuits of the prior art conflict monitors and would not operate the circuits of the hereinbefore referenced monitor if the circuit of the present invention were not employed therein. Therefore, the circuit of the present invention is adapted to operate on either a half-wave a.c. input of a full-wave a.c. input.

Other prior art circuits may develop error signals due to electrical noise either from the semaphore system or from their electromechanical devices. The circuit of the present invention employs an optical coupler to electrically isolate the monitor circuits.

In view of the foregoing, a need exists for a new and useful optical coupling circuit which employs all solid state devices, is operable with inputs of half-wave a.c. or full-wave a.c., and employs an optical coupler.

SUMMARY OF THE INVENTION The circuit of the present invention comprises a solid state device which employs a full-wave bridge rectifier, an optical coupler and a delay circuit to provide electrical noise isolation between the input terminals and output terminals thereof, and allows operation of the circuit on either half-wave or full-wave a.c.

Accordingly, it is an object of the present invention to provide a new and useful optically coupled circuit.

Another object of this invention is to provide a new and useful circuit which develops an output signal when a half-wave signal is received at an input terminal.

Another object of this invention is to provide a new and useful circuit which develops an output signal when a full-wave signal is applied to an input terminal.

Another object of this invention is to provide a new and useful circuit which develops an output signal when a half-wave signal is received at any of the input terminals.

Still another object of this invention is to provide a new and useful circuit which produces an output signal when a full-wave signal is applied to any of the input terminals.

Yet another object of the present invention is to provide a new and useful circuit which is optically coupled between its input terminals and its output terminals to substantially reduce electrical noise.

Another object of this invention is to provide a new and useful circuit which produces an output signal which is shorter in time duration than the input signal.

Other objects and advantages of the present invention will become apparent from the following description when taken in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of one embodiment of the present invention; and

FIG. 2 illustrates waveforms which are useful in explaining the operation of the invention shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT The optically coupled logic circuit shown in FIG. 1 includes a full-wave bridge rectifier 10, an optical coupler 11, a turn-on delay circuit 12 and a pair of inverters l3 and 14. A source of electrical power, such as 1 volts a.c. is connected between terminal 16 and a reference terminal 17. A pair of switches 19 and 20 selectively couple electrical power toa pair of input terminals 22 and 23. Switches 19 and 20 may each include a triac or other types of controlled switches. Rectifier 10 includes a plurality of diodes 25-28 connected to a pair of input leads and 31 and a pair of output leads 32 and 33. A pair of diodes 35 and 36 are connected to output leads 32 and 33 respectively and are connected to input terminal 22. When switch 19 or 20 couples an ac. voltage to either terminal 22 or terminal 23, the rectifier 10 causes a capacitor 38 to charge through resistor 39 to the polarity shown in FIG. 1.

The optical coupler 11 includes a light emitting diode 43 mounted adjacent a phototransistor 44. When capacitor 38 is charged a current I flows from the lower plate of capacitor 38 through resistor 41 and diode 43 to the upper plate of capacitor 38. Current 1 causes diode 43 to emit light which renders phototransistor 44 conductive. When phototransistor 44 is conductive current through resistor 46 produces a voltage drop which causes a low value of voltage at the base of transistor 50 to render transistor 50 nonconductive. When transistor 50 is nonconductive current through resistor 51 causes capacitor 52 to charge to the polarity shown in FIG. 1. Capacitor 52 has a relatively large value so that the voltage across capacitor 52 rises slowly as shown in waveform C of FIG. 2.

Capacitor 38 and resistor 39, across the output leads 32 and 33 of the full-wave rectifier, also provide some time delay in the circuit. For example, if a voltage is applied to input terminal 22 or input terminal 23 at the time I as shown in waveform A, FIG. 2, the voltage across capacitor 38 increases as shown in waveform B. At time t the optical coupler provides enough current so that the voltage drop across resistor 46 renders transistor 50 nonconductive. At time t (waveform C) the voltage across capacitor 52 has increased so that the voltage coupled to the base of transistor 58 renders transistor 58 conductive.

Resistor 51 and capacitor 52 form a time delay circuit so that there is a delay between the time that the input signal of waveform A (FIG. 2) is applied and the time that the output signal of waveform D changes. This delay compensates for variation in value of components such as resistor 39 and capacitor 38. This time delay may be provided in any portion of the circuit between input terminal 22 and output terminal 78. For example, a time delay circuit could be connected between the bridge rectifier l0 and the optical coupler l I.

When transistor 58 is rendered conductive the voltage at the collector drops so that the voltage at the base of transistor 68 drops and renders transistor 68 nonconductive. The voltage at the collector of transistor 68 rises rapidly as shown in waveform E of FIG. 2. The rapid rise in voltage at the collector of transistor 68 is coupled through resistor 81 and capacitor 80 to the base of transistor 58 causing transistor 58 to switch rapidly from a nonconductive state to a conductive state. Capacitor and resistor 81 prevent noise signals from causing transistor 58 to switch back to a nonconductive state at time t;,.

When an ac voltage is no longer applied to either terminal 22 or terminal 23 capacitor 38 discharges and current I, through the light emitting diode 43 decreases. The phototransistor 44 no longer conducts so that the voltage at the base of transistor 50 increases. When the voltage at the base of transistor 50 increases transistor 50 is rendered conductive. The resistance of transistor 50 is relatively low so that capacitor 52 discharges rapidly. This causes the signal shown in wave form C to have a rapid fall time. Thus, the time delay between the change in input signal at time and the change in output signal at the time t is very short. This combined with the time delay in charging capacitor 52 at time causes the duration of the pulse of waveform D to be less than the duration of waveform A.

A plurality of the circuits as shown in FIG. 1 are employed to couple trafiic signals to the Semaphore Conflict Monitor as described in the previously referenced patent application. The monitor compares the traffic signals for simultaneous concurrence which indicates a conflict. By shortening the output pulses as previously described, overlapping of the output signals which may occur during turn-on and turn-off times of the compared signals is prevented from producing conflicting signals which would be sensed by the monitor. When capacitor 52 discharges the voltage at the base of transistor 58 decreases rendering transistor 58 nonconductive. When transistor 58 is nonconductive the voltage at the collector of transistor 58 and at the base of transistor 68 rises so that transistor 68 is rendered conductive. The voltage at output terminal 78 rises and the voltage at output terminal 79 drops as shown in waveforms D and E respectively.

While the principles of the invention have now been made clear in the preferred embodiments, there will be immediately obvious to those skilled in the art many modifications in structure, arrangements, proportions, the elements, and materials used in the practice of the invention, and otherwise, which are particularly adapted to specific environments and operating requirements without departing from those principles. The appended claims are therefore intended to cover and embrace any such modifications within the limits only of the true scope of the invention.

What is claimed is:

1. An optically coupled logic circuit comprising: a full-wave bridge rectifier having first and second input leads and first and second output leads;

first and second input terminals and a reference terminal, said first terminal being connected to said first input lead of said rectifier, said reference terminal being connected to said second input lead of said rectifier;

first and second diodes, said first diode being connected between said second input terminal and said first output lead of said rectifier, said second diode being connected between said second input terminal and said second output lead of said rectifier;

an optical coupler having first and second input leads and an output lead, said first input lead of said coupler being connected to said first output lead of said rectifier, said second input lead of said coupler being coupled to said second output lead of said rectifier;

a time delay circuit having an input lead and an output lead, said input lead of said delay circuit being coupled to said output lead of said coupler; and

first and second inverters each having an input lead 1 and an output lead, said input lead of said first inverter being coupled to said output lead of said delay circuit, said'output lead of said first inverter being coupled to said input lead of said second inverter. 2. An optically coupled logic circuit as defined in claim 1 including:

first and second output terminals, said first output terminal being connected to said output lead of said first inverter, said second output terminal being connected to said output lead of said second inverter. 3. An optically coupled logic circuit as defined in claim 2 including:

a first capacitor; and a first resistor, said first capacitor and said first resistor being connected in series between said output lead of said second inverter and said input lead of said first inverter. 4. An optically coupled logic circuit as defined in claim 2 including:

a first capacitor; and

a first resistor, said first capacitor and said first resistor being connected in series between said first and said second output leads of said rectifier, said second input lead of said coupler being connected to a junction point between said first resistor and said first capacitor.

5. An optically coupled logic circuit as defined in claim 4 including:

a second capacitor; and

a second resistor, said second capacitor and said second resistor being connected in series between said output lead of said second inverter and said input lead of said first inverter.

6. An optically coupled logic circuit as defined in claim 5 wherein said time delay circuit includes:

a transistor having a base, a collector and an emitter;

first and second reference potentials;

a third resistor, said third resistor being connected between said first potential and said collector of said transistor; and

a third capacitor, said third capacitor being connected between said second potential and said collector of said transistor, said input lead of said delay circuit being coupled to said base of said transistor, said output lead of said delay circuit being connected to said collector of said transistor, said emitter of said transistor being connected to said second potential.

Claims

1. An optically coupled logic circuit comprising: a full-wave bridge rectifier having first and second input leads and first and second output leads; first and second input terminals and a reference terminal, said first terminal being connected to said first input lead of said rectifier, said reference terminal being connected to said second input lead of said rectifier; first and second diodes, said first diode being connected between said second input terminal and said first output lead of said rectifier, said second diode being connected between said second input terminal and said second output lead of said rectifier; an optical coupler having first and second input leads and an output lead, said first input lead of said coupler being connected to said first output lead of said rectifier, said second input lead of said coupler being coupled to said second output lead of said rectifier; a time delay circuit having an input lead and an output lead, said input lead of said delay circuit being coupled to said output lead of said coupler; and first and second inverters each having an input lead and an output lead, said input lead of said first inverter being coupled to said output lead of said delay circuit, said output lead of said first inverter being coupled to said input lead of said second inverter.

2. An optically coupled logic circuit as defined in claim 1 including: first and second output terminals, said first output terminal being connected to said output lead of said first inverter, said second output terminal being connected to said output lead of said second inverter.

3. An optically coupled logic circuit as defined in claim 2 including: a first capacitor; and a first resistor, said first capacitor and said first resistor being connected in series between said output lead of said second inverter and said input lead of said first inverter.

4. An optically coupled logic circuit as defined in claim 2 including: a first capacitor; and a first resistor, said first capacitor and said first resistor being connected in series between said first and said second output leads of said rectifier, said second input lead of said coupler being connected to a junction point between said first resistor and said first capacitor.

5. An optically coupled logic circuit as defined in claim 4 including: a second capacitor; and a second resistor, said second capacitor and said second resistor being connected in series between said output lead of said second inverter and said input lead of said first inverter.

6. An optically coupled logic circuit as defined in claim 5 wherein said time delay circuit includes: a transistor having a base, a collector and an emitter; first and second reference potentials; a third resistor, said third resistor being connected between said first potential and said collectOr of said transistor; and a third capacitor, said third capacitor being connected between said second potential and said collector of said transistor, said input lead of said delay circuit being coupled to said base of said transistor, said output lead of said delay circuit being connected to said collector of said transistor, said emitter of said transistor being connected to said second potential.