US3702988A

US3702988A - Digital processor

Info

Publication number: US3702988A
Application number: US72084A
Authority: US
Inventors: Ralph D Haney; James E Zachar; Charles J Drozd
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp; National Cash Register Co
Priority date: 1970-09-14
Filing date: 1970-09-14
Publication date: 1972-11-14
Anticipated expiration: 1989-11-14
Also published as: CA960367A; ATA795971A; NL179519B; ZA715478B; BR7105982D0; GB1324617A; NL7112629A; HU165413B; BE772600A; FR2112955A5; DK140816C; ES394831A1; NO132885B; SE366130B; AU445934B2; NO132885C; AT327590B; DK140816B; DE2145120B2; CH539886A

Abstract

A digital processor built entirely of metal-oxide semiconductor devices constructed on integrated circuits by large-scale integration techniques is shown. The processor includes a readonly memory means which provides a series of coded instruction signals in a serial-by-bit manner to a memory buss line. A plurality of logic circuits is coupled to the memory buss line, and each responds to selected ones of the instruction signals to perform a certain operation. There is also provided a plurality of registers which can be used in processing information.

Description

United States Patent Haney et a]. [4 1 Nov. 14, 1972 1 DIGITAL PROCESSOR 3,440,618 4/1969 Chinlund... ..340/172.5 [72] Inventors: Ralph ey; J E Zach", 3,480,914 11/1969 Schlaepp1 ..340/172.5

both f D Droz i x gg gigg J Pnmary ExammerPaul J. Henon Assistant Examiner-Ronald F. Chapuran [73] Assignee: The National Cash Register Com- Attorney-Louis A. Kline, John J. Callahan and Harry pany, Dayton, Ohio W. Barron [22) Filed: Sept. 14, 1970 [57} ABSTRACT [21] Appl' 72084 A digital processor built entirely of metal-oxide semiconductor devices constructed on integrated cir- [52] US. Cl. ..340/172.5 Quits by lafge'scale integration techniques is 511 lnt.Cl ..G06f7/48 The processor includes a read-Only memory means 58 Field of Search ..340/172.5 which Provides a of coded ir'strucfim signals in a serial-by-bit manner to a memory buss line. A plu- [56] References Cited rality of logic circuits is coupled to the memory buss lme, and each responds to selected ones of the instruc- UNITED STATES PATENTS tion signals to perform a certain operation. There is also provided a plurality of registers which can be 3,315,235 4/1967 Carnevale et al ..340/172.5 used in processing information 3,579,201 5/1971 Langley "340/1725 3,391,394 7/1968 Ottaway ..340/172.5 31 Claims, 23 Drawing Figures FUNCTION FLAG DATA DATA FUNCTION PQRT g TCTB sE CT I6 I.

I a U TF2 INPUT/OUTPUT P 62 2:3 MEANS c r" I T Rsoul cLEAR l Rsti l m RSDHI RSOLI I g 66% 515515; Ri in J INDICATOR 22\ --r MEANs h RSDL CLEAR RSOH- 60 g 40 RSDH- RSOL 36 A Q E 38* [I8 g as 20 m g r58 SAC LAC PARglili'EAll: TO I A j LOGIC BAT 3: CONVERTER Q 8 AccuMuLAToR 2 mg *1 REGISTER m g 56 8: g ACCUMULATOR MEANS 4 ONLY Rsclu l CLAR lnsi mz MEMORY z :I; 55 RSDHZ Rsou '6 RAR TA RTC A f s g 24 BcR 2 LOGIC ADDRESS 3 4 5 49 m REGISTER RAR/ TA/ RTc REGISTER A g 42 Rsoizl CLAR TRsdNI 8 m RSDH! RSOLZ 5 z RSDJ RsoLI g 9 26 CLEAR RSDH4 R$OH4 m '2 PROGRAM COUNTER MEANS --l "-1 1 z E l REcIsTER SEL- 285 E EcTIoN LOGIC B 0 Q SFT TRANSFER wNTROL 8' REGISTER SELECTION MEANS PA TENTED W 14 I97? 3, 702, 988

SHEET 01 HF II FUN TION F A DATA/ HG f c L G FUNCTION TIMING DATA FUNCT'ON PORT I6 FUNCTION TCTB SEL CTION FLA w. f--I Fl JR U NJ W2 W5 INPUT OUTPUT P 1 2:3 MEANS INOICATOR an 5 U T REGISTER I E I RSDL! CL AR T R507]! 5 RSDHI RSOLI L0G": 66v STORAGE REGISTERS INOICATOR I MEANS 22\/ 34 RSDL- CLEAR RSOR- 60 E RSDH- RSOL 36 5 38- is (Z a m 4 (58 BAG LAC PARALLEL TO 1 LOGIC BAT LAN SERIAL ma .l LOR CONVERTER 2 53 ACCuMuLATOR 3 mg REGISTER m g -56 0: 9 ACCuMuLATOR MEANS 44 f k T READ ONLY g RSOLI CLEAR RSOI-I2 MEMORY 2 SI; 55 RSOII2

RSOLI m

50 ,54 z z I 52 48 RAR TA I I-rT 6 R 24\ Ben i 2 [LOGIGZ ADDRESS 3 4 5 49 m REGISTER RAR/ TA/RTC REGISTER g J u A 42 RSDLZt CLEAR f RSOHI 8 m LQGIC [I RSDHI RSOLZ 5 Z RSDLI RSOLI g2 26 CLEAR IRSOR4 RSOR4 In 4 PROGRAM COUNTER MEANS 1 z E NOV 6 In REGISTER SEL- ADD E J ECTION LOGIC SUB o O SFT i Q AOO u 32 S a TRANSFER CONTROL 8! Fl G I 5 REGISTER SELECTION MEANS INVENTORS RALPH D. HANEY JAMES EZACIIAR a IGD |6C I66 16A CHARLES J.DROZD BY @Qm/K m ICE I6F ISG |6H W WEW'F,

THE! ATTORNEYS PATENTEDnnv 14 I972 3; 702,988

sum 02 ur 11 F|G.8 FIG.9 FIG.|O FIG." $3 3 INVENTORS RALPH D. HANEY JAMES ElACHAR 8 CHARLES J. DROZD Wm 47% Q Q W THEIR AT TOR NE YS PAIE'II'IEDIII 14 m2 3.702.988

SIIEEI 03 UF 1 1 FIG. 3 N2 b9 b8 b5 b4 bl FIG. 4 M2 b5 b4 bl C OP FIG. 5 b|2 b9 b8 b5 b4 bl P OP FIG. 6 bl2 b7 b6 b5 b4 bl RA B A OP FIG. 7 M2 b9 b8 b5 b4 b P OP RA I T F bI2 b7 b6 b5 b4 bI INVENTOFIS RALPH D. HANEY JAMES E. ZACHAR 8 CHARLES J. DROZD TH! IR AT TONNk Y5 PATENTEDNM 14 m2 3; 702,988 SHEET on HF 11 1 6 & \68

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INVENTORS RALPH D. HANEY JAMES E. ZACHAR 8| CHARLES J DROZD WW KM BY NW P'A'TE'N'TEDIIIII 14 I972 3.702 988 SIIEEI USUF 11 I I I I II M06 5\ IIIIIIIIIII I6 244 I I I 240 MAI6 I I I2 BIT SHIFT I I5 I I REGISTER I E'I",%E% I LPARRALLEL-TO-SERIAL CONVERTER I I4 8 I 1 LL! I free LOGIC I82 22 I I3 5 7 I MRE 0 I I2 I IMZMAI LOGIC I86 MZMAI I LOGIC MAIZ I I MRB I I MA II I MSRD I MADT I0 I I MRB I88 I MADD MA IO I 2 I LOGIC F I 9 M9 6 I I I \II I 8 MAB I I II MZMAI I 7 MA? I I LOGIC I 6 MAG I I MIGRY I 5 I l I MAS I 4 MA4 I I I IMZMAI I 3 MA3 L I *AB 2 I I IV I MA2 I FIGJGB I MAI {MAB 48 ,L LA LBRARXPC I I 1 LOGIC I I I \J I I I i::; I

INVENTORS RALPH D. HANEY JAMES E. ZACHAR 8 CH RLES J, DR ZD WI BY WQIWM THEIR ATTORNEYS PATENTED III II 3.702.988

SHEET lOUF 11 ICLEAR I MRB MR8 I MB MB IF I 5| sI I I I I I I I l I l I I RSOHI Rs H3 I I R50 3 lRSfiLES /3I2 I I CLEAR I l I AB; 0 DATA REGISTER #2 I I Rs HI Rs HI I Rso| 4 IRG IA 3I4 I CLEAR I I I DATA REGIsTER #3 I I Rs H2 Rs H2 I Rso I IRG LI I 3 I CLEAR 7 f I I OB DATA REGISTER I45 I I I Rs H2 Rs H2 I I RSO RSIELZ f /3 3 I I CLEAR I I DATA REGISTER #6 I I I I I I I I I I I I I l I I I I I R H3 Rs 3: I I I I I RSOLiT Rsom r I I I I I CLEAR I l T I I I AB 08 DATA REGISTER m4 I I I I I I I RSOH4 Rs H3 I I RSOL4 I RGI IL I T I I CLEAR I I B DATA REGISTER 1115 I I I: I I I I I I cc ACC I I 3 AB 1 0 I D I INVENTORS F|G '6 G RALPH D. HANEY G'IISEEE'E SIISID BY fim WA WJMA 40% THEI ATTORNEYS PATENTEDuuv 14 I972 SHEET llUF 11 DATA STATUS SELECT I ON DATA STATUS 5 SELECTION DFS-UDFIS LOGIC INVENTORS RALPH D. HANEY,

Loan:

TBIO

DIGITAL PROCESSOR This invention relates to a digital processor and, more particularly, to a digital processor constructed essentially entirely of metal-oxide semiconductor integrated circuits for use in an operation requiring a processor of this type.

Modern digital computer technology seems to be striving towards highly sophisticated high speed, low access time digital processors. For many applications, the requirement for high speed is necessary, and the cost of the processor bears a minor consideration. However, in certain applications, the speed of the processor is relatively immaterial, and cost is a major factor. Such a system, for instance, could be a commercial terminal for use, for instance, as a retail point-ofentry terminal (cash register) in a department store, or a bank tellers terminal for use in a financial institution. In these types of terminals, the transaction is still limited by the speed at which a human being can operate the terminal. In this case, it matters little whether the processor can add two numbers in ten nanoseconds or whether it takes a millisecond to add these numbers, since the operator's capability of entering the information is much slower than either of these two times.

The other consideration involved in this type of terminal, as previously mentioned, is the cost. Where one wishes to use a digital processor as part of such a terminal, it is necessary to make the cost of this type of terminal relatively competitive in price; that is, the added advantages which may be derived from using a digital processor as the heart of the terminal must not be gained at the expense of so much cost that it becomes impractical or inefficient for a prospective purchaser to purchase one of these terminals.

One good way to reduce the cost and the size of any digital system is through the use of four-phase metaloxide semiconductor (MOS) large scale integration (LSI) integrated circuits. On a given substrate of silicon, one may construct, by MOS LSI techniques, hundreds or thousands of different MOS transistor elements which operate as switches. Thus one may build a digital processor using the four-phase MOS LSI techniques on, for instance, twenty or thirty integrated circuits. The drawback when MOS integrated circuits are used is that they are relatively slow when compared to, for instance, transistor-transistor logic type integrated circuits. However, as previously mentioned, in certain applications speed is a relatively minor factor, and economy is the major consideration.

In accordance with this invention, there is provided a digital processor comprising read-only memory means for providing a serial sequence of instruction signals in a serial-by-bit manner to a memory buss. There is further provided a plurality of storage registers, each of which can assume a condition manifesting the storage thereby of at least one character of information. Each of the storage registers is capable of being selected to provide a signal indicative of a stored character of information in a serial-by-bit manner to at least one of either a destination buss or an origin buss. Each of the storage registers further is capable of being selected to be responsive to a signal appearing on an arithmetic buss. The digital processor further includes register selection means responsive to certain first ones of the instruction signals for selecting at least one of l a register to provide signals to the origin buss, (2) a register to provide signals to the destination buss, or (3) at least one register which responds to the signals on the arithmetic buss. One of the registers further has associated therewith logic means responsive to certain second ones of the instruction signals appearing on the memory bus to affect the condition of that register and responsive to certain other of the instruction signals to provide signals to the read-only memory means indicating the condition of that register.

A detailed description of the digital processor is hereinafter given with reference being made to the following figures, in which:

FIG. 1 is a general block diagram of the digital processor;

FIG. 2 is a series of waveforms illustrating the fourphase signals used in operating the various circuits included in the processor;

FIGS. 3 to 7 inclusive show various formats which the instruction signals of the digital processor can have;

FIGS. 8 through 11 illustrate, respectively, a onegate, a two-gate, a three-gate, and a four-gate which are the basic building blocks of the logic circuitry used in the digital processor;

FIG. 12 is a diagram illustrating which gate can apply signals to or receive signals from which other gate;

FIG. 13 illustrates one stage of a shift register using four-phase MOS logic;

FIG. 14 illustrates a flip-flop latch circuit using fourphase MOS logic;

FIG. 15 shows how FIGS. 16 should be placed together; and

FIGS. 16A through 16H, when placed together, illustrate a more detailed diagram of the digital processor shown in FIG. 1.

Referring now to FIG. 1, there is shown a general block diagram of a digital processor 10 constructed in accordance with this invention. The digital processor 10 operates on a 16-bit periodic cycle, and a timing network 12 provides sixteen separate timing signals, TPl through TPI6. During the time, for instance, between TPl and TF2, four separate signals are provided having four different phases of operation.

The four phases of operation are illustrated in FIG. 2 and are respectively designated 4),, (1) and d The d), and signals are applied to each integrated circuit, and means internal on each integrated circuit will generate the d, and (11 pulses from the respectively applied rb, and a, pulses. In addition, the necessary TPl-TP16 clock pulses are provided to each integrated circuit, and each of these corresponds to the time between 4:, signals.

Referring specifically to FIG. 2A, it is seen that the (b pulse is a relatively short pulse, and it occurs once each cycle of operation of the digital processor 10. The (p pulse is a longer-duration clock pulse than the 4;, pulse. (1) is another shorter clock pulse, and 4a., is a longer-duration clock pulse. The leading edges of the d), and (b pulses occur together, as do the leading edges of a, and 4:, pulses. However, the trailing edges of each of the 1b,, 11),, and 41., clock pulses occur at different times; hence the term four-phase."

Referring again to FIG. 1, the heart of the digital processor 10 is the read-only memory 14. This memory is a 4,096 word by 12-bit read-only memory. Thus, the

memory can store 4,096 12-bit characters, each of which may be an instruction or a portion of an instruction for operating the digital processor 10. The readonly memory 14 is built entirely of MOS semiconductor devices, and it is programmed during manufacture. Where a logical 1" binary digit (bit) is to be used, a transistor is provided in a matrix which can be made to act as a short circuit, and, where a logical bit is to be used, an open circuit is left.

The read-only memory 14, on command of signals applied thereto from the program counter means 16, will apply, in parallel, a series of signals indicating either logical 1" bits or logical 0 bits to the parallelto serial converter 18. The parallel-to-serial converter 18 will apply the parallel instruction signal applied from the read-only memory 14 as a serial signal to the line and from there to a memory bus 22. From the memory buss 22, the serial instruction is applied to each of several other units, which will be described hereinafter, by bussing techniques.

As previously mentioned, the location of any given instruction which can be provided by the read-only memory 14 is determined by the program counter means l6. The program counter means 16 includes an address register 24 and logic circuitry 26. The address register 24 includes a counter which will have any count therein between zero and 4,095. The particular count of the counter included in the address register 24 will determine the location in the read-only memory 14 which is to provide the instruction signal to the paralleltoserial converter 18. For instance, if the count in the counter of the address register 24 indicates the number l ,029, then the instruction in the read-only memory 14 which is located in location 1,029 will be provided as the output of the read-only memory 14. The counter in the address register 24 is of the type which, unless otherwise signaled, will increment itself by one" once each cycle. That is, after the l6 TP timing signals of any given cycle have been provided from the timing network 12, the counter in the address register 24 will increase its count by one."

However, the counter in the address register 24 is also capable, on proper signals applied thereto from the logic circuit 26, of increasing its count by a non-incremental amount. This feature is necessary for branching of the program stored in the read-only memory 14 to take place; that is, so that the program can go from, for instance, the main program to a subroutine to accomplish a certain function and then back to the main program. The purpose of this, of course, is to keep the size of the read-only memory from becoming too large. Further, the counter in the address register 24 must be capable of holding a count for more than one cycle where the time required to execute an instruction is greater than one cycle.

Before referring to the remaining portions of the digital processor 10, it will be advantageous to describe the types of instructions which are provided from the read-only memory 14. For this, reference is made to FIGS. 3 through 7, where diagrams show the five different formats of the instruction words which may be provided by the read-only memory 14.

FIG. 3 shows the D00? instruction format. This is a 12bit instruction word in which bits bl through b4 contain a four-bit operation code (OP) indicating which particular type of instruction this is. Bits b5 through b8 are a four-bit origin code (0) designating a certain register as an origin register, and bits b9 through 1712 are a four-bit destination code (D) designating one of the registers as a destination register.

FIG. 4 shows the COP instruction format. Here, again, bits bl through b4 are a four-bit operation code (OP) designating the particular type of COP instruction, and bits b5 through M2 in this instruction form an eight-bit coded constant (C) which is used in processing the instruction.

FIG. 5 shows the FPOP instruction format, and, again, bits bl through b4 thereof are a four-bit operation code (OP) determining which type of FPOP instruction is involved. Bits b5 through b8 are a four-bit port code (P) designating one of 16 ports, and bits b9 through bl2 are a four-bit function code (F) which designates a particular function to be sent to the port designated in bits b5 through b8.

FIG. 6 shows the RAOP instruction format, and, again, bits bl through b4 form a four-bit operation code (0?) indicating the particular type of RAOP instruction. Bits b5 and b6, respectively, are a two-bit constant (AB) which may designate a subinstruction to the instruction designated by the founbit code. Bits b7 through bl2 indicate a six-bit constant code (RA) which may be anywhere between plus or minus 31. If bit bl2 of this RA constant number is logical 0, the RA number is a positive number and defined by bits b7 through bl 1; if bit bl2 of the RA constant number is a logical I bit, then bits b7 through bll define the complement of the negative number of the RA constant.

FIG. 7 shows the SPOP instruction format. This instruction is a two-character instruction. Bits bl through b4 of the first character are the operation code (OP) of the particular type of SPOP instruction. Bits b5 through b8 are a four-bit port code (P) designating one of the 16 ports of the digital processor 10. Bits b9 through bl2 of the first character are a four-bit status code (S) designating a particular status which could be applied to the digital processor 10 by the port selected by bits b5 through b8. In the second character, bits bl through b4 are a four-bit function code (F) which designates a particular function which can be sent to the port designated by bits b5 through b8 of the first character. Bits b5 and b6 of the second character are a two-bit code (IT) which designates a subinstruction of the instruction defined by the OP code in bits bl through b4 of the first character. Bits b7 through bl2 of the second character form a coded RA constant of plus or minus 31 and are similar to bits b7 through bl2 shown in the RAOP instruction in FIG. 6.

The COP and RAOP instruction formats shown in FIGS. 4 and 6, respectively, may have a second character associated with them. This second character will be a 12-bit address of a location to which a branch in the program is to be made.

Since the operation code OP of each of the five instruction formats shown respectively in FIGS. 3 through 7 is four bits, there are sixteen possible main instructions which can be responded to by circuitry in the digital processor 10. In addition to these l6 main instructions, the RAOP and SPOP instruction formats,

shown in FIGS. 6 and 7, indicate that an instruction of this format can have four subinstructions. Table l is set out below, giving the sixteen main instructions of the digital processor and the various subinstructions associated with each of the main instructions. it should be noted that, in the case of the DOOP type of instruction. there are subinstructions for the cases where the D and the 0 codes are not equal to zero and for the cases where the D and the 0 codes are both equal to zero. The significance of this will be described hereinafter.

each be unique to one of 16 possible registers which may be selected. Thereafter, the MOV, ADD, SUB, or SFI function will be performed.

in the digital processor 10, there are three special types of registers which are included, and there are from zero to thirteen storage registers 34 which may be selected. The number of storage registers 34 is dependent on the particular use to which the digital processor 10 will be put. Each of the storage registers 34 in turn may be one or more characters in size, where a TABLE I Main Sub instrucinstructlon tion Code Type Operation 1 PAC COP g= (AC)+Port Address Reg; Hold port on Release Port Address. 2 C13 0001 COP (INDJtC-JND. 3 MOV 0010 DOOP (Ro)N-(Rd)1, AC, (Ro)l. (AC)-+DO; (Ro)N-+(Rd]1, AC, (Ro)1. COP If (AC)=C, Branch; otherwise continue. COP C- AC. COP (IND C IND. DOOP (Rd)N (Ro)N (Rd)1, AC; (Ro)N-.[Ro)l. (AC]D0; (Rd)N (R N-(Ro)1,AC; (Ro)N-(Ro)1. COP It for all Ci=l, (AC)i="1", ranch; otherwise continue. COP (AC) C- AC. FPOP Issue function F on Port P. DOOP (Rd)N (R0)N (Rd)1, AC; (Ro)N-+(Ro)1. (AC)-D0; (Rd)N(Ro)N- (Rd)1,AC; (RoiN-dRoll. COP If for all Ci=1", (IND)l=i", Branch; otherwise continue. S195? (AC)-CAC.

If US#S, Send F on P; Otherwise Branch by RA. If US=S, Send F on P; Otherwise Branch by RA. 1f Uses, Branch by RA; Otherwise Continue. If US=S, Branch by RA; Otherwise Continue.

The digital processor 10 includes a plurality of different types of registers, from which and to which information flows in the form of eight-bit coded character signals. The registers may be selected in response to signals provided from transfer control and register selection means 28, which includes register selection logic and an ADD/SUB circuit 32. The transfer control and register selection means 28 will respond to the MOV, the ADD, the SUB, and the SET signals, all of which are of the DOOP type shown in FIG. 3. The register selection logic 30 will decode the OP code in bits bl through b4 of the particular instruction signal applied thereto to determine whether it is a MOV, an ADD, a SUB, or a SFl' instruction.

Once the particular type of instruction is determined, then the D code and the 0 code of the instruction signal are decoded, and signals are respectively applied on lines RSDLl through RSDl-l4 and RSOLl through RSOl-l4. These lines are connected to each of the registers in the terminal which may be selected. A signal will appear on one of the RSDLl through RSDL4 lines and one of the RSDl-ll through RSDH4 lines, and on one of the RSOL] through RSOL4 lines and one of the RSOl-ll through RSOl-l4 lines. The two RSOL and RSOH signals and the two RSDL and RSDH signals will character is defined as eight binary bits.

Each of the storage registers 34 will have two outputs to which the most significant positioned character may be applied serial by bit, least significant bit first. One of the outputs is connected to an origin bus 36, and the other output is connected to a destination bus 38. lf the register selection logic 30 selects the register as an origin register by causing the RSOL and RSOH lines coupled to the register to be high, then any character which is transferred out of that register will be applied to the origin bus 36. On the other hand, if the register selection logic 30 selects the storage register as a destination register by causing the RSDL and RSDH lines coupled to the register to be high, any character which is transferred therefrom will be applied to the destination bus 38.

In the storage registers 34, the origin buss output of the register is coupled back as one input to the register. Thus, whenever the register is selected as an origin register, the output applied to the origin bus 36 is also applied to the input of the register and becomes the least significant character thereof. The storage registers 34 act, in this event, as a circular shift register. That is, when a character is provided to the origin buss 36, each of the remaining characters is increased in significance one position, and the character applied to the origin buss 36 is placed in the least significant character position of the register.

A second input of each of the storage registers 34 is coupled to an arithmetic bus 40, which is also coupled to the output of the ADD/SUB circuit 32. The storage register 34 which is selected as a destination register will respond to the signal appearing on the arithmetic buss 40 by storing, in the least significant character position thereof, the information manifested by that signal.

The origin buss 36 and the destination buss 38 are coupled as the two inputs to the ADD/SUB circuit 32. This circuit, in response to signals from the register selection logic 30, will perform either an addition, a subtraction, or a transfer of the information appearing on the origin and destination busses 36 and 38, to the arithmetic bus 40.

in addition to the storage registers 34 in the digital processor 10, there are also three special registers. These include the RAR/TA/RTC register means 42, the accumulator means 44, and an input buffer (not shown in FIG. 1) included in the input/output means 46. Each of these registers also may be selected as either an origin register or a destination register in response to the signals provided by the register selection logic 30.

The RARfTA/RTC register means 42 includes a sixcharacter RARfTA/RTC register 48 and logic circuitry 49. The register 48 is not a shift register in fact, two of the characters which can be provided thereby are not even stored in shift registers at all but merely are provided by a series of flip-flops.

The RAR/TA/RTC register 48 includes a twocharacter shift register called the RAR register 50; a two-character non-shift register called the TA register 52, which can provide two constant-value character signals on proper command; and a two-character shift register called the RTC register 54. There is no transfer from any one of the RAR register 50, TA register 52, or RTC register 54 to any other one of these registers.

Where the information from any one of the RAR register 50, TA register 52, or RTC register 54 is desired to be obtained, a signal is provided thereto from the logic circuit 49, indicating which of the characters and which of the registers is to be applied to the proper place. The two character positions of the RAR register 50 are designated the sixth and the fifth characters of the RAR/TAIRTC register 48; the two characters of the TA register 52 are the fourth and the third characters; and the two characters of the RTC register 54 are the second and the first characters.

A pointer line 1-6 is connected to each character of each register in the RAR/TA/RTC register 48 from the logic circuit 49. If the most significant character of the RAR register 50 is desired, then a signal on the pointer line 1, which is coupled to the sixth character position, will be on, and the remaining pointer line signals will be off. This will cause the most significant character of the RAR register 50 to be applied to the proper place. Similarly, if the least significant character of the TA register 52 is desired, then the pointer line 4 signal will be on, and the remaining five pointer line signals will be off; therefore, the least significant character of the TA register 52 will be applied to the proper place.

The registers respond to the pointer line 1-6 signals by applying signals indicating their stored contents back to the logic circuit 49, and, from there, they can be applied to either the origin bum 36 or the destination bus 38.

The two character positions of the RAR register 50 can be used to store a 12-bit signal indicating an address for the read-only memory 14. The twelve bits are stored as follows: bits bl through b8 are stored in the least significant character position of the RAR register 50, and bits b9 through bl2 are stored in the four least significant bit positions of the most significant character of the RAR register 50. The four most significant bit positions of the most significant character of the RAR register 50 are not used. Upon proper command, the RAR register 50 will shift the twelve bits stored therein over the line 55 to the program counter means 16 and have them inserted as the address in the address register 24. The RAR register 50 may also be used as a normal two-character storage register, and, for this usage, it can apply signals through the logic circuit 49 to either the origin bus 36 or the destination buss 38, and it can respond to signals appearing on the arithmetic bus 40 which are applied thereto through the logic circuit 49.

The TA register 52 can be used as a terminal address register. This register is not a shift register but is merely a series of flip-flops which can provide 16 bits of nonprogrammable coded information. The TA register 52 can apply its coded information through the logic circuit 49 to either the origin buss 36 or the destination buss 38, depending on whether the RAR/TA/RTC register 48 is selected as an origin register or a destination register. it is not responsive to any signals appearing on the arithmetic buss 40.

The RTC register 54 can be used as a real-time clock counter for counting a certain time; for instance, where a short wait is desired. it is a two-character, and therefore a 16-bit, shift register, so it may count a time up to 2 one times the 16-bit cycle of the digital processor 10. The RTC register 54 will respond to a signal appearing on the arithmetic buss 40 which is applied thereto through the logic circuit 49. Once each cycle, the count in the RTC register 54 will be decreased by one until it reaches zero. Periodic sampling of the RTC register 54 will be necessary to determine when the count therein is zero.

The accumulator means 44 includes a one-character accumulator register 56 and associated logic circuitry 58. The accumulator register 56 can be selected as either origin or destination by the register selection logic 30. Further, the accumulator register 56 will always be selected as a destination register whenever a MOV, ADD, 0R SUB instruction signal is provided to the memory bus 22 and detected by the register selection logic 30. Thus, where information is moved from one of the storage registers 34 to another one of the storage registers 34, for instance, the information will also be applied to the accumulator register 56. The advantage of always selecting the accumulator register 56 as responsive to the arithmetic buss 40 signal is that instructions in the read-only memory 14 may be conserved; for instance, where one wishes to move a character from one register to another register and thereafter to check the character in the accumulator to determine its value, it may require several instructions first to move it to the register, then to shift the register, then to move it to the accumulator and shift the registers again, and then to check the character. However, under the present setup, one may merely move the character to the register, and it is automatically placed in the accumulator, ready for checking.

The logic 58 portion of the accumulator means 44 is designed to be able to detect OP codes indicating the BAC, the BAT, the LAC, the LAN, and the LOR instructions. The exact operation when these instructions are detected will be described hereinafter.

The final register which may be selected by the register selection logic 30 is an input/output buffer register (not shown in FIG. 1) which is included as part of the input/output means 46. This register is used for buffering data applied to the digital processor 10 from one of the sixteen peripheral units which may be connected to the sixteen ports thereof. The information in the buffer register may be either data information or status information applied from the particular port. The information is applied to this buffer register only in response to a certain instruction.

Logic means (not shown in FIG. I) are included in the input/output means 46 and cause the input/output means 46 to respond to the OP codes of the PAC, the UNC, and the SFU instruction signals applied to the memory buss 22. The output of the buffer register in the input/output means 46 is connected to the origin buss 36 and the destination buss 48.

Another register which is included in the digital processor 10, but one which is not under the control of the register selection logic 30, is the indicator means 60. The indicator means 60 includes a single character indicator register 62 and associated logic 64. The indicator means 60 is responsive to the SIB, the C18, and the BlT instruction signals applied thereto from the memory buss 22. The SIB instruction signal can be used to cause one or more of the bits in the indicator register 62 to go from a logical to a logical l," and the CIE instruction signal can be used to cause one or more of the bits in the indicator register 62 to go from a logical l to a logical 0." The BlT instruction signal can be used to test the value of one or more bits in the indicator register 62 and to thereafter branch or continue the program in response to the results of the BlT test.

The program counter means 16 is responsive to the OP code for the BCR instruction provided on the memory buss 22.

There is further provided a memory response buss 66, which receives signals from the indicator means 60, from the input/output means 46, from the accumulator means 44, and from the transfer control and register selection means 32, and thereafter applies these signals to the logic circuit 26 in the program counter means 16. The signals applied to the memory response buss 22 are single pulse signals occurring at a given time in the T?! through TP16 cycle of operation. The response of the program counter means 16 to the signal appearing on the memory response buss 66 is determined by the time at which the pulse is applied to the memory response bus 66.

With the above general description of the digital processor in mind, a brief description of each of the sixteen basic instructions and the variations of these instructions will now be given. This description will be given with respect to the functional response of the various different means of the instructions. The detailed response of the means itself is given hereinafter. For an easier understanding of this description, reference should be made to Table I, previously given.

First, the MOV, ADD, SUB, and SFT instructions, to which the transfer control and register selection means 28 is responsive, will be considered. Each of these four instructions is of the D00? format which is shown in FIG. 3; that is, they have a four-bit D code indicating a register to be selected as a designation register, a fourbit 0 code indicating a register to be selected as an origin register, and a four-bit OP code indicating which of the four instructions is then being applied to the register selection logic from the memory buss 22.

For each of these four instructions, means are included in the register selection logic 30 for detecting a situation where all four bits of both the D code and the 0 code of the instruction are logical 0." if this situation is detected, then the eight bits which are then being stored in the accumulator register 56 are transferred to the register selection logic 30, and these will be processed by the register selection logic 30 as if they had been the eight bits in the D and the 0 portions of the instruction applied thereto from the memory buss 22. Under this option, the four least significant bits stored in the accumulator register 56 correspond to the origin register address, and the four most significant bits stored in the accumulator register 56 correspond to the destination register address.

On the assumption that the D and 0 codes of the instructions are non-zero, or, alternatively, assuming that the accumulator character had already been transferred to the register selection logic 30, a description of the operation involved for each of the MOV, ADD, SUB, and SFT instructions, to which the transfer control and register selection means 28 responds, will now be given. The MOV instruction is an instruction for moving a character from one selectable register to another selectable register. The character is moved from the most significant character position of the selected origin register and applied to the origin buss 36. At the same time, this character is circularly shifted and applied back to the input of the selected origin register into the least significant character position thereof. The character being transferred is applied from the origin buss 36 through the ADD/SUB circuit 32 and applied unchanged in content to the arithmetic buss 40. From there, it is applied into the accumulator register 56 and into the least significant character position of the selected destination register. The remaining characters in the selected destination register are increased in significance one position, with the most significant character previously stored disappearing.

Where the ADD instruction has been recognized by the register selection logic 30, the selected origin register will apply its most significant character to the origin buss 36 and, at the same time, to its least signifi cant character position, while at the same time increasing the significance by one of each of its remaining characters. Similarly, the destination register will apply its most significant character to the destination buss 38 while increasing the significance of its other characters by one position. The ADD/SUB circuit will then respond to the character signals appearing on the origin buss 36 and the destination buss 38 by performing a binary addition of these characters and apply a signal manifesting the added sum to the arithmetic bus 40. The arithmetic bus 40 signal is then stored in the accumulator register 56 and the least significant character position of the selected destination register.

For the SUB instruction, the origin and destination registers are selected to apply their most significant characters to the origin buss 36 and the destination buss 38, and the binary value manifested by the character signal appearing on the origin buss 36 is subtracted from the binary value manifested by the character signal appearing on the destination buss 38 in the ADD/SUB circuit 32. A signal manifesting the binary difference is then applied to the arithmetic buss 40 to be stored in the accumulator register 56 and the lowest significant position of the selected destination.

The SF! instruction causes a circular shift to occur in the selected register. In the SFT instruction signal, the code of the instruction designates the selected register, while the D code designates the number of shifts, by character position, which are to occur in the selected register. For instance, if the D code of the instruction applied to the register selection logic 30 from the memory buss 22 had been DUI I and the 0 code had been 0100, this would indicate to the register selection logic 30 that the register four is to have the characters therein circularly shifted three character positions upward; that is, the three most significant characters are shifted to the three least significant character positions, and all of the characters are increased three positions in significance.

Another version of the SPT command is in the event that only the D code of the instruction is binary zero. In this event, the SPT instruction will cause all of the characters stored in the selected register, as determined by the 0 code of the instruction, to become binary zero, Hence, this is a subinstruction of the SFT instruction which is designated as the CLR, or clear, subinstruction. When the CLR subinstruction is detected, a signal will appear on the CLEAR line from the register selection logic 30 and be applied to the selected origin register to clear that register (except for the ARlTHMETlC register 48, as will be explained hereinafter).

The time required to perform the normal MOV, ADD, or SUB instructions is equal to one cycle of the timing network 12. If the D and 0 codes of the instruction are O000, then an additional cycle is required in order to move the contents of the accumulator register 56 to the register selection logic 30. For the SFT instruction, the time required to perform the instruction depends on the D code of the instruction (number of character positions shifted). If the D code is 0-0-0-0 (CLR instruction) or 0-0-0-1, then one cycle is needed; if the D code is 0-Ol0 or 0-0-1-1, two cycles are needed; if the D code is O-l-O-O or O-l-O-l, three cycles are needed, etc. if both the D code and the 0 code are 0-0-0-0, an additional cycle is required to transfer the contents of the accumulator register 56 to the register selection logic 30.

The register selection logic 30 will send a response over the memory response buss 66 after the instruction has been performed, instructing the program counter means 16 to cause the next sequential instruction from the read-only memory 14 to be read.

The accumulator means 44 responds to five instructions, which are the BAC, the BAT, the LAC, the LAN, and the LOR instructions. Each of these instructions are of the COP format; that is, there are an eight-bit C code defining a binary constant and a four-bit OP code designating the particular instruction.

The response of the logic 58 of the accumulator means 44 to the LAC instruction is to cause the constant designated by the C code of the instruction to be stored in the accumulator register 56. The LAN instruction will cause a logical AND to be performed between the accumulator register 56 stored character and the C code of the instruction, with the resultant being placed back into the accumulator register 56 as the new stored character thereof. Similarly, the LOR instruction will cause a logical OR to be performed between the accumulator register 56 character and the character defined by the C code of the instruction, with the resultant placed back in the accumulator register 56 as a new stored character.

For the LAC, the LAN, and the LOR instructions, the time required to perform the operation is equal to one cycle of the tinting network 12, and the logic circuit 58 sends a response over the memory response buss 66 instructing the program counter means to read the next sequential instruction in the read-only memory 14.

The BAC and the BAT instructions will cause a branch of the program counter means 16 to occur under certain conditions. In the case of a BAC instruction, the branch is to occur if, for every logical l in the C code, there is a corresponding logical l in the accumulator register 56. If a branch is to occur for either of these instructions, the address of where the branch is to be made is given in the next sequential location of the read-only memory 14. if no branch is to occur, this next sequential location is meaningless, and the program should continue with the instruction found in the location following it.

If no branch is to occur, the logic circuit 58 applies a signal over the memory response buss 66 indicating that no absolute branch is to be taken. The program counter means 16 responds to this signal by allowing the counter in the address register 24 t0 increment itself one extra time before reading an instruction from the read-only memory 14. If a branch is to occur, the logic circuit 58 applies a signal over the memory response buss 66 indicating that an absolute branch is to occur. The program counter means 16 responds to this signal by causing the next readonly memory location to be read and placed on the memory buss 22. Thereafter, the program counter means places the code of the memory buss 22 signal in the address register 24 and reads the instruction at the location manifested by the memory buss 22 signal. The time required to perform a BAC or BAT instruction is two cycles of the timing network 12.

Logic (not shown) in the input/output means 46 will respond to the PAC, the UNC, and the SFU instructions appearing on the memory buss 22. From Table i, it is seen that the PAC instruction is of the COP type, as shown in FIG. 4, and that there are two subinstructions for the PAC instruction, which are the PAL and PAR subinstructions. The PAL subinstruction is recognized when the C code of the PAC instruction is a binary 1," or O-O-O-O-O-O-O-l, and the PAR subinstruction is recognized when the C code of the PAC instruction is a binary 2, or -0-0-0-0-0-1-0. The occurrence of a PAL subinstruction will cause the ace umulator character to be transferred to the input/output means 46 to lock it on to the port defined by the four least significant bits of the accumulator character. In executing any subsequent instructions to the PAL subinstruction, any P codes in the instructions will be ignored, and all instructions will respond to the port which has been locked on by the PAL subinstruction signal. The PAR subinstruction, on the other hand, will release the locked-on port, so that normal operations can continue thereafter.

The PAC instructions require one cycle to be performed, and the response on the memory response buss 66 is to read the next instruction.

The next instruction to which the input/output means 46 will respond is the UNC instruction, which has the two character SPOP format shown in FIG. 7. This instruction, it should be recalled, is a two character instruction, and it has the [T code in bits b and b6 of the second character, indicating that four suhinstructions of this main instruction can exist. These su binstructions are the FFB subinstruction, the FTB subinstruction, the BSF subinstruction, and the BST subinstruction.

Aftcr the OP code of the signal on the memory buss 22 is recognized as the first character of a UNC instruc tion, the input/output means 46 will cause the status signal, one of which is continually being applied to each of the sixteen ports of the digital processor 10, which is applied to the port defined by the P code of the first character, to be compared with the S code in the first character. If the S code of the first character is equal to the status code applied to the selected port of the input/output means 46, an equal compare flag is set; otherwise the flag is not set.

Thereafter, the second character of the instruction is applied to the memory buss 22, and the input/output means 46 responds to the IT code of the second character to determine which UNC subinstruction is involved. If the [T code is 1-1, then the FFB subinstruction is present and requires that, if the code of the status signal applied to the selected port is not equal to the S code, then the function signal defined in the F code of the second character is to be sent to the peripheral unit coupled to the selected port P. If the unit status code and the S code of the first character are equal, a branch by the RA constant should be made.

If the IT code is 1-0, then the FT B subinstruction is present. For this subinstruction, if the unit status code and the S code are the same, then the function signal defined by the F code should be sent to the selected port; otherwise a branch by the RA constant should be made. If the IT code is 0-0, then the BSF subinstruction is present, and this indicates that, if the unit status code and the S code of the instruction are unequal, a branch by RA should be made; otherwise, the program counter should increment itself by one" and continue in the normal manner. Finally, if the IT code is 0-1, the BST subinstruction is present, and this indicates that, if the unit status code is equal to the S code of the instruction, a branch by RA should be made. Otherwise, the program counter should increment itself and continue in the normal manner.

The time required to perform any of the UNC subinstructions is two cycles of operation. The response which the input/output means applies to the memory response buss 66 for the first character of the UNC instruction will instruct the program counter means 16 to apply a signal to the memory bus 22 indicating the character stored in the next read-only memory 14 location and to instruct the other means in the digital processor 10 not to treat it as an instruction. After the second character of the UNC instruction is applied to the memory bus 22, the input/output means 46 sends a signal over the memory response bus which instructs the program counter means 16 to either take a relative branch and proceed with the program, or merely cause the next sequential instruction to be read from the read-only memory 14.

The third type of instruction to which the input/output means 46 responds is the SFU instruction, which is an instruction of the FPOP format shown in FlG. 5. This instruction, when detected by the input/output means 46, will cause a function signal having the F code of the instruction to be sent to the peripheral unit coupled to the port defined by the P code of the instruction. An example of where this instruction could be used would be to instruct the printer to print a character. The character could be subsequently sent, but the printer would place itself in a condition to receive that character and print the symbol defined by the character signal code subsequently sent.

The time required to perform the SFU instruction is one cycle of operation, and the signal applied to the memory response bus 66 instructs the program counter means 16 to cause the next sequential instruction in the read-only memory to be read.

The indicator means will respond to the SIB, CH3, and BlT instruction signals applied thereto from the memory buss 22. Each of these three instructions has the COP format; that is, they have the four bit OP code, specifying which type of instruction, and the eight bit C code, which is an eight-bit constant.

The response by the logic 64 of the indicator means 60 to the SIB instruction is to cause a logical OR to be performed between the eight-bit character stored in the indicator register 62 and the eight bits in the C code of the instruction, with the resultant being stored in the indicator register 62. The response to the C18 instruction is to cause a logical AND to be performed between the eight-bit character stored in the indicator register 62 and the logical inversion of the eight bits of the C code of the instruction, with the resultant being stored in the indicator register 62.

The SIB instruction generally is used to set one or more of the bits in the indicator register 62 to a logical l state from a previous logical 0" state. This is done by having the C field contain a logical l in the position corresponding to the desired bit to be set. Therefore, the logical OR function would cause a logical l bit to be thereafter stored in the proper position of the indicator register 62. The CIB instruction is generally used to clear the indicator register of one or more logical 1" bits. In this case, the desired bits to be cleared would have a logical l in the C" code of the instruction in the positions thereof corresponding to the bit or bits to be cleared. After the C" code is logically inverted and the logical AND is performed, the result is a logical replacing the previous logical l The time required for the SIB and CH3 instructions in one cycle of operation, and the response on the memory response bus 66 instructs the program counter means 16 to read the next instruction from the read-only memory 14.

A third signal to which the indicator means 60 responds is the BIT instruction. The logic circuit 64 of the indicator means 60 tests the contents of the indicator register 62 to see whether, for every logical l bit in the C code, there is a corresponding logical l bit in the indicator register 62. If the test is positive, a branch in the program to the location indicated by the contents of the next sequential location of the readonly memory 14 is required. If the results of the test are negative, the next character in the read-only memory 14 should be skipped, and the one following it should be read and treated as an instruction signal.

The response on the memory response bus 66 for the BIT instruction is the same as it was for the BAC and BAT instructions previously described. The time required to perform the BAT instruction is two cycles of operation.

The final one of the sixteen instructions which can be applied from the read-only memory 14 to the memory buss 22 is the BCR instruction, which is a branch instruction. This instruction is of the RAOP format shown in FIG. 6, and there are four subinstructions associated therewith, which depend on what the BA code If the BA code is l-(), the BUC subinstruction occurs and indicates that the address register 24 is to change its count by the RA factor. If the BA code is I-l, the BSR subinstruction occurs. The response to the BSR subinstruction is for an absolute branch to be made and for the contents of the address register 24 to be modified to address the next sequential instruction of the read-only memory 14 and then stored in the RAR register 50, with the eight least significant bits of the address being stored in the least significant character of the RAR register 50 and the four most significant bits of the address to be stored in the four least significant bit positions of the most significant character of the RAR register 50. The logic circuit 26 will then respond to the next occurring signal applied to the memory bus 22 and cause the address register 24 to assume the count manifested by this signal. Thereafter, the readonly memory 14 will begin applying instruction signals from the branched-to address specified by the previously-mentioned following signal.

A third subinstruction of the BCR instruction is the BIR subinstruction, which occurs when the BA code is 0-0. The response of the program counter means 16 to the BIR subinstruction is to cause the contents of the RAR register 50 to be modified by the RA constant and, as modified, to be placed in the address register 24 as a new address thereof. This instruction can be used for returning the address register 24 to the main logic after it had been branched therefrom by the BSR subinstruction.

The final subinstruction of the BCR instruction is the BIS subinstruction, which occurs when the BA code is O-l. The response to this instruction is to have the contents of the address register 24 modified to address the next sequential instruction of the read-only memory 14 and then stored in the RAR register 50, and to have the contents of the RAR register 50 modified by the RA constant and then stored in the address register 24 to become the new address of the address register 24.

The time required to perform the BCR instruction is two cycles of operation. The response on the memory response bus 66 for the BSR subinstruction instructs the program counter means to cause the next sequential location of the read-only memory to be read and applied to the memory bus 22 but not be treated as an instruction signal by the means responsive to instruction signals. The response on the memory response buss 66 for the BUC, the BIR, and the BIS subinstructions instructs the program counter means to adjust the count of the counter in the address register 24 by the RA constant and to proceed normally from the new address.

Before an understanding of the detailed diagram of the digital processor 10, shown in FIGS. 16A through 16H, can be had, a general understanding of four-phase MOS logic circuitry is necessary, since the detailed illustration in FIGS. 16A through 16H will consist of labeled blocks of logic for which equations and operation, but not detailed circuitry, will be given. The following description concerning FIGS. 8 through 13 will explain the circuits which may be constructed in response to the logical equations which will be given.

FIGS. 8 through 11 show the basic building blocks used in four-phase MOS logic circuitry. These building blocks are respectively called I," 2," 3," or 4" gates and are respectively shown in FIG. 8, FIG. 9, FIG. 10, and FIG. 11. In FIG. 8, the 1 gate shown includes a first MOS transistor 100, which is designated as a load transistor; a second MOS transistor 102, which is designated an isolation transistor; and a series of MOS transistors connected together to form a logic circuit 104. Examples of the form circuit 104 can take will be hereinafter given in more detail. The gate electrode of the load transistor is connected to the drain electrode thereof, and both of these are connected to the d, signal, shown in FIG. 2A. The source electrode of the load transistor 100 and the drain electrode of the isolation transistor 102 are coupled together, and the output 0 from the l gate is taken from this connection. The source electrode of the isolation transistor 102 is connected to the drain electrodes of at least some of the transistors in the logic circuit 104, and the source electrodes of at least some of the transistors in the logic circuit 104 are connected to the d), signal. The gate electrode of the isolation transistor 102 is connected to the signal, and the gate electrodes of the transistors in the logic circuit 104 are connected to the input signals A through N. A general statement concerning the configuration of the logic circuit 104 would be that, wherever two signals are to have a logical AND performed therebetween, the transistors to which those signals are applied will be connected in series, and, wherever two signals are to have a logical OR performed therebetween, the transistors to which those signals are applied will be connected in parallel. The output signal 0 from a l gate can be written as a function of the various input signals followed by a slash, indicating that

Claims

1. A digital processor comprising read-only memory means for providing a serial sequence of instruction signals in a serial-by-bit manner to a memory buss; a plurality of storage registers each of which can assume a condition manifesting the storage thereby of at least one character of information, each of said registers being capable of being selected to provide a stored signal indicative of a stored character of information in a serial-by-bit manner to at least one of either a destination buss or an origin buss, each of said registers further being capable of being selected to respond to a signal appearing on an arithmetic buss; register selection means responsive to certain first ones of said instruction signals for selecting at least one of (1) a register to provide signals to said origin buss, (2) a register to provide signals to said destination buss, or (3) at least one register which responds to the signals on said arithmetic buss; one of said registers further having associated therewith logic means responsive to certain second ones of said instruction signals appearing on said memory buss to affect the condition of said register and responsive to certain other of said instruction signals to provide signals to said read-only memory means indicating the condition of said one register.

2. The invention according to claim 1 wherein said read-only memory means includes means responsive to certain of the signals provided to said read-only memory means by said one register for affecting the sequence of the instruction signals provided by said read-only memory means.

3. The invention according to claim 2: wherein said signal is provided to said read-only memory from said one register through a memory response buss; and wherein said register selection means provides a signal to said read-only memory means through said memory response buss.

4. The invention according to claim 1 wherein said one register is always selected along with another one of said registers to be responsive to the signal appearing on said arithmetic buss for selected ones of said certain first instruction signals.

5. The invention according to claim 4 wherein said processor further includes an adder/subtractor means which responds to the occurrence of any one of said selected ones of said certain first instruction signals, in such a manner that any signals caused to appear on at least one of said origin buss or said destination buss are processed thereby in a predetermined manner in accordance with which particular one of said selected certain first instruction signals occurs, said adder/subtractor means thereafter providing a signal to said arithmetic buss.

6. The invention according to claim 5: wherein said register selection means and said adder/subtractor means respond to a first one of said selected ones of said certain first instruction signals to cause information signals to be applied from a selected origin register through said origin buss to said adder/subtractor means and from a selected destination register through said destination buss to said adder/subtractor means, said adder/subtractor means adding the information manifested by the origin buss and destination buss signals and applying a signal manifesting the added information through said arithmetic buss to said register selected to be responsive to said arithmetic buss signal and to said one register; wherein said register selection means and said adder/subtractor means respond to a second one of said selected ones of said first instruction signals to cause information signals to be applied from a selected origin register through said origin buss to said adder/subtractor means and from a selected destination register through said destination buss to said adder/subtractor means, said adder/subtractor means subtracting the information manifested by the signal appearing on said origin buss from the information manifested by the signal appearing on said destination buss and applying a signal manifesting the subtracted information through said arithmetic buss to said register selected to be responsive to said arithmetic buss signal and to said one register; and wherein said register selection means and said adder/subtractor means respond to a third one of said selected ones of said instruction signals to cause information signals to be applied from a selected origin register through said origin buss to said adder/subtractor means, said adder/subtractor means causing a signal manifesting the same information to be applied through said arithmetic buss to a register selected to be responsive to said arithmetic buss signal and to said one register.

7. The invention according to claim 6: wherein said first, second, and third ones of said selected first instructions include codes designating the operation to be performed in response to the instruction being provided, which register is to be selected as a destination register to apply a signal to said destination buss and which register is to be selected as an origin register to apply a signal to said origin buss and to be responsive to the signal appearing on said arithmetic buss; wherein said register selection means selects said origin and destination registers according to the codes which designate the registers to be selected as origin and destination of said instruction then being provided in the event said codes are not respectively a first certain number, including zero, and a second certain number, including zero, and performs the operation designated by the code designating said operation; and wherein said register selection means selects said origin and destination registers according to a code stored by said one register in the event the codes of said instruction then being provided which designate said origin and destination registers are respectively said first and second certain numbers, and performs the operation designated by the code designating said operation to be performed.

8. The invention according to claim 6: wherein each of said selectable registers includes at least one stage, each of said stages being capable of storing a character of information; and wherein said signal applied to said destination buss from said selected destination register manifests the character stored in the most significant stage thereof, said information applied to said origin buss from said selected origin registers manifests the character stored in the most significant stage thereof, all other characters in said selected registers being increased one stage in significance.

9. The invention according to claim 8 wherein the signal manifesting information applied tO said origin buss from said selected origin register is also applied to the least significant stage of said origin register to cause that information to be stored therein.

10. The invention according to claim 1: wherein each of said selectable registers includes at least one stage, each of said stages being capable of storing a character of information; wherein one of said instructions has first, second, and third portions which respectively convey information concerning an operation code, a register selection code, and a constant number code; wherein, in the event neither said register selection code or said constant number code is respectively a second certain number, including zero, or a third certain number, including zero, said register selection means responds to said operation code portion of said one instruction by selecting a register according to the register selection code portion of said one instruction and by causing the characters stored by said selected register to be circularly shifted a number of character positions specified by the constant number code of said one instruction; wherein, in the event said constant number coded portion of said one instruction manifests a first certain number, said register selection means responds to said operation code of said one instruction by selecting a register according to the register selection code of said instruction and clearing said selected register; and wherein, in the event said register selection code of said one instruction manifests said second certain number and said constant number code of said one instruction manifests said third certain number, said register selection means responds to said operation code of said one instruction by selecting a register according to a code stored in said one register and circularly shifting the characters in said selected register a given number determined by another code stored in said one register.

11. A digital processor comprising: a memory buss; a memory response buss; an arithmetic buss; an origin buss; a destination buss; read-only memory means for providing a serial sequence of coded instruction signals in a serial-by-bit manner to said memory buss; a plurality of storage registers each of which can assume a condition manifesting the storage thereby of at least one coded character of information, each of said registers being capable of being selected to provide a signal manifesting a stored character of information in a serial-by-bit manner to at least one of either said origin buss or said destination buss, each of said registers further being capable of being selected to respond to a signal appearing on said arithmetic buss; register selection means coupled to said memory buss, said memory response buss, said arithmetic buss, said origin buss, and said destination buss and responsive to first certain ones of said coded instruction signals appearing on said memory buss for selecting at least one of (1) a register to provide a signal to said origin buss, (2) a register to provide a signal to said destination buss, and (3) a register to respond to signals appearing on said arithmetic buss to store the character manifested by said arithmetic buss signal; operating means coupled to said origin, destination, and arithmetic busses and to said register selection means for operating on signals appearing on said origin and destination busses in a manner determined by the response of said register selection means to an instruction signal and to apply a signal indicative of the results of the operation performed to said arithmetic buss; and accumulator register means coupled to said memory buss, said memory response buss, said origin buss, said destination buss, and said arithmetic buss, and to said register selection means for storing at least one coded character of information, said accumulator register means capable of being selected by said register selection means, Said accumulator register means further being responsive to second certain ones of said coded instruction signals in a manner (1) to affect the coded condition of said character stored thereby or (2) to apply a signal through said memory response buss to said read-only memory means indicating the coded condition of said character stored thereby, said read-only memory means responding to said signal applied thereto from said accumulator register means to affect the sequence of said instruction signals provided thereby.

12. The invention according to claim 11 wherein said accumulator register means is selected to be responsive to a signal appearing on said arithmetic buss and to store the character manifested by that signal whenever one of said storage registers is selected to be responsive to said signal appearing on said arithmetic buss.

13. The invention according to claim 11: wherein said second certain ones of said instruction signals each have first and second coded portions which respectively manifest an operation to be performed and a constant number associated with said operation to be performed; wherein said second certain instruction signals, which have a first coded portion manifesting that the operation to be performed is to affect the coded condition of the character stored by said accumulator register means include instructions for causing (1) the constant number of said second portion to be stored by said accumulator register means, (2) the logical AND result of said constant number and said stored character to replace said stored character, and (3) the logical OR result of said constant number and said stored character to replace said stored character; and wherein said second certain instruction signals which have a first coded portion manifesting that a signal is to be applied to said read-only memory means indicating the coded condition of said character stored in said accumulator register means include instructions for causing said signal to be applied in the event (1) the stored character and the coded constant portion of said instruction signal are the same, or (2) the stored character has a logical bit of one type in each bit position that said constant has a logical bit of one type.

14. The invention according to claim 13: wherein signals are applied to said memory response buss after said operating means has completed operating on the signals applied thereto and after said accumulator means has affected the condition of its stored character; wherein said read-only memory means is inhibited from providing another instruction signal until at least after a signal is applied to said memory response buss; and wherein the signals applied to said memory response buss convey different meanings depending upon the time during which they are applied thereto.

15. A digital processor comprising: read-only memory means having a plurality of multibit storage locations, there being a multibit coded instruction stored in each of said locations, said read-only memory means being responsive to a coded location selection signal which is applied thereto to provide a signal manifesting the coded information stored in a then selected location thereof, the code of said location selection signal determining said then selected location; address control means including a counter which can have the count thereof changed by an incremental amount or a nonincremental amount, said address control means providing said location selection signal to said read-only memory means, the code of said location selection signal being a function of the then existing count of said counter, said address control means being capable of providing an address signal manifesting a function of the then existing count in said counter in response to a first one of said read-only memory signals being applied thereto, said first read-only memory signal causing the count in said counter to be nonincrementAlly changed; and return address register means responsive to said first read-only memory signal capable of performing at least one of (1) storing information which is a function of the address manifested by said address signal in response to an address signal applied thereto from said address control means, and (2) providing a return address signal which manifests the information being stored thereby to said address control means, said return address signal causing the count in said counter to nonincrementally change to a value which is a function of the information manifested by said return address signal.

16. The invention according to claim 15: wherein said first read-only memory signal includes, as a portion thereof, coded information manifesting a constant value, including zero; and wherein said address control means is responsive to said first read-only memory signal to cause the count in said counter to change to a value which is the information manifested by said return address signal as modified by said constant value.

17. The invention according to claim 15: wherein said first read-only memory signal causes said address signal to be provided by said address control means, said return address register means responding to said address signal by storing the information manifested by said address signal; an wherein the count in said counter is nonincrementally changed to a count manifested by the next sequential read-only memory signal.

18. The invention according to claim 15 wherein said first read-only memory signal causes said address signal to be provided by said address control means and causes said address control means to be responsive to said return address signal to cause the count in said counter to change to a value which is manifested by said return address signal.

19. The invention according to claim 18: wherein said first read-only memory signal includes, as a portion thereof, a coded constant number, including zero; and wherein said counter changes its count to a value manifested by said return address signal, as modified by said constant number.

20. The invention according to claim 15 wherein said address control means is responsive to a said read-only memory signal, which includes, as a portion thereof, information manifesting a constant number, including zero, for causing the count of said counter to be modified by said constant number.

21. A digital processor capable of having connected thereto a plurality of peripheral units each of which can apply signals to or receive signals from said digital processor comprising: a memory buss, a memory response buss, an arithmetic buss, an origin buss, and a destination buss, each of said busses being capable of coupling a serial-by-bit signal from one selected point in said digital processor to another selected point in said digital processor; read-only memory means for providing instruction signals to said memory buss in response to instruction selection signals applied thereto; instruction selection means responsive to signals applied thereto from said memory buss and said memory response buss for providing said instruction selection signals to said read-only memory; a plurality of selectable storage registers each of which includes at least one stage in which a multibit digital character can be stored, each of said selectable storage registers being connected to said origin buss, said destination buss, and said arithmetic buss, each of said selectable registers being capable of being selected to apply a signal manifesting the character stored in the most significant stage thereof to one of either said origin buss or said destination buss, and when selected to apply a signal to said destination buss to store, as the least significant character thereof, the information manifested by the signal appearing on said arithmetic buss; input/output means coupled to said memory buss, said memory response buss, said arithmetic buss, said origin buss, and said destination buss, including logic means responsive to said instruction signal capable of either applying signals to a selected one of said peripheral units or receiving signals from a selected one of said peripheral units, said selected peripheral unit being selected by said logic means responding to said instruction signal, said signal applied to said selected peripheral unit being determined by at least one of the response of said logic means to said instruction signal or said input/output means being selected to be responsive to the signal appearing on said arithmetic buss, said signal applied to said input/output means by said selected peripheral unit being either compared with a signal derived from said logic means response to said instruction signal or being applied to one of said origin or destination busses, in the event said signal applied to said input/output means is compared with said signal derived from said logic means response to said instruction signal, said logic means applying either a signal to said memory response buss indicating the results of the comparison or a signal, derived from said logic means responding to said instruction signal, to said selected peripheral unit; and operating means responsive to said instruction signal for selecting at least one of which selectable storage register is to apply signals to said origin buss, which selectable register is to apply signals to said destination buss, whether said input/output means is to be selected to apply a signal to said origin buss or said destination buss, or whether said input/output means is to be selected to be responsive to a signal appearing on said arithmetic buss, said operating means further being responsive to any signals appearing on said origin buss and said destination buss to apply a signal to said arithmetic buss after operating on said signals in accordance with a logical response to said instruction signal.

22. The invention according to claim 21 wherein said instruction signal appearing on said memory buss which causes said input/output means logic to respond thereto is one of a first or a second type, said first type including coded information manifesting the type of instruction, a peripheral unit to be selected, and a signal to be applied to said peripheral unit, said second type of instruction including coded information manifesting the type of the instruction, a peripheral unit to be selected, a code to be compared with the code manifested by a signal applied to said input/output means from the selected peripheral unit, a subinstruction code manifesting action required as a result of the comparison to be made, a code manifesting a signal to be sent to said peripheral unit for certain of said subinstruction codes when the comparison to be made is one result and a code manifesting a constant value which causes said instruction selection means to affect the instruction selection signal applied to said read-only memory means for said certain subinstruction codes where said comparison to be made is another result and where other of said subinstruction codes occur and the comparison to be made is one result.

23. The invention according to claim 22: wherein said digital processor further includes an accumulator means which can be selected to apply a signal to either said origin buss or said destination buss manifesting a character of information stored thereby; and wherein said input/output means further is responsive to the provision of a third type of instruction signal on said memory buss for causing the logic means thereof to lock one peripheral unit thereto and perform any subsequent instruction signals with respect to said one peripheral unit regardless of any code manifesting a peripheral unit to be selected, said one peripheral unit being determined by said logic means response to a signal manifesting the code of the character stored in said accumulator means.

24. A digital processor comprising: memory means for prOviding a sequence of serial by bit coded memory signals in response to the code of a program control signal applied thereto; program control means for providing a coded program control signal in which the code thereof may be nonincrementally changed upon command of a branch signal; logic means responsive to said coded memory signals for performing a logical operation and providing one of a series of signals, each signal of said series of signals occurring at a different time, one of said series of signals being said branch signal; and coupling means for coupling said logic means signal to said program control means, said program control means, in response to said branch signal nonincrementally changing the code of said program control signal.

25. The invention according to claim 24 wherein the code of said program control signal is changed in accordance with said sequence of coded memory signals whenever said branch signal is provided by said logic means.

26. The invention according to claim 24 wherein said logic means signals are pulse signals occurring at specified times and the response of said program control means to nonincrementally change the code of said program control signal occurs when said branch signal occurs at a first specified time.

27. The invention according to claim 30: wherein said memory means stores a plurality of multibit digital words in sequentially ordered locations each of which are defined by the code of said program control signal; and wherein said program control means includes additional means coupled to said logic means and responsive to said logic means signal for identifying a word read from said memory means as being an instruction word to which said logic means is to respond or a branch word to which said program control means is to nonincrementally change the code of said program control signal, said additional means identifying said word read from said memory means in accordance with the time said logic means signal occurs.

28. The invention according to claim 27 wherein said logic means includes test register means which stores a given multibit digital word, said test register means being responsive to one of said instruction words that includes a multibit digital constant to determine if said given word has a certain relationship with said constant, said test register means providing a signal to said coupling means during a first given time whenever said certain relationship exists and providing a signal to said coupling means during a second given time whenever said certain relationship does not exist, said program control means responding to said test register means signal which occurs during said first given time by reading the next sequential word from said memory and causing said next sequential word to become the code of said following program control signal, said additional means identifying said next sequential word as being a branch word.

29. The invention according to claim 28 wherein said program control means includes means for ignoring said next sequential word in the event said test register means signal occurs during said second given time and reads the word following said next sequential word, said additional means including means for identifying said word following said next sequential word as an instruction word.

30. The invention according to claim 29 wherein said logic means includes other means which stores a multibit digital signal and responds to a two word instruction signal which includes a special coded portion in each word thereof, said other means responding to said first word by providing said logic signal to said coupling means during a third time and by determining whether the special coded portion of said first word is identical to the stored multibit signal, said program control means responding to said logic means signal occurring during said third time to cause the next sequentially ordered word to be read and not treated as an instruction signal, said loGic means responding to said second word by providing said logic means signal to said coupling means during a fourth time in the event said determination was one way and providing said logic means signal to said coupling means during a fifth time in the event said determination was another way, said program control means responding to said logic means signal provided during said fourth time by altering the code of said program control signal by an amount determined by the special coded portion of said second word and said program control means responding to said logic means signal provided during said fifth time by incrementing by one the code of said program control signal.

31. The invention according to claim 30 wherein said fourth time occurs prior to the time said special coded portion of said second word is serially provided by said memory means.