US3729820A - Method for manufacturing a package of a semiconductor element - Google Patents

Method for manufacturing a package of a semiconductor element Download PDF

Info

Publication number
US3729820A
US3729820A US00017207A US3729820DA US3729820A US 3729820 A US3729820 A US 3729820A US 00017207 A US00017207 A US 00017207A US 3729820D A US3729820D A US 3729820DA US 3729820 A US3729820 A US 3729820A
Authority
US
United States
Prior art keywords
gold
layers
package
layer
metallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US00017207A
Inventor
T Ihochi
T Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of US3729820A publication Critical patent/US3729820A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • a metallized layer of molybdenum-manganese is formed on a ceramic plate, and a gold plating is applied to this metallized layer to form fitting portions for a semiconductor substrate, wirings and external lead-out electrodes.
  • This package has the following disadvantages shown in an environmental test. Due to pinholes, imperfectly plated portions, and scars in the gold plating layer, the metallized layer of molybdenum-manganese having a large ionization tendency is corroded by a localized galvanic action.
  • the metallized layer suffers from the breakage of wires or a degradation of its mechanical strength, or precipitations (hydroxides of molybdenum and manganese) extending over the surface of the ceramic plate cause deterioration of the insulation resistance between the metallized wirings.
  • the insulation resistance of metallized layers with 1 mm gap therebetween drops from Qprior to a high temperature and moisture test at 80C with 90 percent moisture for 168 hours to about 10" (I after the test.
  • An object of this invention is to provide a method of manufacturing a highly reliable package for semiconductor elements at a low price.
  • Another object of this invention is to provide a method of preventing the corrosion of a metallized layer extending over the surface ofa flat package which accommodates an integrated circuit.
  • a method of manufacturing a package having a casing of a semiconductor element wherein a conducting lead is attached to one end of a metallized layer leading out from the casing to the surface of the package; the metallized layer and conducting lead are both plated with gold; and finally the gold plated layers are dipped into a lead-tin solder bath to replace the gold plated layers on the surfaces of the metallized layer and conducting lead by lead-tin soldered layers, thereby preventing the corrosion of the metallized layer.
  • FIGS. 1 to 5 show the cross sections of the manufacturing steps of a flat package according to one embodiment of this invention.
  • a body of package 1 as shown in FIG. 1 is prepared.
  • This body 1 is formed by stacked ceramic sheets 2, 3 and 4 whose major ingredient is alumina or beryllium oxide and whose thickness is 0.05 to 1 mm, then by hot-pressing and sintering these sheets at 1,500 to 1,600C.
  • a metallized layer 8 is preliminarily formed on a portion of the sheet 2 where a semiconductor substrate is to be disposed.
  • the metallized layers 5 and 6 extend over the surface of the sheet 3.
  • the center portion of the sheet 3 corresponding to the metallized layer 8 is perforated to expose the same.
  • the sheet 4 is annularly formed to surround the prescribed surface area of the sheet 3.
  • a metallized layer 7 is formed on the major surface of the sheet 4.
  • the metallized layers 5, 6, 7 and 8 are formed by the use of the well-known screen printing method, i.e., coating a metal ink mainly consisting of molybdenum-manganese on the prescribed surfaces of
  • 11 and 12 having a thickness of 2 to 7 p. are formed on the surfaces of the metallized layers 5, 6, 7 and 8 respectively, as shown in FIG. 2.
  • leads 13 and 14 are connected to the ends of the nickel-plated metallized layers 5 and 6 respectively.
  • 18b, 19a, 19b, 16 and 17 with thickness of about 1 to 4 ,u. are formed on the surfaces of leads l3 and 14 and of nickel layers 9a, 9b, 10a, 10b, 11 and 12 respectively.
  • These gold plated layers are formed by the electroplating method in the same way as the above nickel-plated layers.
  • the gold layers 18a, 20, 19a and 21 positioned outside the ceramic plate 4 are dipped in a bath of solder which consists of lead 40 percent and tin 60 percent fused at 250C. Dipping is performed for 5 to 10 seconds. Next, the body of the package is taken out of the bath and is cooled.
  • solder layers 30, 31, 28 and 29 of 3 to 10p thickness, preferably 3 to 5 ,u, containing a small amount of gold are formed instead of the gold layers 18a, 19a, 20 and 21 respectively.
  • solder layers whose ionization tendency is larger than that of gold are formed on the surface of the metallized layers and leads, the corrosion thereof can be prevented.
  • the shortcomings of the prior art, such as breaking of wires, weak mechanical strength, and low insulation resistance are eliminated. Since the surfaces of the leads are coated with the solder plated layer, the solderability of the leads is extremely good. Further, by the formation of the gold layers 18b, 19b and 17 on the necessary portions in the casing, a firm inner connection is attained. Thus, a highly reliable package with perfect connections and a strong anticorrosive property is obtained.
  • solder is not always limited to the lead-tin solder, but may be a metal eutectic with gold at a relatively low temperature without damaging the semiconductor device by heat, e.g., cadmium, zinc, lead, tin and alloys thereof, e.g., lead-tin solder and cadimiumtin solder.
  • a method of manufacturing a package for a semiconductor device comprising the steps of:

Abstract

A method of manufacturing a flat package having a casing for accommodating semiconductor elements, in which a conducting lead is adherent to a portion of a metallized layer leading out from the casing to the surface of the package, and the exposed surface of the metallized layer outside the casing is coated with an alloy layer of lead-tin, thereby preventing the corrosion of the metallized layer.

Description

United States Patent [191 Ihochiet al.
METHOD FOR MANUFACTURING A PACKAGE OF A SEMICONDUCTOR ELEMENT Inventors: Takahiko Ihochi; Tomio Yamada,
both of Kodaira, Japan Assignee: Hitachi, Ltd., Tokyo, Japan Filed: Mar. 6, 1970 Appl. No.: 17,207
Foreign Application Priority Data Mar, 12, 1969 Japan ..44/l8330 US. Cl. ..29/627, 29/589, 29/590, 29/626, 174/52 S, l74/D1G. 3, 317/234 Int. Cl. ..H05k 3/28 Field of Search ..l74/52 S, 52 PE, 174/52 FP, 68.5; 29/588-590; 204/15;
[451 May 1, 1973 [5 6] References Cited UNITED STATES PATENTS 3,517,279 6/1970 Ikeda et al ..3 1 7/234 M UX 3,404,214 10/1968 Elliott ..l74/DlG. 3 3,404,215 10/1968 Burks et al ..174/DIG. 3 3,495,023 2/1970 Hessinger et a1. ..l74/DlG. 3
Primary Examiner-Bemard A. Gilheany Attorney--Craig and Antonelli ABSTRACT A method of manufacturing a flat package having a casing for accommodating semiconductor elements, in which a conducting lead is adherent to a portion of a metallized layer leading out from the casing to the surface of the package, and the exposed surface of the metallized layer outside the casing is coated with an alloy layer of lead-tin, thereby preventing the corrosion of the metallized layer.
1 Claim, 5 Drawing Figures Patented May 1, 1973 INVENTOR TAKAHI'KO rHocHI and roMIo YAMADA ATTQRNEY METHOD FOR MANUFACTURING A PACKAGE OF A SEMICONDUCTOR ELEMENT BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of manufacturing a casing of a semiconductor device, and more particularly a method of manufacturing a flat package suitable for accommodating a semiconductor integrated circuit.
2. Description of the Prior Art In a known casing for a semiconductor device called a flat package or a dual in line package, a metallized layer of molybdenum-manganese is formed on a ceramic plate, and a gold plating is applied to this metallized layer to form fitting portions for a semiconductor substrate, wirings and external lead-out electrodes. This package, however, has the following disadvantages shown in an environmental test. Due to pinholes, imperfectly plated portions, and scars in the gold plating layer, the metallized layer of molybdenum-manganese having a large ionization tendency is corroded by a localized galvanic action. As a result, the metallized layer suffers from the breakage of wires or a degradation of its mechanical strength, or precipitations (hydroxides of molybdenum and manganese) extending over the surface of the ceramic plate cause deterioration of the insulation resistance between the metallized wirings. For example, the insulation resistance of metallized layers with 1 mm gap therebetween drops from Qprior to a high temperature and moisture test at 80C with 90 percent moisture for 168 hours to about 10" (I after the test.
The above defects may be some degree reduced by thickening the gold plated layer in order not to expose the underlying metal. For this purpose, however, alarge amount of very precious gold would have to be used, whence the method becomes economically undesirable. Furthermore, even by this methodthe external portions of a metallized layer near the wall of a casing leading out therefrom may not be satisfactorily gold plated, and a problem of not being able to attain enough anti-corrosiveness in this portion arises.
SUMMARY OF THE INVENTION An object of this invention is to provide a method of manufacturing a highly reliable package for semiconductor elements at a low price.
Another object of this invention is to provide a method of preventing the corrosion of a metallized layer extending over the surface ofa flat package which accommodates an integrated circuit.
According to one embodiment of this invention, a method of manufacturing a package having a casing of a semiconductor element is provided, wherein a conducting lead is attached to one end ofa metallized layer leading out from the casing to the surface of the package; the metallized layer and conducting lead are both plated with gold; and finally the gold plated layers are dipped into a lead-tin solder bath to replace the gold plated layers on the surfaces of the metallized layer and conducting lead by lead-tin soldered layers, thereby preventing the corrosion of the metallized layer.
The above and other objects and advantages of the present invention will be made more apparent from the preferred embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 5 show the cross sections of the manufacturing steps of a flat package according to one embodiment of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of this invention will be explained in particular with reference to a method of manufacturing a flat package suitable for accommodating a semiconductor integrated circuit.
First, a body of package 1 as shown in FIG. 1 is prepared. This body 1 is formed by stacked ceramic sheets 2, 3 and 4 whose major ingredient is alumina or beryllium oxide and whose thickness is 0.05 to 1 mm, then by hot-pressing and sintering these sheets at 1,500 to 1,600C. A metallized layer 8 is preliminarily formed on a portion of the sheet 2 where a semiconductor substrate is to be disposed. The metallized layers 5 and 6 extend over the surface of the sheet 3. The center portion of the sheet 3 corresponding to the metallized layer 8 is perforated to expose the same. Similarly, the sheet 4 is annularly formed to surround the prescribed surface area of the sheet 3. A metallized layer 7 is formed on the major surface of the sheet 4. The metallized layers 5, 6, 7 and 8 are formed by the use of the well-known screen printing method, i.e., coating a metal ink mainly consisting of molybdenum-manganese on the prescribed surfaces of the sheets.
Next, in order to simplify the lead attaching process in the later steps, nickel plating layers 9a, 9b, 10a, 10b,
11 and 12 having a thickness of 2 to 7 p. are formed on the surfaces of the metallized layers 5, 6, 7 and 8 respectively, as shown in FIG. 2.
As shown in FIG. 3, using an alloy of silver and copper for the soldering layers 15a and 15b, leads 13 and 14 are connected to the ends of the nickel-plated metallized layers 5 and 6 respectively.
As shown in FIG. 4, gold plated layers 20, 21, 18a,
18b, 19a, 19b, 16 and 17 with thickness of about 1 to 4 ,u. are formed on the surfaces of leads l3 and 14 and of nickel layers 9a, 9b, 10a, 10b, 11 and 12 respectively. These gold plated layers are formed by the electroplating method in the same way as the above nickel-plated layers.
Further, as shown in FIG. 5, the gold layers 18a, 20, 19a and 21 positioned outside the ceramic plate 4 are dipped in a bath of solder which consists of lead 40 percent and tin 60 percent fused at 250C. Dipping is performed for 5 to 10 seconds. Next, the body of the package is taken out of the bath and is cooled.
By the above treatment in this embodiment, according to which the gold layers on the surfaces of the conductors l3 and 14 fuse into the fused solder in the bath in the form of a gold-tin eutectic alloy, the surfaces of the metallized layers and leads of molybdenum, manganese and nickel outside the casing are wetted with solder. Thus, on the surfaces of the metallized layers and leads taken out of the solder bath, solder layers 30, 31, 28 and 29 of 3 to 10p thickness, preferably 3 to 5 ,u, containing a small amount of gold are formed instead of the gold layers 18a, 19a, 20 and 21 respectively.
On the gold layer 17 a substrate of semiconductor integrated circuit of silicon 22 is bonded. The electrodes 23 and 24 formed on the major surface of the substrate of the semiconductor integrated circuit are firmly connected to the gold layers 18b and 19b with the connecting wires 25 and 26 of, e.g., gold respectively. The connection is performed either by the ultrasonic bonding method or by the thermocompression bonding method. After the connection of the substrate and connecting wires, a metal cover 27 is fused onto the gold layers 16 over the ceramic frame 4, whereby the silicon integrated circuit substrate 22 is sealed in airtight.
Since solder layers whose ionization tendency is larger than that of gold are formed on the surface of the metallized layers and leads, the corrosion thereof can be prevented. The shortcomings of the prior art, such as breaking of wires, weak mechanical strength, and low insulation resistance are eliminated. Since the surfaces of the leads are coated with the solder plated layer, the solderability of the leads is extremely good. Further, by the formation of the gold layers 18b, 19b and 17 on the necessary portions in the casing, a firm inner connection is attained. Thus, a highly reliable package with perfect connections and a strong anticorrosive property is obtained.
The above solder is not always limited to the lead-tin solder, but may be a metal eutectic with gold at a relatively low temperature without damaging the semiconductor device by heat, e.g., cadmium, zinc, lead, tin and alloys thereof, e.g., lead-tin solder and cadimiumtin solder.
Although this invention has been explained with reference only to one embodiment, it is not limited thereto but may be altered without departing from the spirit of the invention. For example, it is possible to use the electro-plating or the chemical plating method for plating the above solder onto the surface of the gold plated layers, and thereafter by heating the gold layers are fused into solder plating layers in order to decrease their ionization tendency, whereby corrosion of the underlying metals is prevented. The step of depositing soldered layers on the external metallized layers and leads may be performed after fitting the semiconductor substrate to the ceramic plate 2 and making the necessary wirings.
What is claimed is:
l. A method of manufacturing a package for a semiconductor device comprising the steps of:
a. preparing a combination of an insulating substrate having a major surface, an insulating frame disposed on said major surface so as to surround a prescribed region of said major surface, a first metal layer of a first metal having a larger ionization tendency than that of gold and formed on said major surface so as to extend from said prescribed region toward the outside of said frame through a gap between said insulating frame and said substrate; a first gold layer covering a first portion of said first metal layer on said prescribed region, and a second gold layer covering a second portion of said first metal layer extending toward the outside of said frame;
b. disposing a semiconductor element on said prescribed region and electrically connecting said semiconductor element to said first portion of said first metal layer through said first old layer; 0. covering said frame with a sea mg means and forming an air-tight space surrounding said semiconductor element; and
. bringing said second gold layer into contact with a fused solution of a second metal comprising a solder selected from the group consisting of lead, tin, zinc, cadmium and an alloy of an arbitrary combination thereof, so as to dissolve only the gold of said second gold layer into said fused solution of said second metal.
US00017207A 1969-03-12 1970-03-06 Method for manufacturing a package of a semiconductor element Expired - Lifetime US3729820A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP44018330A JPS4810904B1 (en) 1969-03-12 1969-03-12

Publications (1)

Publication Number Publication Date
US3729820A true US3729820A (en) 1973-05-01

Family

ID=11968601

Family Applications (1)

Application Number Title Priority Date Filing Date
US00017207A Expired - Lifetime US3729820A (en) 1969-03-12 1970-03-06 Method for manufacturing a package of a semiconductor element

Country Status (2)

Country Link
US (1) US3729820A (en)
JP (1) JPS4810904B1 (en)

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864728A (en) * 1970-11-20 1975-02-04 Siemens Ag Semiconductor components having bimetallic lead connected thereto
US3872583A (en) * 1972-07-10 1975-03-25 Amdahl Corp LSI chip package and method
US3922775A (en) * 1973-09-13 1975-12-02 Sperry Rand Corp High frequency diode and manufacture thereof
US4246697A (en) * 1978-04-06 1981-01-27 Motorola, Inc. Method of manufacturing RF power semiconductor package
US4465742A (en) * 1978-09-05 1984-08-14 Ngk Spark Plug Co., Ltd. Gold-plated electronic components
US4486511A (en) * 1983-06-27 1984-12-04 National Semiconductor Corporation Solder composition for thin coatings
US4572924A (en) * 1983-05-18 1986-02-25 Spectrum Ceramics, Inc. Electronic enclosures having metal parts
US4590672A (en) * 1981-07-24 1986-05-27 Fujitsu Limited Package for electronic device and method for producing same
EP0209642A2 (en) * 1985-07-25 1987-01-28 Hewlett-Packard Company Ceramic microcircuit package
US4656499A (en) * 1982-08-05 1987-04-07 Olin Corporation Hermetically sealed semiconductor casing
US4677741A (en) * 1981-11-30 1987-07-07 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing package for high power integrated circuit
WO1988003705A1 (en) * 1986-11-07 1988-05-19 Olin Corporation Semiconductor die attach system
US4769345A (en) * 1987-03-12 1988-09-06 Olin Corporation Process for producing a hermetically sealed package for an electrical component containing a low amount of oxygen and water vapor
US4784974A (en) * 1982-08-05 1988-11-15 Olin Corporation Method of making a hermetically sealed semiconductor casing
US4891333A (en) * 1984-10-09 1990-01-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US4929516A (en) * 1985-03-14 1990-05-29 Olin Corporation Semiconductor die attach system
US4978052A (en) * 1986-11-07 1990-12-18 Olin Corporation Semiconductor die attach system
US5006963A (en) * 1989-12-18 1991-04-09 Mcdonnell Douglas Corporation Selectable chip carrier
USRE34484E (en) * 1978-09-05 1993-12-21 Ngk Spark Plug Co., Ltd. Gold-plated electronic components
US5423119A (en) * 1994-07-08 1995-06-13 Hualon Microelectronics Corporation Method for manufacturing a hybrid circuit charge-coupled device image sensor
US5448826A (en) * 1993-10-08 1995-09-12 Stratedge Corporation Method of making ceramic microwave electronic package
US5508888A (en) * 1994-05-09 1996-04-16 At&T Global Information Solutions Company Electronic component lead protector
US5736783A (en) * 1993-10-08 1998-04-07 Stratedge Corporation. High frequency microelectronics package
US5753972A (en) * 1993-10-08 1998-05-19 Stratedge Corporation Microelectronics package
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
US6064286A (en) * 1998-07-31 2000-05-16 The Whitaker Corporation Millimeter wave module with an interconnect from an interior cavity
US6172412B1 (en) * 1993-10-08 2001-01-09 Stratedge Corporation High frequency microelectronics package
US20070090515A1 (en) * 2005-10-24 2007-04-26 Freescale Semiconductor, Inc. Semiconductor structure and method of assembly
EP2757582A1 (en) * 2013-01-17 2014-07-23 Nxp B.V. Packaged electrical components
US20150124411A1 (en) * 2003-09-18 2015-05-07 Antti Iihola Method for manufacturing an electronic module and electronic module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404215A (en) * 1966-04-14 1968-10-01 Sprague Electric Co Hermetically sealed electronic module
US3404214A (en) * 1967-07-17 1968-10-01 Alloys Unltd Inc Flat package for semiconductors
US3495023A (en) * 1968-06-14 1970-02-10 Nat Beryllia Corp Flat pack having a beryllia base and an alumina ring
US3517279A (en) * 1966-09-17 1970-06-23 Nippon Electric Co Face-bonded semiconductor device utilizing solder surface tension balling effect

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404215A (en) * 1966-04-14 1968-10-01 Sprague Electric Co Hermetically sealed electronic module
US3517279A (en) * 1966-09-17 1970-06-23 Nippon Electric Co Face-bonded semiconductor device utilizing solder surface tension balling effect
US3404214A (en) * 1967-07-17 1968-10-01 Alloys Unltd Inc Flat package for semiconductors
US3495023A (en) * 1968-06-14 1970-02-10 Nat Beryllia Corp Flat pack having a beryllia base and an alumina ring

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864728A (en) * 1970-11-20 1975-02-04 Siemens Ag Semiconductor components having bimetallic lead connected thereto
US3872583A (en) * 1972-07-10 1975-03-25 Amdahl Corp LSI chip package and method
US3922775A (en) * 1973-09-13 1975-12-02 Sperry Rand Corp High frequency diode and manufacture thereof
US4246697A (en) * 1978-04-06 1981-01-27 Motorola, Inc. Method of manufacturing RF power semiconductor package
US4465742A (en) * 1978-09-05 1984-08-14 Ngk Spark Plug Co., Ltd. Gold-plated electronic components
USRE34484E (en) * 1978-09-05 1993-12-21 Ngk Spark Plug Co., Ltd. Gold-plated electronic components
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
US4590672A (en) * 1981-07-24 1986-05-27 Fujitsu Limited Package for electronic device and method for producing same
US4677741A (en) * 1981-11-30 1987-07-07 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing package for high power integrated circuit
US4656499A (en) * 1982-08-05 1987-04-07 Olin Corporation Hermetically sealed semiconductor casing
US4784974A (en) * 1982-08-05 1988-11-15 Olin Corporation Method of making a hermetically sealed semiconductor casing
US4572924A (en) * 1983-05-18 1986-02-25 Spectrum Ceramics, Inc. Electronic enclosures having metal parts
US4486511A (en) * 1983-06-27 1984-12-04 National Semiconductor Corporation Solder composition for thin coatings
US4891333A (en) * 1984-10-09 1990-01-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US4929516A (en) * 1985-03-14 1990-05-29 Olin Corporation Semiconductor die attach system
EP0209642A3 (en) * 1985-07-25 1987-04-15 Hewlett-Packard Company Ceramic microcircuit package
EP0209642A2 (en) * 1985-07-25 1987-01-28 Hewlett-Packard Company Ceramic microcircuit package
WO1988003705A1 (en) * 1986-11-07 1988-05-19 Olin Corporation Semiconductor die attach system
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
US4978052A (en) * 1986-11-07 1990-12-18 Olin Corporation Semiconductor die attach system
US4769345A (en) * 1987-03-12 1988-09-06 Olin Corporation Process for producing a hermetically sealed package for an electrical component containing a low amount of oxygen and water vapor
US5006963A (en) * 1989-12-18 1991-04-09 Mcdonnell Douglas Corporation Selectable chip carrier
US5448826A (en) * 1993-10-08 1995-09-12 Stratedge Corporation Method of making ceramic microwave electronic package
US6172412B1 (en) * 1993-10-08 2001-01-09 Stratedge Corporation High frequency microelectronics package
US5692298A (en) * 1993-10-08 1997-12-02 Stratedge Corporation Method of making ceramic microwave electronic package
US5736783A (en) * 1993-10-08 1998-04-07 Stratedge Corporation. High frequency microelectronics package
US5753972A (en) * 1993-10-08 1998-05-19 Stratedge Corporation Microelectronics package
US5508888A (en) * 1994-05-09 1996-04-16 At&T Global Information Solutions Company Electronic component lead protector
US5423119A (en) * 1994-07-08 1995-06-13 Hualon Microelectronics Corporation Method for manufacturing a hybrid circuit charge-coupled device image sensor
US6064286A (en) * 1998-07-31 2000-05-16 The Whitaker Corporation Millimeter wave module with an interconnect from an interior cavity
US20150124411A1 (en) * 2003-09-18 2015-05-07 Antti Iihola Method for manufacturing an electronic module and electronic module
US10798823B2 (en) * 2003-09-18 2020-10-06 Imberatek, Llc Method for manufacturing an electronic module and electronic module
US11716816B2 (en) 2003-09-18 2023-08-01 Imberatek, Llc Method for manufacturing an electronic module and electronic module
US20070090515A1 (en) * 2005-10-24 2007-04-26 Freescale Semiconductor, Inc. Semiconductor structure and method of assembly
US7446411B2 (en) * 2005-10-24 2008-11-04 Freescale Semiconductor, Inc. Semiconductor structure and method of assembly
EP2757582A1 (en) * 2013-01-17 2014-07-23 Nxp B.V. Packaged electrical components

Also Published As

Publication number Publication date
JPS4810904B1 (en) 1973-04-09

Similar Documents

Publication Publication Date Title
US3729820A (en) Method for manufacturing a package of a semiconductor element
US3881884A (en) Method for the formation of corrosion resistant electronic interconnections
US4727633A (en) Method of securing metallic members together
JP2526007B2 (en) Structures and methods for forming electrical interconnections to semiconductor chips
US5540378A (en) Method for the assembly of an electronic package
US4675243A (en) Ceramic package for semiconductor devices
USH498H (en) Electronic component including soldered electrical leads
EP0074168B1 (en) Device and method for packaging electronic devices
JP4344560B2 (en) Semiconductor chip and semiconductor device using the same
US4765528A (en) Plating process for an electronic part
US6791182B2 (en) Semiconductor device
JP2627509B2 (en) Electronic component having conductive layer
US3743895A (en) Copper plated base plate with nickel plated insert for semiconductor component housing
JP3420469B2 (en) Wiring board
JP2593646B2 (en) Electronic components
JP4364033B2 (en) Wiring board with lead pins
JP2670208B2 (en) Package for storing semiconductor elements
JP3537667B2 (en) Wiring board
JPS6311744Y2 (en)
JPH0685165A (en) Semiconductor device and manufacture thereof
JPH04264709A (en) Chip-type solid state electrolytic capacitor
JPS5994571A (en) Terminal for soldering
JPS6360549A (en) Electronic component with conductive layer consisting of gold
JPH0397212A (en) Chip type solid-state electrolytic capacitor
JPS6356996A (en) Electronic parts with gold conductive layers