US3737885A

US3737885A - Digital responsive altimeter

Info

Publication number: US3737885A
Application number: US00129812A
Authority: US
Inventors: G Hedrick
Original assignee: Lear Siegler Inc
Current assignee: Lear Siegler Inc
Priority date: 1971-03-31
Filing date: 1971-03-31
Publication date: 1973-06-05
Anticipated expiration: 1990-06-05

Abstract

An apparatus for providing an analog indication of altitude in response to a digital altitude information signal, such as from a digital air data computer. The apparatus preferably provides coarse-fine altitude selection. Means, such as a digital-toresolver converter operatively connected to a resolver, provides an analog synchro signal in response to the digital altitude information signal. A servo network, such as one which includes a brushless D. C. motor, is operatively connected to the synchro signal providing means, such as to the resolver. The servo network provides an analog servo driving signal which is utilized to drive an analog display device, such as one which includes an altitude counter and analog pointer in which a geneva drive transfer mechanism interconnects the least two significant display positions, such as the tens and hundreds positions of the altimeter display.

Description

United States Patent [191 Hedrick 1 June 5 1973 [5 DIGITAL RESPONSIVE ALTIMETER ABSTRACT [75] Inventor: Geoffrey S. Hedrick, Katonah, NY. An apparatus for providing an analog indication of altitude in response to a digital altitude information [73] Asslgflee' Lear Slegler Armonk NY signal, such as from a digital air data computer. The Filed: 1971 apparatus preferably provides coarse-fine altitude [21] APPL NOJ 129,812 selection. Means, such as a digital-to-resolve r converter operatively connected to a resolver, provides an analog synchro signal in response to the digital al- [52] US. Cl. ..340/198, 318/584, 318/620 mude information SignaL A servo network, such as [221;] one which includes a brushless C motor, is opera re 0 earc tively connected to the synchro signal providing [56] References Cited means, such as to the resolvenThe servo network provldes an analog servo driving signal which [5 utilized to UNITED STATES PATENTS drive an analog display device, such as one which includes an altitude counter and analog pointer in which $332323 132; $33 5.31?"""13333313113133223?#32 n n n nnnnfnn n n innnnnnnnnnnn the 3,039,030 6,1962 weidnerm ""340/198 least two significant display pOSllElOnS, such as the tens 3,040,221 6/1962 Fitzner..... ....340/ 198 and hundreds positions of the altimeter display. 3,056,909 10/1962 Tripp ..340/l98 Primary ExaminerThomas B. Habecker AttorneyHubbell, Cohen & Stiefel and Wilfred O. Schmidt 24 Claims, 9 Drawing Figures ADDRESS 39 GENERATOR CLEAR 5 W934? gvnc cgA 1 N RA I (26 DATA 2o CLOCK I FROM BUS DATA BUS 253M 2a DADC INTERFACE INPUT ADDRESS I2 DECODER DARITY (IOLSB) DIGITAL TO RESOLVER CONVERTER (IOMSB) DIGITAL TO SUMMING JUNCTION 9 COARSE FINE RESOLVER RESOLVER TWO-SPEED DIODE SWITCH pmmmm 5l973 SHEET 2 [1F 5 F O D RZR I NETWORK 40X 5m ROM R-ZR LADDER NETW INVENTOR GEOFFREY s. HEDRICK BY 94,4 1; (I-A "fl FIG. 3.

' ATTORNEYS.

'------1-----'r----r ----'r--'"r SHEET 3 UP 5 SINUSOIDAL FUNCTION MATRIX- FIG. 4.

PATENIEDJUH 51mllllvllll'l INVENTOR GEOFFREY S. HEDRICK Mg, AT TORNEYS.

SINUSOIDAL FQNCTION MATRIX PAIENTED 51975 3,737,885

sum u [If 5 FIG. 6. my

I l i I .u i m] u I1 I L E T l E I l :r '1: -1' L:r :r

[22 SINUSOIDAL. FUNCTION MATRIX v 250 ROM) l A A A: J;

55 FIG. 7

l I I I T l l I l I l INVENTOR GEOFFREY S. HEDRICK I BY {WW (kl-m XM /*1 ATTORNEYS.

SSIGNAL INPUT 248 PATENIED 5W5 3,737,885

sum 5 BF 5 COMPLEMENTARY SYMMETRY OUTPUT STAGE 3 22 COMPLEMENTARY SYMMETRY OUT PUT STAGE COMPLEMENTARY SYMMETRY OUTPUT STAGE COMPLEMENTARY SYMMETRY OUTPUT STAGE .INVENTOR GEOFFREY S. HEDRICK BY M Mi, g a a;

ATTORNEYS.

DIGITAL RESPONSIVE ALTIMETER BACKGROUND OF INVENTION 1. Field of the Invention The present invention relates to altitude indicators, and more particularly to altitude indicators in which an analog indication of altitude is provided in response to a digital altitude information signal.

2. Description of the Prior Art.

Digital air data systems, that is systems in which a digital air data computer (DADS) is utilized to provide digital altitude information, have gained wide acceptance and are utilized on many of today's commercial aircraft. However, with the increasing use of such systems, problems have resulted in attempting to interface digital altitude indicators with the digital air data computer. Although some success has been achieved in the prior art, prior art altitude indicators have not been able to overcome the inherent disadvantages of the ambiguity in digital altitude displays, such as at or near the hundred and thousand foot transition points of such an altitude display. Furthermore, digital air data computers are susceptible both to quantizing least significant bit oscillation and acoustical noise in the pitot/static system. This results in distracting flutter of the altitude indicator during both straight and level flight, causing variations or jumps in the altitude display. These variations are not only distracting to the pilot but may become critical in certain flight situations. Such problems become increasingly difficult in emergency descent situations where an aircraft is experiencing rapid altitude change.

Prior art attempts to eliminate this altitude noise without providing excessive lag have proved inadequate. In addition, prior art altitude indicators which employ coarse-fine altitude selection suffer from transition errors which are introduced in the switching of the system from coarse to fine follow-up. This introduces an ambiguous position on the fine follow-up resolver of such a system. In such prior art altitude indicators, wherein the digital altitude presentation is provided by a counter mechanism and an analog pointer, conventional counter drive mechanisms between the least two significant display positions, or drums, result in unusually high impact loading of the gear teeth, especially at high input rates, such as experienced at turn-on of the indicator and rapid altitude change. These impact loading stresses decrease counter reliability and, since the altitude counter is one of the most critical sections of an altitude indicator, such decreases in reliability are not tolerable.

Since the altimeter or altitude indicator is one of the most critical instruments on board an aircraft, in that it indicates the dynamic altitude of the aircraft to the pilot, the altitude display is critical. Prior art attempts to provide a digitally compatible numerical display have involved the use of magnetic wheels which permit a virtually direct interface between an analog display and the digital input mentioned. However, these magnetic wheels are both difficult to failure monitor and consume an inordinate amount of power which results in an undesirable significant internal temperature rise in the altimeter. In addition, the analog pointer movement utilized in such a system for rate sensing requires that two virtually independent systems be provided within such an altimeter. This introduces undue circuit complexity in such a prior art system. In addition, magnetic wheels experience display flutter which, as was previously mentioned, is both distracting and undesirable. Furthermore, the resulting internal heat rise and increased circuit complexity result in both degraded reliability and increased cost which are both undesirable in a critical instrument such as an altitude indicator.

In addition, prior art altitude indicators employ counter-analog pointer displays which utilize either instantaneous transfer with respect to the drum containing the least two significant display positions or the standard fork-and-pinion transfer. In the first instance, reading errors and annoying flutter are introduced, while in the second instance half way reading errors are introduced. Both these compromises are undesirable. Consequently, no satisfactory prior art altitude indicators capable of direct interface with a digital air data computer have been available.

These disadvantages of the prior art are overcome by the present invention.

SUMMARY OF THE INVENTION An apparatus for providing an analog indication of altitude in response to a digital altitude information signal, such as from a digital air data computer is provided. The apparatus preferably provides coarse-fine altitude selection. Means, such as a digital-to-resolver converter are operatively connected to a resolver to provide either a coarse or fine analog synchro signal in response to the digital altitude information signal. A servo network, which preferably includes a brushless D.C. motor, such as one employing direct rate sensing, is operatively connected to the synchro signal providing means, such as the resolver portion thereof. The servo network provides an analog servo driving signal which is utilized to drive an analog display device, such as one which includes an altitude counter and analog pointer in which a geneva drive transfer mechanism interconnects the least two significant display positions, such as the tens and hundreds positions of the altimeter display.

The digital-to-resolver conversion of the digital altitude information signal provided from the digital air data computer is provided by means of a pair of readonly memories which have been programmed to each provide a complementary sinusoidal function of the digital altitude input signal and a binary scaling means, such as an R-2R ladder network connected to the output of each of the respective memories. Preferably, each memory has an operating state and a protection state, an output being producible'only in the operating state. In such instance, a source of reference potential which has a value sufficient to maintain the memories in the operating state is connected to the sealing means. However, these read-only memories may be provided without protection means, in which instance the reference potential is not required to be connected to the ladder network. In addition, the analog synchro signal providing network includes means for damping the synchro signal so as to substantially eliminate any altitude signal noise component present in the altitude information signal. Such means preferably includes non-linear integration means.

Preferably, the brushless D.C. motor utilized in the servo portion of the altitude indicator includes a first excitation stator, a magnetic rotor rotatably positioned in magnetic relation with the first stator, a magnetic flux sensor means positioned in fixed relation to the first stator and in magnetic relation to the rotor so as to sense the magnitude of the rotor flux density as a sinusoidal function of angular position of the rotor and produce a signal proportional thereto, a second stator magnetically independent from the first stator and positioned in magnetic relation with the rotor, and an independent feedback path for the sensor means, theindependent feedback path including the second stator, whereby direct rate feedback control for the sensor means is provided.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a block diagram partially in schematic of the preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of the preferred word sync gap generator and data bus interface portions of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram partially in schematic of the preferred typical fully cycle digital-to-resolver conversion portion of the embodiment shown in FIG. 1;

FIGS. 4, 5 and 6 are schematic diagrams partially in block of alternative embodiments of the quarter cycle digital-to-resolver converter portion of the full cycle converter shown in FIG. 3;

FIG. 7 is a schematic diagram of the preferred servo amplifier portion of the embodiment shown in FIG. 1; and

FIGS. 8 and 9 are schematic diagrams partially in block of the preferred embodiment of the brushless D.C. motor portion of the embodiment shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS General Description Referring now to the drawings in detail and especially to FIG. 1 thereof. The altitude indicator of the present invention, generally referred to by the reference numeral 10, includes a conventional data bus interface portion 12 which, as will be explained in greater detail hereinafter, is operatively connected to a conventional digital air data computer (not shown) for receiving a digital differential altitude data word indication of the aircrafts altitude therefrom. The data bus interface portion 12, which will be described in greater detail hereinafter with reference to FIG. 2, is operatively connected to a conventional word sync gap generator 14. The data bus interface 12 provides a clear-pulse synchronized with the word sync gap, this pulse illustratively shown as being provided on path 16. As will be explained in greater detail hereinafter, the data bus interface portion 12 also provides a single ended data output via a path 18, and a clock output via a path 20.

The data bus interface portion 12 is operatively connected to a shift register network which is preferably a -bit shift register in accordance with conventional digital air data computer information and is illustratively shown as comprising a four-bit shift register (S.R.) 22, and a pair of eight-bit shift registers (S.R.) 24 and 26, respectively. The input to the shift register network 22-24-26 is preferably a conventional 18-bit altitude word, the other two bit positions in the shift register network 22-24-26 being provided for monitoring, the first two stages of the shift register network 22-24-26 being pre-set prior to the shifting of new information into the shift register network 22-24-26. A

conventional address decoder 28 is operatively con nected to the lasttwo stages of the shift register network 22-24-26 which, as illustratively shown, comprises the last two stages of the eight-bit shift register 26. As will be explained in greater detail hereinafter, the function of the address decoder 28 is to enable a parity check for the altitude word present in the shift register network 22-24-26.

As will be further explained in greater detail hereinafter, the address decoder 28 provides a valid output via a path 30. Path 30 is operatively connected to one input ofa three input NAND gate 32. The second input of the three input NAND gate 32 is operatively connected via a path 34 to one stage of the four-bit shift register 22. This stage provides the valid data bit in the altitude word. The third input of the three input NAND gate 32 is operatively connected via a path 36 to the output of a conventional parity checker 38 which, as will be described in greater detail hereinafter, preferably checks for odd parity in the altitude word present in the shift-register network 22-24-26. Accordingly, the first 16 stages of the shift register network 2224-26, that is all the stages except the last two stages of shift register 26 which are operatively connected to the address decoder 28, are operatively connected to the inputs of the parity checker 38.

In addition, the four-bit shift register 22 is also preferably operatively connected to a conventional address generator 39. Furthermore, as shown and preferred, the last two stages of the four-bit shift register 22 and all eight stages of the eight-bit shift register 24 are operatively connected in parallel to the input of a digital-toresolver conversion stage 40, to be described in greater detail hereinafter, which conversion stage 40 is preferably of the type disclosed in my copending U. S. Pat. application Ser. No. 67,543, filed Aug. 27, 1970 and entitled ALTITUDE ALERTING APPARATUS, and assigned to the same assignee, which disclosure is hereby incorporated by reference. As also shown and preferred, the last four stages of the eight-bit shift register 24 and the first six stages of the eight-bit shift register 26 are operatively connected in parallel to another digital-to-resolver conversion stage 42 which is preferably identical with conversion stage 40.

The output of the two

conversion stages

40 and 42, respectively, are connected to a fine resolver 46 and a coarse resolver 48, which resolvers 46 and 48 aredifferentially geared together through a conventional gear reduction device 50, illustratively shown as having a gear reduction ratio of 64:1, the ratio being dependent on the scale factor of the fine-to-

coarse resolvers

46, 48. The sine winding of the fine and

coarse resolvers

46 and 48, respectively, is operatively connected to a conventional two-speed diode switch 52. The output of the two-speed diode switch 52 is operatively connected to a servo stage 54 which, as will be described in greater detail hereinafter, provides a servo driving signal.

The servo stage 54 preferably includes a servo amplifier 56, to be described in greater detail hereinafter, and a generator 58 and servo motor 60 operatively connected in a servo control loop, the generator 58 and motor 60 preferably being a brushless D.C. motor, as will be described in greater detail hereinafter. The brushless D.C. motor 60 is preferably of the type disclosed in my copending U. S. Pat. application Ser. No. 54,387, filed July 13, 1970 and entitled BRUSI-ILESS DC MOTOR, and assigned to the same assignee, and

now US. Pat. No. 3,679,954, which disclosure is hereby incorporated by reference. As will be described in greater detail hereinafter, the servo control stage or network 54 generator signal is summed with the output signal of the two-speed diode switch 52 at a summing junction 62. The output of servo stage 54 is connected to a display stage 64, which is preferably an analog display, through a conventional gear train 66. The fine and coarse follow-up

resolvers

46 and 48, respectively, are also differentially geared to the analog display 64 through a conventional gear train 68 similar to gear train 66.

As will be explained in greater detail hereinafter, the analog display 64 preferably includes a conventional counter mechanism 70 comprising a plurality of

rotating drums

72, 74, 76, and 78. For purposes of illustration, the least significant display position, or tens position, is represented by rotary drum 78 and the most significant display position, or ten thousands position in the example shown, is represented by rotary drum 72. In addition, the least significant display position drum 78 is directly geared to a conventional analog pointer 80. As will be explained in greater detail hereinafter, drums 72, 74 and 76 of the conventional counter mechanism are preferably interconnected by means of a conventional internal pinion, alternate tooth pinion drive mechanism so that transfers of the

drums

72, 74 and 76 occur at the same speed. However, as will be explained in greater detail hereinafter, the least significant display position drum 78 is preferably interconnected to the next significant display position drum, or hundreds drum 76, by means of a geneva drive mechanism 82 to accomplish transfer therebetween. As shown and preferred, barometric correction is preferably provided in the altitude indicator by means of a non-linear potentiometer 84 which is geared directly to a conventional barometric counter 86 via a conventional gear train 88; the conventional barometric counter 86 being directly geared to a conventional baro set knob 90. As will be described in greater detail hereinafter, the output of the potentiometer 84 is linear with effective altitude correction. This output is in turn operatively connected to the digital air data computer (not shown) to correct for local barometric readings.

DATA BUS INTERFACE Referring now to FIG. 2 and describing the data bus interface 12 and word sync gap generator 14 in greater detail. The differential signal received from the digital air data computer is operatively connected to a conventional operational amplifier 92 which, as shown and preferred, is operated in the differential configuration. The amplifier 92 in this differential configuration provides excellent common mode rejection and converts the received differential signal into a more compatible single-ended output signal. In this conventional data bus interface configuration 12,

capacitors

94 and 96 are associated with the differential input amplifier 92 so as to integrate the differential input signal such that the time constant for this integrator insures rejection of noise pulses for a predetermined desired time interval. The output of this differential integrator 92-94-96 is operatively connected to a pair of conventional operational

amplifier voltage comparators

98 and 100, respectively, which detect predetermined voltage levels to preclude false triggering due to static differential voltage levels on the data bus. As will be explained in greater detail hereinafter, voltage comparator 98 provides the data signal to the shift register network 22-24-26 via path 18. As shown and preferred,

diodes

102 and 104 operatively associated with

comparators

98 and 100, respectively, are provided to protect the differential input amplifier 92 from high voltage transients. The output of voltage comparator 98 and voltage comparator are operatively connected as inputs to an OR gate 106 to provide the clock or shift pulse for the shift register network 22-24-26 and the word sync gap generator 14.

The output of OR gate 16, which is the clock signal, is preferably operatively connected to a conventional transistor 108 which, as shown and preferred, is operatively connected so as to short the capacitor 110 of a conventional unijunction transistor relaxation oscillator 112. The output of the unijunction transistor relaxation oscillator 112 is operatively connected to drive a conventional common emitter output transistor 114 to provide a clear signal via path 16 as the output of the word sync gap generator configuration 14, input'transistor 108, relaxation oscillator 112 and output transistor 114 comprising the word sync gap generator configuration 14. If desired, any other conventional data bus interface-word sync gap generator network 12-14 could be utilized in place of that previously described without departing from the present invention.

DIGITAL-TO-RESOLVER CONVERSION STAGE Referring now to FIG. 3 and describing, by way of example, the digital-to-resolver conversion stage 40 in greater detail, the digital-to-resolver conversion stage 42, as was previously mentioned, being preferably identical therewith. As was previously mentioned, the conversion stage 40 is preferably of the type disclosed in my copending U. S. Pat. application Ser. No. 67,543, filed Aug. 27, 1970 and entitled ALTITUDE ALERT- ING APPARATUS, and assigned to the same assignee, which disclosure has been incorporated by reference. However, for purposes of clarity, applicable portions of this disclosure will be repeated hereinafter.

The digital-to-synchro conversion stage 40 preferably includes a digital-to-synchro quarter-cycle convertor 118 capable of providing a pair of complementary sinusoidal functions, which are preferably sine and cosine, respectively, of a representative synchro or resolver shaft angle between 0 and 90 from a digital input, and a full cycle quadrant selection portion 120 capable of providing the sine and cosine functions respectively, of a representative synchro shaft angle between 0 and 360 from the quarter-cycle shaft angle information and the quadrant selection information. Of course, if a full cycle digital signal without quadrant selection were utilized as the digital input, then, if desired, a full cycle convertor similar in principle of operation to the preferred quarter cycle converter 118, could be utilized in place thereof, in which case the quadrant selection portion 120 would be omitted. The preferred ten bit digital input signal is preferably provided as a parallel input, one conductor per bit. As will be explained in greater detail hereinafter, preferably, the eight least significant bits (LSB) of the ten bit input signal from the appropriate shift register stages of shift register network 22-24-26 provide the digital input information to the digital-to-synchro quarter-cycle conversion portion 1 18 whereas the two most significant bits (MSB) of this signal control the quadrant selection portion 120 in a manner to be described in greater detail hereinafter.

Preferably, the digital-to-synchro quarter-cycle converted portion 118 includes a pair of read-

only memories

122 and 124, respectively, which are programmed in a conventional manner to provide a sine function of the digital input and a cosine function of the digital input, respectively. The sine read-only memory 122 and the cosine read-only memory 124 are preferably constituted by metal-oxide semi-conductor monolithic chips, which are commonly termed MOS chips. As will be explained in greater detail hereinafter by reference to FIG. 4, these

MOS chips

122 and 124 each have an input portion 126 which is apre-programmed function matrix which provides the desired sinusoidal function, and an output portion 128 which preferably comprises a plurality of bistable output sections 130, one for each binary input, each section comprising a pair of serially coupled sink-source field-effect transistors (FET) 132, 134, to be described in greater detail hereinafter. The eight least significant bit parallel digital input is coupled in parallel to eight inputs to both the sine readonly memory 122 and the cosine read-only memory 124, one input corresponding to one binary bit. The output portions 128 of both the sine read-only memory 122 and the cosine read-only memory 124 are each respectively coupled to a binary scaler, which is preferably a conventional R-

2R ladder network

136 and 138. The output portions 128 of the read-

only memory

122 and 124 are also coupled to ground in the embodiment shown in FIG. 4 for a purpose to be described in greater detail herinafter.

The ladder networks 122 and 124, for the read-only memory-ladder network configuration shown in FIG. 4, are preferably coupled in parallel through a source of reference potential 140 which is illustratively shown as comprising a DC source, although an AC source can be utilized, whose function is to maintain the read-

only memory

122 and 124 in the operating condition, which, in the embodiment of FIG. 4, is preferably the only condition in which the read-only memory provides an output, as will be described in greater detail hereinafter. The sine function output of the read-only memory 122 is preferably provided via a path 142 through a non-linear integration network 144-to a high gain operational amplifier 146 which provides the quarter cycle to 90) output via a path 148 and aids in maintaining the sine read-only memory 122 in the operating state in a manner to be described in greater detail hereinafter. Similarly, the cosine function output of the cosine read-only memory 124 is fed via a path 150 through another non-linear integration network 152 to another high gain operational amplifier 154 which provides the quarter cycle (0 to 90) cosine function output via a path 156 and aids in maintaining the cosine read-only memory 124 in the operating state in a manner to be described in greater detail hereinafter.

The

non-linear integration networks

144 and 152 are preferably identical and each include a series R-C lag network 158-160 and 162-464, respectively, which preferably has a time constant such that the altitude noise is integrated out, and a pair of diodes 166-168 and 170-172, respectively, connected in parallel with the series resistor, 158 and 162, respectively, so as to shunt the

series resistor

158 or 162 so as to provide a low resistance path to charge the

capacitor

160 or 164 and significantly reduce the time constant of the integrator for altitude changes of greater than a predetermined value, such as 5 feet. In this manner undue lag for rapid altitude changes is prevented. The voltage on the

capacitors

160 and 162 is buffered by the unity gain

operational amplifiers

146 and 154, respectively.

The quarter cycle sine function output on path 148 and the quarter cycle cosine output on path 156 of the digital-to-synchro quarter cycle (0 to convertor 118 are connected to the quadrant selection portion 120. The quarter cycle sine function output via path 148 is connected, via a path 174, through a unity gain inverting amplifier 176 to the inputs of a conventional 2-out-of-8 multiplexer 178 and via a pat 180, directly to the multiplexer 178. Similarly, the quarter cycle cosine function output via path 156 is connected, via a path 182, through another unity gain inverting amplifier 184 to the multiplexer 178 and, via a path 186, directly to the multiplexer 178.

The multiplexer 178 preferably has four inputs relating to the

sine function

188, 190, 192 and 194, and four inputs relating to the

cosine function

196, 198, 200 and 202. The quadrant selection portion receives the two most significant bits for quadrant selection. The most significant bit of the 10 bit digital input word determines the phase of the output signal. This bit is fed through an Exclusive OR gate 204 which acts as a controlled true complement gate. The control input for this gate 204 is preferably provided by an in phase square wave generator source 206, such as a 400 Hz square wave source. In this manner the analog multiplexer 178 serves as a full wave modulator. Each of the multiplexer inputs 188 through 202 inclusive is associated with a switch (not shown) which is enabled in accordance with the bit condition of the quadrant select bits.

The sine function output of the multiplexer 178 which is selected by switches 188 through 194 is fed via path 208 through a unity gain buffer amplifier 210 to provide a full cycle sine function output (0 to 360) of the synchro shaft angle representative of the altitude digital input via path 212, which function is represented by the expression sine 0 where 0 represents the fine resolver shaft angle. The cosine function output of the multiplexer 178 which is selected by switches 196 through 202, is fed via path 214 through a unity gain buffer amplifier 216 which provides a full cycle cosine function output (0 to 360) of the synchro shaft angle representative of the altitude digital input via path 218, which function is represented by the expression cosine 6,, where 0 represents the fine resolver shaft angle. These full cycle output signals sine 0 via path 212, and cosine 0, via path 218 are fed to the fine resolver 46 for further processing in a manner to be described in greater detail hereinafter.

Digital-To-Synchro Quarter Cycle Converter" Referring once again to FIG. 4 and now describing the read-only memory-ladder network portion in greater detail. For purposes of illustration only, the cosine read-only memory-ladder network 122-136 will be described, the cosine read-only memory-ladder network 124-138 and manner of operation preferably being identical therewith with the exception that a cosine function matrix instead of a sine function matrix is provided in the read-only memory so as to program it to perform the cosine function in place of the sine function. The sine function matrix input portion 126 is a conventional matrix array program wired to provide a sine function of a digital input signal and will not be described or shown in greater detail hereinafter. As was previously mentioned, the read-only memory 122 is preferably an MOS device. Such MOS devices have some fixed value resistance which can be compensated for if desired in the ladder network 136. Such compensating resistance has been omitted in FIG. 4 for purposes of clarity.

Preferably, each of the output sections 130 of the output portion 128 is identical and only one such section will be described in greater detail for purposes of explanation. The output section 130 includes a pair of field effect transistors (FET) 132 and 134, FET transistor 132 having a source electrode 220, a gate electrode 222, and a drain electrode 224, and FET transistor 134 including a source electrode 226, a gate electrode 228 and a drain electrode 230. As was previously mentioned,

FET transistors

132 and 134 are serially connected together in sink-source relationship, with the drain electrode 224 of transistor 132 coupled to the source electrode 226 of transistor 134 at a coupling junction 232. The source electrode 220 of transistor 132 is connected to ground whereas the drain electrode 230 of transistor 134 is coupled via path 142 to the high gain operational amplifier 146 input. As shown and preferred in FIG. 4, the respective uncoupled source electrode 220 of each sin-source FET transistor pair 132-134 is connected in parallel to ground via path 234 and the uncoupled drain electrode 230 of each of these FET pairs 132-134 is connected in parallel to output path 142. The conventional R2R ladder network 136 has a 2R branch 236 connected to each coupling junction 232 and an R linking branch 238 having an impedance value which is preferably approximately half the value of the 2R branch 236. The ladder network 136 is connected to ground through another 2R branch 236.

By way of illustration, diode protection devices 240 are shown as being connected in parallel to the

drain electrodes

224 and 230 of each transistor pair 132-134 for protecting the MOS memory 122, and specifically the output portion 128 thereof, against voltage surges. These protection devices are normally provided with read-only memories having field-effect output transistors to prevent these memories from exceeding their given rated potential at the input. If these diode protection devices 240 are forward biased to the point of conduction no output will be provided from the read-only memory. This is termed the protection state of the memory. When the read-only memory is in the protection state, even if a digital input is received, this input will be shorted to ground, whereby no output is provided.

The source of reference potential 140 which is connected to the ladder network 136 is preferably chosen to be a value less than the forward bias potential of the protection devices 240 so that the read-only memory will remain in the operating state, which is the state in which an output can be produced, for all time. Typically, the value of this reference potential for most read-only memories is 3 to 5 volts for a ladder network where R is approximately 50,000 ohms and 2R is approximately 100,000 ohms. This reference potential which is fed through the ladder network 136, maintains the sources and drains of the output field effect transistors at a potential close to the substrate voltage of the MOS memory which insures that the drain-to-substrate and source-to-substrate junctions will not be forward biased, as well as preventing the protection devices 240 from being forward biased to the point of conduction.

FIGS. 5 and 6 refer to alternative embodiments of the read-only memory-ladder network configuration described above with reference to FIG. 4. Preferably, these alternative embodiments are of the type disclosed is my copending U. S. Pat. application Ser. No. 92,125, filed Nov. 23, 1970 and entitled APPARATUS FOR PROVIDING AN ANALOG OUTPUT IN RESPONSE TO A DIGITAL INPUT, and assigned to the same assignee, which disclosure is hereby incorporated by reference. These embodiments will not be described in greater detail hereinafter as the disclosures thereof have been incorporated by reference. Suffice it to say that in the alternative embodiment shown in FIG. 5 no source of reference potential is applied through the ladder network 136 to the memory 122. Instead, the analog signal input, which may preferably be a reference signal of between 3 to 5 volts, is applied from a signal source 242 via a parallel connection to the uncoupled drain electrode 230 of each of the FET transistor pairs 132-134. The output of the R2R ladder network 136 is connected in conventional fashion to the summing junction of the operational amplifier summing means 146. The opposite end of the ladder network 136 is connected to ground. In the embodiment shown in FIG. 5, level shifting of the signal is accomplished to compensate for the positive and negative voltage deviation or swing of the analog input signal so as to maintain the sources and drains of the output field effect transistors 132-134 at a potential close to the substrate voltage of the MOS memory 122 which insures that the drain-to-substrate and source-tosubstrate junctions will not be forward biased, as well as preventing the protection devices 240 from being forward biased to the point of conduction. This level shifting is accomplished by preferably connecting the uncoupled source electrode 220 to a source of reference potential 244 having, by way of example, a positive potential value of between 3 and 5 volts. In addition, a second source of reference potential 246 which, by way of example, is preferably a negative potential such that the most positive deviation of the analog input signal is never greater than the substrate potential of the MOS memory 122, is connected to the memory 122.

With respect to the alternative embodiment shown in FIG. 6, suffice it to say that the read-only memory means 122 of this embodiment is preferably identical to that previously described with reference to FIG. 4 with the exception that no diode protection devices are employed. In this instance, prevention of the forward biasing of such protection devices to the point of conduction is not a consideration. The ladder network 136 is connected to the output portion 128 of the read-only memory means 122 in a manner similar to the connection of the ladder network to the output portion of the read-only memory of FIG. 4 with the exception that the output of the ladder network is directly connected to the summing junction of the high gain operational amplifier 146. In this embodiment, the analog input signal is supplied from a source 248 via a path 250 where it is connected in parallel to the uncoupled drain electrode 230 of the FET transistor pairs 132-134. The uncoupled source electrodes 220 of the FET transistor pairs 132434 are connected in parallel via path 234 to ground. The opposite end of the ladder network 135 from that which is connected to the summing junction is also connected to ground. Except for the absence of the diode protection devices and the associated means for preventing these devices from being forwardbiased to the point of conduction, the operation of the embodiment shown in FIG. 6 is identical to that previously described with reference to the embodiment shown in FIG. 4 and will not be described in greater detail hereinafter.

SERVO STAGE Referring now to FIGS. 7, 8, and 9 describing the servo stage 54 in greater detail. The servo amplifier 56 is substantially a conventional servo amplifier configuration as shown and preferred in FIG. 7 comprising a two speed coarse-fine selector switch, pre-amplifier, peak sampling demodulator, a power amplifier and a servo null detector. A conventional two-speed diode switch 52 associated with the servo network 54 transfers servo loop follow-up from coarse to fine at a predetermined altitude from the fine servo null. This point is chosen to assure a smooth transition from coarse to fine follow-up resolver information and precludes ambiguous null position on the fine follow-up resolver. The output of the two-speed diode switch 52 is fed into a conventional pre-amplifier 300 built around a high gain integrated circuit operational amplifier. The output of this pre-amplifier 300 is operatively connected to a peak sampling demodulator 302 which provides quadrant rejection without inducing excessive lag. The output of the peak sampling demodulator is connected to a holding capacitor 304 for charging the capacitor 304 at the peak of the signal sine wave. Capacitor 304 is buffered by another high gain operational amplifier 306 which provides a driving signal for the brushless D. C. motor 60. This will be explained in greater detail hereinafter. The brushless D. C. motor rate generator 58-60 includes a pair of

Hall effect sensors

308 and 310 which are operatively connected in parallel to the output of operational amplifier 306. The outputs of the

Hall sensors

308 and 310 are operatively connected to

differential amplifiers

312 and 314, respectively. These

differential amplifiers

312 and 314 are operatively connected to the

motor drive windings

316 and 318, respectively through respective complementary symmetry output stages 320 and 322. Preferably, as will be explained in greater detail hereinafter, the

sensors

308 and 310 are connected to

independent generator windings

321 and 323, respectively, whose outputs are scaled by

series resistors

324 and 326, respectively and are summed with the

respective Hall sensors

308 and 310. This provides null-free direct rate sensing since the voltage on these windings is proportional to the angular velocity of the rotor of the brushless D. C. motor by the equation Eganw[sin(wt) Preferably, if desired, non-linear damping action may be provided for the brushless D. C. motor rate generator 58-60 by placing a capacitor across each of the two

generator windings

321 and 323, as shown in dotted lines in FIG. 7, in order to take advantage of the variable frequency component of this rate signal. As the phase shift from the generator passes through 90, the rate generator damping coefficient reduces to zero; and as the angular velocity increases, the generatorprovides a positive feedback signal.

BRUSHLESS D. C. MOTOR RATE GENERATOR As was previously mentioned, the brushless D. C. motor rate generator 5860 is preferably of the type disclosed in my copending U. S. Pat. application Ser. No. 54,387, filed July 13, 1970 and entitled BRUSH- LESS D. C. MOTOR, and assigned to the same assignee, which disclosure has been incorporated by reference. Therefore, this motor rate generator 58-60 will not be described in greater detail hereinafter except for portions of this disclosure which will be reproduced hereinafter only for purposes of clarity.

Referring now to FIGS. 7, 8 and 9 and describing in greater detail the preferred brushless D. C. motor rate generator 58-60 portion of the servo stage 54 of the altitude indicator 10 of the present invention. The brushless D.C. motor 60, which may be a conventional brushless D. C. motor such as the type readily available from Siemans Corporation of America, is preferably a multispeed motor and preferably includes an excitation stator, generally referred to by the reference numeral 328, preferably consisting of the two

perpendicular excitation windings

316 and 318, respectively, which are commonly termed the cosine and sine windings, respectively. These

excitation windings

316 and 318, preferably, each have an equal number of turns of wire and are of substantially equal resistance for a purpose to be described in greater detail hereinafter. The motor 60 also, preferably, includes a magnetic rotor, generally referred to by the reference numeral 334, rotatably positioned in magnetic relation with the

stator excitation windings

316 and 318. As shown and preferred, the rotor 334 includes a permanent magnet 336 which is supported by a shaft 338 for rotation.

As shown and preferred, the two magneto-sensitive conventional

Hall Effect sensors

308 and 310, are angularly displaced apart from each other, preferably at an angle of If desired

Hall sensors

308 and 310 could be replaced by any other magnetic flux sensor which provides a signal proportional to magnetic flux, such as magnetically sensitive transistors which are commercially available under the name Magnistor. Furthermore, as shown and preferred, the

sensors

308 and 310 are also angularly displaced 90 with respect to the magnetic axes 344 and 346 of the

excitation windings

316 and 318 respectively. Hall sensor 308 is angularly displaced 90 with respect to magnetic axis 344, and Hall sensor 310 is angularly displaced 90 with respect to magnetic axis 346. If desired, the angular displacement of the

Hall sensors

308 and 310 with respect to the respective magnetic axes 344 and 346 of the

excitation windings

316 and 318 could be any desired angle other than 90 such as 45.

Referring now to FIG. 9, the

additional stator windings

321 and 323 which are, preferably, magnetically independent of

stator excitation windings

316 and 318 are provided in order to provide direct rate sensing, as will be described in greater detail hereinafter.

Stator windings

321 and 323 are wound on a second stator stack to prevent direct coupling to the

excitation windings

316 and 318. These

independent stator windings

321 and 323 are, preferably, perpendicular to each other. Stator winding 321 is, preferably, aligned with the magnetic axis of Hall sensor 308, and independent stator winding 323 is, preferably, aligned with the magnetic axis of Hall sensor 310. Each

Hall sensor

308 and 310 includes a pair of

input terminals

352 and 354, and

356 and 358, respectively, which are each displaced 180 apart from each other, and a pair of

output terminals

360 and 362 and 364 and 366, respectively, which are also each displaced 180 apart from each other. Each of the terminals 352 through 366, inclusive, is associated with an electrode of the

respective Hall sensors

308 and 310 to either apply an electrical potential thereto or to pick up an electrical potential therefrom.

Terminals

354 and 356 of

Hall sensors

308 and 310, respectively, are connected through

resistors

355 and 357, respectively which are connected in common, to the output of the high gain operational amplifier 306 to provide a current source for

sensors

308 and 310. Preferably, the value of

resistors

355 and 357 are equal and substantially greater than the internal impedance of the

respective Hall sensors

308 and 310 so as to provide a constant current source therefor. Independent stator winding 321 is connected in an independent feedback path 370 between output terminal 360 and output terminal 362 of the Hall sensor 308 to provide a direct rate feedback signal thereto in a manner to be described in greater detail hereinafter. The feedback path 370 preferably includes the scaling resistor 324 connected between the independent stator winding 321 and the output terminal 362 of the Hall sensor 308. The value of the scaling resistor 324 is chosen to be equivalent to the proportionality constant between the angular velocity of the rotor shaft 338 and the induced signal applied to the Hall sensor 308 through winding 321, so as to, preferably, provide a linear torque-speed relationship. The scaling resistor 324 provides a linear slope for the torque-speed curve of the motor which may be changed by merely changing the value of the resistor 324. If a non-linear torque-speed relationship is desired, the scaling resistor 324 may be replaced by a non-linear impedance such as a capacitor (not shown). Furthermore, resistor 324 in addition to the previously described scaling function also performs the function of providing a feedback signal which is substantially independent of variations in the internal impedance of the Hall sensor 308. If these functions are not desired, this scaling resistor 324 may be omitted.

A similar arrangement is, preferably, provided for Hall sensor 310 wherein an independent feedback path 374 between output terminal 364 and input terminal 358 is provided. This feedback path 374 includes the winding 323 and the other scaling resistor 326 whose functions are similar to those of scaling resistor 324 described above and which also may be omitted if these functions are not desired. Furthermore, if a non-linear torque-speed relationship is desired, resistor 326 could be replaced by a non-linear impedance, such as a capacitor (not shown).

Output terminal 360 and output terminal 362 of Hall sensor 308 are, preferably, connected to the differential input power amplifier 312, which is conventional and need not be described in greater detail hereinafter. Suffice it to say, the differential input power amplifier 312 includes two

input terminals

378 and 380, output terminal 360 being connected to input terminal 378 through an impedance, omitted in FIG. 9 for purposes of clarity, and output terminal 362 being connected to input terminal 380 through another impedance, omitted in FIG. 9 for purposes of clarity, and an output terminal 382 which output terminal 382 is connected to stator excitation winding 316 through complementary symmetry output stage 320 to provide a signal path thereto in a manner to be described in greater detail hereinafter.

Similarly, for Hall sensor 310, the other conventional differential input power amplifier 3l4'having input terminals 384 and 386 connected to output terminal 364 and output terminal 366, respectively, of Hall sensor 310 through respective impedances omitted in FIG. 9 for purposes of clarity, has an output terminal 388 which is connected to excitation winding 318 through complementary symmetry output stage 322 to provide a signal path thereto in a manner to be described in greater detail hereinafter.

Excitation windings

316 and 318, preferably, have their opposite ends connected together at a point 390 which is in turn connected to ground.

If desired, other servomechanisms, or other arrangements of brushless D. C. motor rate generators such as the alternative embodiments described in my copending U. S. application Ser. No. 54,387 previously incorporated by reference herein, may be utilized without departing from the present invention.

OPERATIQN Now describing in greater detail the operation of the altitude indicator 10 of the present invention. The altitude indicator 10 receives a differential altitude data word from the digital air data computer. This differential data signal is inserted into the data bus interface portion 12 where this signal is differentially sensed, integrated, and processed to provide a single ended data signal via path 18, a clock signal via path 20, and a clear pulse synchronized with the word sync gap via path 16 in a manner to be described in greater detail hereinafter. The differential altitude data word is fed into operational amplifier 92 which is operated in the differential configuration.

As was previously mentioned, the input impedance is set to provide a light balanced resistive loading of the data bus in a conventional manner. Amplifier 92 in this preferred configuration provides excellent common mode rejection and converts this differential data signal into the single ended data output signal supplied on path 18. Integrating

capacitors

94 and 96 associated with the differential amplifier 92 integrate this differential data input signal such that the time constant for this integrator insures rejection of noise pulses for a predetermined interval. The output of this differential integrator configuration is then fed into voltage comparator

operational amplifiers

98 and 100 which detect plus or minus deviations form a predetermined value, such as 5 volts, precluding false triggering due to static predetermined differential voltage levels on the data bus. Voltage comparator 98 provides the single ended data signal output to the shift register to network 22-24-26 via path 18. The output of voltage comparator 98 is also fed in parallel to OR gate 106 together with the output of comparator 100. These output signals are ORD to provide the clock or shift pulse via path 20 for the shift register network 222426 and the word sync gap generator or sensor 14.

This signal on path 20, which is fed in parallel to the shift register network 22-24-26 and to the word sync gap generator 14, is fed to the word sync gap generator 14 transistor input stage 108 which shorts the capacitor 110 of the unijunction transistor relaxation oscillator 112. The time constant (RC) at the emitter input is set to preferably fire the unijunction transistor 112 after a time corresponding to a preferred predetermined number of clock pulses, such as 2% clock pulses. When the clock signal is not generated for this predetermined time interval, the unijunction transistor 112 drives the common emitter transistor 114 into saturation which,

in turn, provides a clear pulse via path 16 through the shift register network 22-24-26 so as to clear the shift registers to prepare for the loading of a new data word. In this manner, the unijunction transistor 112 acts as a timing device for word synchronization.

The single ended data signal via path 18 is shifted into the shift register network 22-24-26 which provides parallel access to the altitude data word. As shown and preferred, the integrity of the shift register network 22-24-26 is monitored by pre-setting the first two stages of the shift register network 22-24-26 prior to shifting new information into the network 22-24-26. This preset information, which is provided by the address generator 39, is shifted to the last two stages of the shift register network 22-24-26 where it is read by the address decoder 28. The address decoder 28, which reads the valid address word, provides a valid address signal via path which signal is fed to NAND gate 32.

The altitude word present in the shift register network 22-24-26, following the shifting of the information, is preferably checked for odd parity by being fed to the conventional parity checker 38 whose operation need not be described in greater detail hereinafter. The parity checker 38 provides a valid output signal via path 36 when the parity is correct. In addition, the altitude data word preferably also contains the valid data bit which, as shown and preferred, is present in the first stage of the shift register network 22-24-26. This valid data bit is also fed, via path 34, to NAND gate 32. The three VALID signals present on

paths

30, 34, and 36 are then NANDD to provide the load command signal via path 41 to the read-only memories 122-124 of the digital-to-

resolver converters

40 and 42. The load command signal present on path 41 loads the parallel information present in the shift register network 22-24-26 in the

appropriate converters

40 and 42. As will be explained in greater detail hereinafter, the altitude data word which is loaded into the digital-to-

resolver converters

40 and 42 is converted into a fine resolver signal by converter 40 and a coarse resolver signal by converter 42. By way of illustration, converter 42 converts the ten most significant bits into a coarse resolver signal and feeds it to the coarse follow-up resolver 48 and converter 40 converts the ten least significant bits into a fine resolver signal which is fed to the fine follow-up resolver 46.

By way of illustration, the eight least significant bits of the respective 10 bit data word which is to be converted to the resolver compatible signal are fed into the two read-

only memories

122 and 124 which are programmed to generate a sine and'cosine quarter cycle binary output, respectively. As was previously mentioned, the read-only memory output stages are directly interface with the ladder networks 136 and 150 and DC reference voltage source 140 such that the outputs of the respective ladder networks 136 and are analog voltages whose range is from zero to the voltage of the reference source 140 and whose sinusoidal amplitude function is determined by the eight least significant bits of the 10 bit digital word. These output signals of the respective ladder networks 136 and 150 are fed into

buffer amplifiers

146 and 154, respectively,

through the

non-linear integrator networks

144 and 152, respectively.

An adequate time constant of these

networks

144 and 152 is selected such that the altitude noise is integrated out. Diodes 166 and 168 shunting resistor 158, and

diodes

170 and 172 shunting resistor 162 prevent undue lag for rapid altitude changes by providing, for altitude changes of greater than a predetermined low range value, such as 5 feet, a low resistance path to charge the respective capacitors for

network

144 and 164 for network 152 .to significantly reduce the RC time constant of the

respective integrators

144 and 152, such as by a factor of 1,000 to 1. The respective voltages present on the

integrated capacitors

160 and 164 is buffered by the unity gain

operational amplifiers

146 and 154, respectively. Outputs of these two

buffer amplifiers

146 and 154 represent two complementary sinusoidal quarter cycle signals. These complementary signals are each fed in parallel through unity

gain inverting amplifiers

176 and 184 respectively to provide out of phase complementary signals. The out of phase complementary outputs of

inverter amplifiers

176 and 184 and the non-inverted parallel outputs of

amplifiers

146 and 154 are then fed to the conventional 2-out-of-8 analog multiplexer 178.

As was previously mentioned, this multiplexer 178 is preferably an MOS multiplexer which contains eight zero offset low resistance analog switches operatively associated with terminals 188 through 202 inclusive, and an on-chip two bit decoder operatively associated with

terminals

203 and 205. The operation of the multiplexer 178 is conventional and need not be described in greater detail hereinafter. Suffice it to say that the two most significant bits of the 10 bit data words present in the

converter

40 or 42 select the appropriate quarter cycle so as to generate the proper full cycle (360) sinusoidal shaft angle function. As shown and preferred, the most significant bit of the ten bit digital word determines the phase of the output signal. This bit is fed through the Exclusive OR gate 204 which acts as a controlled true complement gate whose control input is the in phase square wave signal generated by source 206. In this manner the analog multiplexer 178 serves as a fully wave modulator. In accomplishing this modulator function, the multiplexer 178 converts the complementary DC signals, which are proportional to the sine and cosine of the digital shaft angle, into a pair of AC signals whose amplitudes are proportional to this shaft angle. These complementary AC signals are the signals which are then fed through the appropriate follow-up

resolvers

46 or 48 through buffer amplifiers 210 for the sine and 216 for the cosine.

The follow-up

resolvers

46 and 48 as was previously mentioned, and as shown and preferred, are connected to the display portion 64 and the motor portion 60 of the servo network 54 through the appropriate gearings 66 and 68 and to each other through appropriate gearing 50 so as to preserve the desired fine-coarse relationship, shown by way of illustration as being 64:1. The respective sine windings of the fine and coarse follow-up

resolvers

46 and 48 are fed into the conventional twospeed diode switch 52, the two-speed diode switching network 52 transferring servo loop follow-up from coarse to fine at a predetermined equivalent altitude deviation from the fine servo null so as to assure smooth transition from coarse to fine follow-up resolver information and preclude ambiguous null position in the fine follow-up resolver 46.

As will be described in greater detail hereinafter, the output of the conventional two-speed diode switch 52 is then fed to the servo network 54 where it is summed at junction 62 of the generator signal 58 and passed to the servo amplifier 56 to provide the driving signal for the servo motor 60. The output signal of the two-speed diode switch 52 is fed into the pre-amplifier portion of the servo network 54, which portion is built around the high gain integrated circuit operational amplifier 300. The output of this pre-amplifier 300 is then fed to the peak sampling FET demodulator 302 which, in turn, charges the capacitor 304 at the peak of the signal sine wave, demodulator 302 and capacitor 304 acting as a sample-and-hold storage network to preserve the associated value of angular velocity for the motor representative of the synchro signal. The DC error signal which is present on holding capacitor 304 is buffered by high gain operational amplifier 306 which provides the driving signal for the

Hall Effect sensors

308 and 310 of the brushless DC motor rate generator 58-60.

The output of the

Hall sensors

308 and 310 are differentially amplified by

respective amplifiers

312 and 314 and fed through the motor drive or

excitation windings

316 and 318 by the respective complementary-symmetry output stages 320 and 322. The respective outputs of the

generator windings

321 and 323 are scaled by the

resistors

324 and 326, respectively, located in the respective independent feedback paths, which signals are summed with the

respective Hall sensors

308 and 310. In this manner, null-free direct rate sensing is provided as the voltage present on the

respective generator windings

321 and 323 is proportional to the angular velocity of the brushless DC motor rate generator rotor 334 by the equation Eg anw[sin (wt)], where w is the equivalent to the angular velocity of the rotor 334. If a capacitor is placed across each of the

generator windings

321 and 323 in order to take advantage of the variable frequency component of the rate signal, as the phase shift from the generator passes through 90, the rate generator damping coefficient reduces to zero and, as the angular velocity increases, the generator provides a positive feedback signal. This servo analog driving signal is utilized to drive the altitude counter mechanism 70 and pointer 80 to provide a visual display of the dynamic altitude condition of the aircraft. As was previously mentioned, barometric correction is preferably provided by means of the nonlinear potentiometer 84 geared directly to the barometric counter 86. The output of the potentiometer 84 is linear with effective altitude correction and is utilized to'feed the digital air data computer to correct for local barometric readings.

ALTERNATIVE EMBODIMENT If desired, one digital-to-resolver converter could be utilized in place of the preferred two

converters

40 and 42. The digital-to-resolver converter configuration, in' such instance, would preferably be the same as that described previously with reference to FIG. 3 with the exception that in such instance, the eight least significant bits of the bit digital word would be fed into the pair of read-only memories. In such instance, the shift register network preferably includes five eight-bit shift registers. One of the shift registers comprising the shift register network, in such instance, is loaded with eight bit positions for the fine resolver word and eight different bit positions for the coarse resolver words. The selective loading of the eight least significant bits is controlled by a coarse/fine selector latch. In such a network, to minimize the bit conversion requirement and improve the resolver follow-up accuracy, a two speed servo loop is preferably utilized. A preselected periodic valid altitude word, such as every sixteenth valid altitude word, is utilized to set a RS Flip Flop which gates the appropriate eight least significant bits into the shift register for the coarse resolver conversion. This flip flop would also gate the rotor signal from the coarse resolver into the servo amplifier connecting the coarse resolver into the servo loop. A null detector at the input of the servo amplifier would reset the flip flop when a null is present, gating the appropriate bit positions for fine conversion into the shift register. Simultaneously, the rotor of the fine resolver would be switched to the input of the servo amplifier thereby connecting the fine resolver back into the servo loop. By utilizing such a switching arrangement, the requirement for a second digital-to-resolver converter is obviated. In addition, the two most significant bits selection of the coarse or fine resolver signal is loaded by this flip flop into a two bit holding register which subsequently feeds this information to the multiplexer.

By utilizing the altitude indicator of the present invention, a system which combines the implementation of an analog point of display with an altitude counter presentation which can be interfaced with a digital air data computer so as to provide a digitally compatible system is provided.

It is to be understood that the above described embodiments of the invention are merely illustrative of the principles thereof and that numerous modifications and embodiments of the invention may be derived with the spirit and scope thereof.

Whatis claimed is:

1. An apparatus for providing an analog indication of altitude in response to a digital altitude information signal comprising means for providing an analog synchro signal in response to said digital altitude information signal, said analog synchro signal being proportional to said altitude information signal, said synchro signal providing means including means for damping said synchro signal so as to substantially eliminate any altitude signal noise component present in said altitude information signal, said damping means comprising integration means for integrating said altitude signal noise component to substantially eliminate said noise component, said integration means having an associated time constant of a value which enables said noise component to be integrated out and comprising means for reducing said associated time constant when a variation in the value of said analog synchro signal exceeds a predetermined value of said analog synchro signal whereby undue lag for rapid variations in said analog synchro signal value is minimized;

servo means for providing an analog servo driving signal in response to said synchro signal, means connecting said servo means to said synchro signal providing means, said noise damped synchro signal being fed to said servo means for providing said servo driving signal;

means for providing an analog display as said altitude indication in response to said servo driving signal; and

means connecting said servo means to said display means. 1

2. An apparatus in accordance with claim 1 wherein said integration means associated time constant comprises an R-C time constant, said integration means comprising a chargeable capacitance means, a first charging path therefor having a predetermined impedance for providing said associated R-C time constant and a second charging path therefor connected in parallel with said first charging path, said second charging path comprising said reducing means and including means providing a substantially higher impedance therefor than said first path when said analog synchro signal value is below said predetermined value and a substantially lower impedance therefor than said first path when said analog synchro signal value is above said predetermined value, said means being enabled to provide said lower impedance when said predetermined value is exceeded.

3. An apparatus in accordance with claim 2 wherein said impedance providing means comprises diode means for providing an open circuit path for said second path when said analog synchro signal value is below said predetermined value and a short circuit path for said second path when said analog synchro signal value exceeds said predetermined value.

4. An apparatus in accordance with claim 1 wherein said integration means is non-linear.

5. An apparatus in accordance with claim 1 wherein said servo means includes means for further damping said synchro signal so as to substantially eliminate any altitude signal noise component present in said altitude information signal, said noise damped synchro signal being fed to said analog display means.

6. An apparatus in accordance with claim 1 wherein said synchro signal providing means includes means for providing a coarse synchro signal proportional to said altitude information signal and a fine synchro signal proportional to said altitude information signal, said coarse signal being proportionally related to said fine signal, said servo means being operatively connected to said synchro signal providing means for providing said servo driving signal in response to said fine synchro signal and said coarse synchro signal.

7. An apparatus in accordance with claim 6 wherein said apparatus includes at least a two-speed switching means for operatively connecting said servo means to said synchro signal providing means for selectively passing either said coarse synchro signal or said fine synchro signal to said servo means for providing said servo driving signal in response to said selectively passed synchro signal, said switching means passing said coarse synchro signal above a predetermined altitude level and passing said fine synchro signal below a predetermined altitude level, said switching means transferring from passing said coarse synchro signal to passing said fine synchro signal at said predetermined level.

8. An apparatus in accordance with claim 7 wherein said servo means includes a multispeed servomechanism for driving said altitude display means in response to said servo driving signal.

9. An apparatus in accordance with claim 1 wherein said synchro signal providing means includes a read only memory means having an input portion and an output portion, said digital signal being operatively fed to said input portion, said input portion being programmed to provide a sinusoidal function of said digital signal in response to said digital signal; and

binary scaling means operatively connected to said memory means output portion for scaling said digital signal to provide said analog synchro signal in accordance with said sinusoidal function.

10. An apparatus in accordance with claim 9 wherein said binary scaling means is an R-ZR impedance ladder network.

11. An apparatus in accordance with claim 9 wherein said memory means output portion includes a bistable switching means, said bistable means including a seri-,

ally coupled sink-source pair of field effect transistors each having a source electrode, a drain electrode and a gate electrode with the source electrode of one transistor of said transistor pair being coupled to the drain electrode of the other transistor of said transistor pair, said scaling means being operatively connected to said source-drain electrode couple.

12. An apparatus in accordance with claim 9 wherein said synchro signal providing means further includes a source of reference potential operatively connected to said memory means, and summing means having an input and an output, said summing means input being operatively connected to said sealing means, said scaling means having a total impedance value and a scaled impedance value equivalent to a binary equivalent of said digital signal, said summing means output being said analog synchro signal, said summing means output having a magnitude proportional to said reference potential and a ratio of said sealing means scaled impedance to said scaling means total impedance.

13. An apparatus in accordance with claim 9 wherein said digital signal comprises a plurality of bits, said plurality of hits including digital angular information bits and quadrant location bits, said angular information bits indicating a digital angular equivalent between 0 and and said quadrant location bits indicating a quadrant of 360 in which said equivalent digital angle is located, said synchro signal providing means further including means for providing said synchro signal as an analog sinusoidal function of a digital angle between 0 and 360 from said angular information and said quadrant location bits.

14. An apparatus in accordance with claim 13 wherein said read only memory means input portion is programmed to provide said analog sinusoidal function as a function of a digital angle between 0 and 90 and said analog 0 to 360 analog sinusoidal function providing means includes multiplexer switching means operatively connected to said binary scaling means through said integration means for providing said 0 to 360 analog function from said sinusoidal function of a digital angle between 0 and 90 and said quadrant location bits.

15. An apparatus in accordance with claim 14 wherein said analog sinusoidal function providing means includes unity gain inverting means operatively connected to an input of said multiplexer and to said binary scaling means for providing said 0 to 90 sinusoidal function as an input to said multiplexer, and at least one of said quadrant location bits being provided as another input to said multiplexer.

16. An apparatus in accordance with claim 14 wherein said analog sinusoidal function providing means includes a controlled true complement gating means having a control input and a signal input and an output, said gating means output being operatively connected to an input to said said multiplexer, one of said quadrant location bits being fed to said gating means signal input, the other of said quadrant location bits being fed to said multiplexer; and said analog sinusoidal function providing means further including square wave generation means, said square wave generation means being operatively connected to said gating means control input, whereby said multiplexer provides full wave modulation for said sinusoidal function for providing an AC analog signal output whose amplitude is proportional to said to 360 digital angle as said 0 to 360 analog function.

17. An apparatus in accordance with claim 1 wherein said analog display means includes altitude counter display means and analog pointer means, said counter means including geneva drive means.

18. An apparatus in accordance with claim 17 wherein said counter means includes rotary drum means having a least significant increment rotary drum portion and a next to least significant increment rotary drum portion, said drive means being a star wheel geneva drive means for enabling transfer between said least significant drum portion and said next to least significant portion.

19. An apparatus in accordance with claim 1 wherein -said servo means comprises a brushless DC. motor having a first stator, a magnetic rotor rotatably positioned in magnetic coupled relation with said first stator, a magnetic flux sensor means positioned in fixed relation to said rotor for sensing the magnitude of the rotor flux density as a sinusoidal function of angular position of the rotor and producing said servo driving signal proportional thereto; a second stator having a winding electrically independent from said first stator and positioned in magnetic coupled relation with said rotor; and an independent feedback path for said sensor v wherein said first stator comprises first and second windings electrically angularly displaced from each other and said magnetic flux sensor means comprises first and second sensors angularly displaced with respect to each other and to said first stator first and second windings, respectively.

23. An apparatus in accordance with claim 22 wherein said second stator further comprises a second stator winding; each sensor has an associated independent feedback path for said sensor, said first sensor feedback path including said second stator first winding and second sensor feedback path including said second stator second winding.

24. An apparatus in accordance with claim 6 wherein said apparatus further includes means operatively connected to said servo means and to said synchro signal providing means for switching from said fine synchro signal to said coarse synchro signal at a predetermined transition point to selectively provide only one of said signals to said servo means; said display means includes a rotary analog pointer means operatively driven in response to said servo driving signal, said driven rotary pointer having an associated value of angular velocity at said transition point; and said servo means includes sample-and-hold storage means for receiving said selected synchro signal and preserving said associated angular velocity value.

Claims

1. An apparatus for providing an analog indication of altitude in response to a digital altitude information signal comprising Means for providing an analog synchro signal in response to said digital altitude information signal, said analog synchro signal being proportional to said altitude information signal, said synchro signal providing means including means for damping said synchro signal so as to substantially eliminate any altitude signal noise component present in said altitude information signal, said damping means comprising integration means for integrating said altitude signal noise component to substantially eliminate said noise component, said integration means having an associated time constant of a value which enables said noise component to be integrated out and comprising means for reducing said associated time constant when a variation in the value of said analog synchro signal exceeds a predetermined value of said analog synchro signal whereby undue lag for rapid variations in said analog synchro signal value is minimized; servo means for providing an analog servo driving signal in response to said synchro signal, means connecting said servo means to said synchro signal providing means, said noise damped synchro signal being fed to said servo means for providing said servo driving signal; means for providing an analog display as said altitude indication in response to said servo driving signal; and means connecting said servo means to said display means.

9. An apparatus in accordance with claim 1 wherein said synchro signal providing means includes a read only memory means having an input portion and an output portion, said digital signal being operatively fed to said input portion, said input portion being programmed to provide a sinusoidal function of said digital signal in response to said digital signal; and binary scaling means operatively connected to said memory means output portion for scaling said digital signal to provide said analog synchro signal in accordance with said sinusoidal function.

10. An apparatus in accordance with claim 9 wherein said binary scaling means is an R-2R impedance ladder network.

11. An apparatus in accordance with claim 9 wherein said memory means output portion includes a bistable switching means, said bistable means including a serially coupled sink-source pair of field effect transistors each having a source electrode, a drain electrode and a gate electrode with the source electrode of one transistor of said transistor pair being coupled to the drain electrode of the other transistor of said transistor pair, said scaling means being operatively connected to said source-drain electrode couple.

12. An apparatus in accordance with claim 9 wherein said synchro signal providing means further includes a source of reference potential operatively connected to said memory means, and summing means having an input and an output, said summing means input being operatively connected to said scaling means, said scaling means having a total impedance value and a scaled impedance value equivalent to a binary equivalent of said digital signal, said summing means output being said analog synchro signal, said summing means output having a magnitude proportional to said reference potential and a ratio of said scaling means scaled impedance to said scaling means total impedance.

13. An apparatus in accordance with claim 9 wherein said digital signal comprises a plurality of bits, said plurality of bits including digital angular information bits and quadrant location bits, said angular information bits indicating a digital angular equivalent between 0* and 90* and said quadrant location bits indicating a quadrant of 360* in which said equivalent digital angle is located, said synchro signal providing means further including means for providing said synchro signal as an analog sinusoidal function of a digital angle between 0* and 360* from said angular information and said quadrant location bits.

14. An apparatus in accordance with claim 13 wherein said read only memory means input portion is programmed to provide said analog sinusoidal function as a function of a digital angle between 0* and 90* and said analog 0* to 360* analog sinusoidal function providing means includes multiplexer switching means operatively connected to said binary scaling means through said integration means for providing said 0* to 360* analog function from said sinusoidal function of a digital angle between 0* and 90* and said quadrant location bits.

15. An apparatus in accordance with claim 14 wherein said analog sinusoidal function providing means includes unity gain inverting means operatively connected to an input of said multiplexer and to said binary scaling means for providing said 0* to 90* sinusoidal function as an input to said multiplexer, and at least one of said quadrant location bits being provided as another input to said multiplexer. 16. An apparatus in accordance with claim 14 wherein said analog sinusoidal function providing means includes a controlled true complement gating means having a control input and a signal input and an output, said gating means output being operatively connected to an input to said said multiplexer, one of said quadrant location bits being fed to said gating means signal input, the other of said quadrant location bits being fed to said multiplexer; and said analog sinusoidal function providing means further including square wave generation means, said square wave generation means being operatively connected to said gating means control input, whereby said multiplexer provides full wave modulation for said sinusoidal function for providing an AC analog signal output whose amplitude is proportional to said 0* to 360* digital angle as said 0* to 360* analog function.

19. An apparatus in accordance with claim 1 wherein said servo means comprises a brushless D.C. motor having a first stator, a magnetic rotor rotatably positioned in magnetic coupled relation with said first stator, a magnetic flux sensor means positioned in fixed relation to said rotor for sensing the magnitude of the rotor flux density as a sinusoidal function of angular position of the rotor and producing said servo driving signal proportional thereto; a second stator having a winding electrically independent from said first stator and positioned in magnetic coupled relation with said rotor; and an independent feedback path for said sensor means, said independent feedback path including said second stator winding whereby direct rate feedback control for the sensor means is provided.

20. An apparatus in accordance with claim 19 wherein said sensor is capable of producing a voltage which is proportional to a sinusoidal function of the combined angular position of the rotor and the angular position of the sensor with respect to the first stator.

21. An apparatus in accordance with claim 19 wherein said magnetic flux sensor means is a Hall effect sensor means.

22. An apparatus in accordance with claim 19 wherein said first stator comprises first and second windings electrically angularly displaced from each other and said magnetic flux sensor means comprises first and second sensors angularly displaced with respect to each other and to said first stator first and second windings, respectively.