US3798463A

US3798463A - Switch control system

Info

Publication number: US3798463A
Authority: US
Inventors: S Ikeguchi; N Yamashita
Original assignee: Tokyo Sanyo Electric Co Ltd; Sanyo Electric Co Ltd
Current assignee: Sanyo Electric Co Ltd
Priority date: 1971-10-28
Filing date: 1972-10-24
Publication date: 1974-03-19
Anticipated expiration: 1991-03-19
Also published as: GB1415199A; DE2252903B2; JPS5227793B2; DE2232903A1; JPS4865390A; DE2232903C3; DE2232903B2; DE2251332A1; DE2252903C3; DE2252903A1

Abstract

A switch control system of the present invention comprises a plurality of channels each comprising an individual input terminal and a flip-flop, and a clock pulse generator for generating clocks in response to an individual selection signal applied to any one of the channels. The said individual selection signal is written and stored in the flip-flop of the corresponding channel as a function of the clocks for bringing the channel in an active state. A switch control system of a preferred embodiment is also capable of being controlled with a common selection signal applied to a common input terminal as well as the individual selection signals to be applied individually to the respective individual input terminals by means of a ring counter connection formed between the respective flip-flops. In accordance with another embodiment a chain of pulses is applied in a remote control manner to the common input terminal and the first portion of the chain pulses is used to forcibly return the system in an initial condition in which a predetermined flip-flop is in an active state, while the remaining portion of the chain pulses is used to shift the active state in the flip-flops connected in a ring counter manner depending upon the number of chain pulses as determined by manual individual selection.

Description

United States Patent Ikeguchi et al.

[4 1 Mar. 19, 1974 SWITCH CONTROL SYSTEM Gumma-ken, both of, Japan Filed: Oct. 24, 1972 Appl. No.: 300,224

Primary Examiner-Robert K. Schaefer Assistant ExaminerM. Ginsburg Attorney, Agent. or FirmStaas. Halsey & Gable [57] ABSTRACT A switch control system of the present invention comprises a plurality of channels each comprising an individual input terminal and a flip-flop, and a clock pulse generator for generating clocks in response to an individual selection signal applied to any one of the channels. The said individual selection signal is written and [30] Foreign Application priority Data stored in the flipflop of the corresponding channel as O t 28 19 J 46 85873 a function of the clocks for bringing the channel in an 1971 Japan 46485874 active state. A switch control system of a preferred 1971 46:85875 embodiment is also capable of being controlled with a I 1971 'i "46403052 common selection signal applied to a common input p terminal as well as the individual selection signals to [52] U S Cl 307/125 328/15.) I be applied individually to the respective individual [51] nicer. H6111 47/06 input terminals by means of a ring counter connectim [58] Field of Search 307/125 149 252 formed between the respective flip-flops. in accor- 34O/258 163', 5 dance with another embodiment a chain of pulses is 103 applied in a remote control manner to the common input terminal and the first portion of the chain pulses [56] References Cited is used to forcibly return the system in an initial condition in which a predetermined flip-flop is in an active UNITED STATES PATENTS state, while the remaining portion of the chain pulses 3.191770 7/1965 Marshall 328/155 is used to shift the active state in the flip-flops con- 3344-369 W966 Nasslmbene 342/365 C nected in a ring counter manner depending upon the 3530310 9/1970 Adelson et 340/58 C X number of chain pulses as determined by manual individual selection.

20 Claims, 14 Drawing Figures 0ND CH/\ 0 l ,Q/ P/ GNU l CHZ\ g1 T i E F2 F2 12 P2 0ND l v T i R3 [1' p F] H 0)? ma T P I I 1 [/7 PM /l l '/'Z PATENTEDMAR 1 9 I974 SHEET 1 BF 9 Z 7J\|0 0 0 U 0 H Wu 0 Wm Z\ II I. I! w n m m m j M D N T D D. D N ET ET QT A \H H m H 1 Z. 3 H H H n G p H H p PATENTEDMAR19 I974 3798;463

SHEET 5 UF 9 VD m 101%" W I l 1| K g I J H V y l (a) (d) [0 H I 3.05) 3 L I I M d from P/ [V] p15 1 7 n TH (d) FIG. 5

PATENTEDMAR 19 1914 37983163 SHEET 8 BF 9 @WWHTJ m u SWITCH CONTROL SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch control system, and more specifically to such a system in which any one of a plurality of circuits is selectively brought into an active state upon application of an individual selection signal to the corresponding'circuit for providing an output selection signal therefrom.

2. Description of the Prior Art;

In reception of the television broadcast, it is necessitated to select a desired channel out of several television broadcast channels. One of the typical circuit selectors so far employed in selection of television channels is a rotary switch. However, a rotary switch usually makes a circuit through a mechanical touch between paired contacts performed by a manual rotating operation. For this reason a rotary switch always suffers fatally from a poor electrical contact between the paired contacts caused by deterioration of the contact surfaces, a tiresome manual operation and a noise caused by rotating operation thereof.

Another typical circuit selector suitable for selection of television channels in a multi-circuit push-button switch. Again, however, the push-button switch involves the same shortcoming of a poor electrical contact on the same ground asthe rotary switch.

Recently a television channel selecting apparatus for selecting VHF television channels employing a voltage controlled variable capacitor has been proposed and will be expected to be widely used in the future. Such a voltage controlled variable capacitor uses a capacitance formed at a barrier portion of a diode, variable as a function of a reverse voltage applied thereto, and is also known as a variable capacitance diode. In such a television channel selecting apparatus, it is necessary to use a control system in which any one of a plurality of circuits is selectively brought in an active state or a signal storing state upon individual manual selection for providing an output signal from the corresponding circuit. In view of implementing the channel selecting v circuit by means of solid state components, it is also preferred toimplement the switch control system by means of solid. state components.

A television channel selecting apparatus of a remote control type has also been proposed and in practical use. .In such circumstance the apparatus is supplied with a common selection signal via a common input circuit in lieu of individual selection signals to be applied individually to the corresponding circuits. It is again preferred to provide asolid state switch control system in which any one of a plurality of circuits is selectively brought in an active state upon application of a common selection signal via a common input circuit as well as of an individual selection signal to the corresponding circuit for providing an output selection signal therefrom.

I SUMMARY OF THE INVENTION A switch control system in accordance with the basic feature of the present invention comprises a plurality of channels or circuits, each comprising an individual input terminal and a store device, and a clock pulse generator for generating clocks in response to an individual selection signal applied to any one of the channels. The said individual selection signal is written and stored in the storedevice of the corresponding channel as a function of the clocks generated in response to application of the said individual selection signal, thereby bringing the corresponding channel in an active state. A flip-flop implemented with field effect transistors is advantageously used as a store device operable in rean initial condition in which only one channel is in an active state in response to turning on of the power circuitry of the system so that an undesired situation may be avoided in which more than twochannels are in an active state.

In a further preferred embodiment of the present invention, there is provided a pulse chain generator,

which generates a chain of pulses in response to individual selection of individual inputs, the number of which pulses is determined depending upon the selected input. The chain of pulses is applied to the common input terminal and is separated into a first portion and a second portion. The first portion of the chain of pulses is applied to areturn control circuit for forcibly returning the system in an initial condition in which a predetermined store device is in an active state and the second portion of the chain of pulses is applied to the ring counter connected store devices for shifting the active state in the ring counter connected store devices depending upon the number of pulses in the said second portion of the chain of pulses. Advantageously, the chain of pulses is generated in a pulse chain generator provided in a remote stationand is transmitted to the switch control system of the present invention via a transmission path suitable for a remote control purpose. r I

Therefore, an objectof the present invention-is to provide an improved switch control system in which any one of a plurality of circuits is selectively brought in an active state or a signal storing state upon application of an individual selection signal to the corresponding circuit for providing an output selection signal therefrom.

Another object of the present invention is to provide an improved switch control system in which any one of a plurality of circuits is selectively brought in an active state or a signal storing state upon application of an individual selection signal to the corresponding circuit or 'upon application of a common selection signal to a common input means for providing an output selection These objects and other objects and features of the present invention will be apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a block diagram of a switch control system embodying the basic feature of the present invention,

FIG. 2 shows a schematic diagram of a flip-flop for use in the system shown in FIG. 1,

FIG. 3 shows a schematic diagram of another example of an input terminal for use in the system shown in FIG. 1,

FIG. 4 shows a block diagram of a clock source shown in FIG. 1,

FIG. 5 shows waveforms at various portions of the clock source shown in FIG. 4,

FIG. 6 shows a block diagram of a switch control system of another embodiment of the present invention,

FIG. 7 shows a block diagram of a return control circuit for use in the system shown in FIG. 6,

FIG. 8 shows waveforms at various portions of the return control circuit shown in FIG. 7,

FIG. 9 shows a block diagram of a switch control system of a further embodiment of the present invention,

FIG. 10 shows a block diagram of a signal separation circuit for use in the system shown in FIG. 9,

FIG. 11 shows a schematic diagram of the signal separation circuit shown in FIG. 10,

FIG. 12 shows waveforms at various portions of the signal separation circuit shown in FIG. 11,

FIG. 13 shows in a block form an example of the circumstance wherein the switch control system of the present invention can be advantageously employed, and

FIG. 14 shows a detailed block diagram of a pulse chain generator shown in FIG. 13.

In the drawings like reference characters designate like portions.

DESCRIPTION OF THE PREFERRED EMBODIMENTS:

Refering to the drawings, a switch control system embodying the basic feature of the present invention is shown in FIG. 1 in a block form. The system shown comprises a plurality of circuits or channels CH1, CH2, CH3, CHn, at least one of which is to be selectively in an active state or in a signal storing state for providing a selection signal at an output of the corresponding channel in accordance with the present invention. The channels CH1, CH2, CH3, Cl-In each comprise electrode plates P1, P2, P3, Pn for an individual touch by a portion of a human body such as a finger for the purpose of selectively introducing an individual selection input signal into a desired channel, flip-flops F1, F2, F3, Fn for storing the introduced selection signal, inverters I], I2, I3, In, and output terminals 01, O2, O3, On, respectively, these components being connected in a well-known cascade fashion in the order as mentioned above. In the embodiment shown, all the flops F1, F2, F3, Fn are operable as a function of a clock pulse applied thereto. An example of such flipflop will be described in more detail subsequently with reference to FIG. 2. Resistors R1, R2, R3, Rn of high resistance are inserted between the elctrode plates P1, P2, P3, Pu and the inputs of the flip-flops F1, F2, F3, Fn, respectively, each of which inputs is also connected to the ground potential through a parallel circuit of a resistor and a capacitor so that the input of the flip-flop is clamped to the ground potential or the so-called high level or a logic one at a normal condition or at a situation where no selection signal is applied to the input of the flip-flop. It is pointed out that the flipflops F1, F2, F3, Fn are operable as a function of a clock pulse applied thereto. As to be more fully described subsequently, the flip-flops F1, F2, F3, Fn each comprise two stages, as shown divided by dotted lines, which are operated with the first clock 421 and the second clock (#2, respectively, supplied by a clock generator CL. The detail of the clock generator CL will be described in more detail subsequently with reference to FIGS. 4 and 5. The input of the clock generator CL is an output of an AND gate A, inputs of which are obtained from the inputs of the flip-flops F1, F2, F3, Fn.

Now the operation of the system shown in FIG. 1 will be described. For this purpose, first let it be assumed that no selection signal is applied to any of the electrode plates. It is recalled that the inputs of all the flipflops are normally clamped to the high level. Therefore it is understood that the input condition of the AND gate A is met and an output thereof is in a high level as well. A touch ofa human body such as a finger to the electrode plate PI, for example, causes an AC signal to be applied to the plate Pl as an effect of electrostatic induction through the human body from a commercial power supply. Since the input of the flip-flop has been normally clamped to the high level, as mentioned previously, application of the AC signal to the input of the plate P1 is equivalent to application of a low level signal thereto or a logic zero signal thereto. Thus, a touch to the electrode plate by means of a finger can be considered as an individual application of a selection signal of a low level or a logic zero to the desired channel. The resistors R1, R2, R3, Rn and the capacitors connected therefrom to the ground GND form an integration circuit for preventing an undesired chattering effect, which occurs at the time of touching of the human body to the plates P1, P2, P3, Pn, respectively. Application of the selection signal of the low level to the plate P1 brings the output of the AND gate A from the high level to the low level. The low level signal obtained at the output of the gate A as'a function of application of said individual selection signal is applied to the clock generator CL as an input thereto. As to be more fully described subsequently, the clock generator CL generates in a normal condition the second clock signal 2 and only in response to the application of the low level signal to the input generates the first clock signal d 1 of relatively narrow pulse width in lieu of the second clock pulse 4J2. The individual selection signal applied to the input of the flip-flop F1 is written into the first stage thereof as a function of the first clock (bl generated in response to the application of the said selection signal to the channel CH1. The said first clock (#1 is also applied to the first stage of other flip-flops F2, F3, Fn. However, the inputs of these flip-flops have been kept in the high level, as mentioned previously. Therefore, the high level, which is equivalent to no selection signal, is written into the first stage of these flipflops as a function of the said first clock 4J1. Subsequent to the first clock (1J7, the second clock 4:2 is generated at the generator CL and continues until application of the next individual selection signal. The selection signal of the low level stored and inverted in the first stage of the flip-flop F1, and the high level signal, equivalent to no selection signal, stored and inverted in the first stage of the flip-flops F2, F3, Fn are shifted to the second stages of the flip-flops F1, F2, F3, Fn, respectively, as a function of the said second clock (12, and stored and inverted again therein. Thus the selection signal is obtained as in the low level from the second stage of the flip-flop F1 as a function of the second clock (112. The output of the flip-flop F1 is inverted by the inverter I1 and the output selection signal of the high level is taken out from the output terminal 01. On the contrary, the outputs of the flip-flops F2, F3, Fn are inverted by the inverters I2, I3, In, respectively, and the low level signals are taken out from the

output terminal

02, 03, 0n. Likewise, if any other electrode plate, say P3, is touched, the output selection signal of the high level will be obtained from the corresonding output terminal 03, while the low level signals are obtained at any output terminals other than the terminal 03. Thus in accordance with the basic feature of the present invention, if an individual selection signal is applied to an input of any one of a plurality of channels, through a touch by a human finger, for example, such signal is written and stored only in the corresponding channels and taken out from the output thereof, while in the remaining channels a signal equivalent to no selection signal is stored and taken out. Such write-in and read-out of the selection signal and non-selection signal are performed as a function of the clock pulses generated in response to the application of the selection signal.

Referring to FIG. 2, there is shown a schematic diagram of an exemplary static delay type flip-flop implemented with P channel enhancement MOS transistors for use in the system shown in FIG. 1. The flip-flop shown comprises the first stage STl and the second stage ST2. It is readily seen that both stages comprise substantially the same circuit configuration. Therefore, a detailed description will be made of the circuit configuration of only the first stage STl using reference characters of 'I" followed by a subscript of tens numeral for identifying the MOS transistors. In the second stage the reference characters of T" combined with a subscript of the corresponding twenties numerals for identifying the corresponding MOS transistors have been used. Thus a detailed description of the second stage configuration is not considered necessary.

By particularly referring to the first stage STl of the flip-flop shown in FIG. 2, transistors T10 and T17 are used as a switching device, transistors T11, T12, T14, T15 and T18 are used as a store element, and transistors T13, T16 and T19 are used as a load of parallelpaired transistors T11 and T12, parallel-paired transis tors T14 and T15, and transistor T18, respectively, The connection of the MOS transistors in the abovementioned manner is well known to those skilled in the art. Thus it is readily seen that the transistors T11, T12, T14, T15 and T18 serve as an inverter by the aid of the transistors T13, T16 and T19, respectively.

For the purpose of description of the operation of the FIG. 2 circuit, it is assumed that first a low level signal is applied to an input terminal IN and then a low level clock (bl of a relatively narrow pulse width is applied to an input terminal (#1. The transistor T10 is turned on in response to the clock (#1 and the input signal IN of the low level is applied via transistor T10 to the gate of the transistor T11 so that the said input signal is stored therein. The inverted output thereof is provided at the drain electrode of the transistor T11 and is applied to the gate of the transistor T14. On the other hand, the transistor T17 is also turned on in response to the clock qbl and the inverted output of the high level, which is inverted by the transistor T18, is applied via the transistor T17 to the gate of the transistor T15 so that the said inverted signal is stored therein. The inverted output thereof in the low level is provided at the drain electrode of the transistor T15 and is applied to the gate of the transistor T12. As well known, the low level charge at the gate of the transistor T1 1 tends to discharge after the application of the clock dfl. However, the transistor T11 is shunted by the transistor T12 whose gate is connected to the drain of the parallel-paired transistors T14 and T15. As mentioned previously, the gate of the transistor T14 is also connected to the opposite parallel-paired transistors T11 and T12. Such cross connection of two sets of parallel-paired transistors serves to self-hold the written-in signal therein in a well known manner.

After the end of the first clock dil, the second clock qb2 of the low level is applied to the input terminal 2. Thus during the second clock (#2, the inverted output of the transistors T11 and T12 is applied via the transistor T20 to the transistor T21 and the output of the transistors T14 and T15 is applied via the transistor T27 to the gate of the transistor T25. Such signals from the first stage STl is self-held in the cross connection of two sets of parallel-paired transistors in the second stage ST2 in the similar manner. It is understood that since the input signal IN is assumed to be the low level, the input signal is inverted by the transistor T18 and again inverted by the transistor T15 to provide a signal of original low level at the output electrode thereof.

, The said signal of original low level is inverted by the transistor T25 and again by the'transistor T28 to provide the outputsignal of the original level at the output terminal OUT. Such output signal can be obtained during the second clock (1)2.

In the foregoing description it was assumed that the input signal applied to the input terminal was in the low level. It is readily understood that if an input signal of the high level had been applied to the flip-flop, the relation of the levels involved in the respective set of parallel-paired transistors would have been reversed and the output signal obtainable at the output terminal OUT would have been in the high level.

Now referring to, FIG. 3, another embodiment of the input circuit of the system is illustrated. In the embodiment shown the electrode plate for a touch by a human finger is comprised of two segments PL1 and PL2 slightly spaced apart from each other. The segment PL1 is connected through a resistor R to the input of the flip-flop clamped to the high level or the ground potential, whereas the segment PL2 is connected through a resistor to a low level source or a minus voltage source V. It is understood that a touch by a human finger to the segments PL1 and PL2 at the same time makes a circuit therebetween by resistance through the portion of the human finger touching the plates P1 and P2 simultaneously and thus spanning the gap between the plates P1 and P2, with the result that the low level signal is applied to the input of the flip-flop. Geometry of the segments PLl and PL2 should be so selected that an attempt to touch by a human finger tends to cause a simultaneous touch to both segments and make a circuit therebetween.

Referring to FIG. 4, there is illustrated a block diagram of the clock generator CL shown in FIG. 1. The clock generator CL comprises a first monostable circuit M1 connected to the AND gate A (see FIG. 1) and a second monostable circuit M2, these being connected in series in the order as mentioned above. The first monostable circuit M1 comprises a first differentiation circuit DFl and a first inverter Ill and the second monostable circuit M2 comprises a second differentiation circuit DF2 and a second inverter I12. The differentiation circuit DF2 is clamped to a minus voltage source VD.

The operation of the clock generator CL will be better understood by reference to FIG. 5, which illustrates the waveforms at various portions in the circuit shown in FIG. 4. As fully described in conjunction with FIG.

' l, the output of the AND gate A is brought from the high level to the low level during application of the selection signal to any one of the channels in the system shown in FIG. 1. Such variation of the output of the gate A caused by application of the selection signal is illustrated in FIG. 5(a). The output as shown in FIG. 5(a) is applied to the differentiation circuit DFl to pro vide a differentiation output as shown in FIG. 5(b). It is pointed out that the time constant of the circuit DFl is selected to be relatively larger as compared with that of the circuit DF2. The output shown in FIG. 5(b) is applied to the inverter I11, which is implemented with a- P-channel enhancement field effect transistors in a well known manner. Therefore, such inverter Ill provides an inverted output, as shown in FIG. 5(a), during a time period in which the differentiated output shown in FIG. 5(b) is lower than the threshold voltage TI-I of the field effect device. It is seen that the output from the inverter Ill shown in FIG. 5(0) is normally in the low level, while it is in the high level during a predetermined period of time immediately after the low level output is obtained from the gate A and thus immediately after the selection signal is applied to any one of the channels in the system shown in FIG. 1. The output from the inverter 111 is taken out as second clock (#2.

The output of the inverter Ill is applied to the second differentiation circuit DF2. The time constant of the differentiation circuit DF2 has been selected to be relatively smaller, as described previously. Therefore, a positive going pulse and a negative going pulse, as shown in FIG. 5 (d), are generated corresponding to the rising edge and the falling edge of the output pulse shown in FIG. 5(a). It will be understood that the rising edge of the pulse-like configuration shown in FIG. 5(0) is in fact the trailing edge of the $2 clock pulse of a prelow level, as shown in FIG. 5(a), which is of narrow pulse width and occurs immediately after the application of the selection signal to the input of any one of the channels in the system shown in FIG. 1. The output of the inverter I12 is taken out as the first clock (bl. These clocks (b1 and Q52 are applied to the clock terminals l and (b2, respectively, of the flip-flop shown in FIG. 2. The operation of the flip-flop in response to the clocks (b1 and (#2 has already been described.

It should be pointed out that in accordance with the FIG. 4 embodiment, the fall portion of the output from the AND gate A is usually delayed as compared with the input to the flip-flop due to a switching delay time which occurs at the AND gate A while the signal is transferred therethrough and the output from the differentiation circuit DFl is delayed similarly as compared with the output from the AND gate A. As a result, the rise portion of the output from the monostable circuit M1 is delayed as compared with the input to the flip-flop. It is understood that the said rise portion of the output from the monostable circuit M1 corresponds to the end of the second clock pulse 422 of the preceding cycle. In a similar manner, the first clock pulse 4)! from the monostable circuit M2 is also delayed as compared with the rise portion or the end of the second clock (1)2. As a result, after the lapse of the said slight delay time since the application of the input to the flip-flop, the second clock Q52 of the preceding cycle ends, and the similar delay time after the end of the second clock (#2 of the preceding cycle the first clock (1)1 is provided. This assures that the write-in of the signal into the flip-flop is performed after the transient state at the time of application of the said input has been stabilized and as well the read-out of the signal from the flip-flop is performed after the lapse of the said predetermined time period since the said first clock (bl, at which time the transient state at the time of write-in has been stabilized.

It is seen that the second clock pulse (#2 generated by the FIG. 4 embodiment is of pulse width starting the said predetermined time period after the first clock pulse (1)1 and ending soon after application of the input of the following cycle to the flip-flop. Alternatively, however, the second clock (b2 having narrow pulse width can be equally used for the purpose of operating the flip-flop shown in FIG. 2. Such second clock can be generated by simply delaying the first clock (#1 by means of a suitable delay device, for example.

For the purpose of illustrating an example of the flipflop for use in the embodiment of the present invention, Z-phase 2-stage static delay flip-flop implemented with the field effect transistors has been described with reference to FIG. 2. However, this should not be construed by way of limitation. Various types of flip-flop, such as Z-phase quasi static delay flip-flop, edge trigger delay flip-flop or the like, can be employed for the same purpose. Thg Z-phase quasi static delay flip-flop can be operated with the same type clock pulse as that used in FIG. 2 embodiment. For the purpose of operating the edge trigger delay flip-flop, a delayed output of the AND gate A may conveniently be used. It is understood that the delay time period of the said delay output of one logical state serves as the first clock and the remaining portion of the said delay output of the other logical state serves as the second clock. It is to be further pointed out that the flip-flop of the abovementioned type may be implemented with bipolar devices I 9 and othertypes of flip-flop, such as J-K type,-R-S type and the like may equally be used for the same purpose.

A switch control system of another embodiment of the present invention is illustrated in FIG. 6 in a block form. The switch control system shown is capable of being controlled with a common selection signal applied to a common input terminal as well as the individual selection signals to be applied individually to the respective individual input terminals. For this purpose the channels CH1, CH2, CH3, CHn each comprise OR gates G1, 0G2, 063, OGn, respectively, each having two inputs. One input of each gate is connected to the output of the flip-flop of the adjacent channel denoted by the reference character of one less number subscript and only in case of the gate OGl, one input thereof is connected to the output of the flip-flop Fn which is denoted by the reference character of a maximum number subscript. The other input of each gate is connected commonly to a common selection signal source CS, which provides a common selection signal in response to application of a remote control signal applied to remote control terminal RT in a remote control manner, for example.

The channels CH1, CH2, CH3,.. CHn eachalso comprise AND gates AGl, AG2, AG3, AGn, connected between the individual input terminals P1, P2, P3, Pn and the flip-flops F1, F2, F3, Fn, respectively, and one input of each gate is connected to the output of the corresponding one of the OR gates OGl 0G2, 0G3, OGn, respectively.

Only the channel CHI further comprises an AND gate AGll connected between the gate A61 and the flip-flop F1 and one input of the gate AGll is connected to a return control signal source-RC, which will be fully described subsequently with reference to FIGS. 7 and 8, while the other input is connected to the output of the gate A GLThe circuitry of any other portions in FIG. 6 is the same as that of FIG. 1 except that the clamp circuit at the input of each flip-flop has been omitted for simplicity of illustration and therefore a further detailed description of the circuitry will be omitted. First let it beassumec'l that the output of the common selection signal source CS and the output of the return controlsignal source RC are normally in the high level. In such event one input of each of the gates AGl, AG2, A63, AGn and AGll is in the high level and the input level of the flip-flops F1, F2, F3, Fn depends upon the individual selection signal applied to the respective input terminals P1, P2, P3, Pn. In other words, the system shown in FIG. 6 is operable in response to the individual selection signal applied to the respective input terminals in exactly the same manner as described in connection with the system shown in FIG. 1. 7

Now operation of the system shown in response to the common selection signal will be described. For this purpose let it be assumed that only one of the flip-flops F1, F2, F3, Fn, say only the flip-flop F1, stores a written-insignal so that the output of the low level is provided therefrom. As briefly described, the common selection signal source CS generates the common selection signal of the low level and of relatively narrow pulse width in response to a remote control signal applied to the remote control terminal RT. The said common selection signal is applied to the gate 0G1, .062,

0G3, OGn. However, since the output of the flipflops F2, F3, Fn is in the high level, while only the output of the flip-flop F1 is in the low level, only the OR gate 0G2 provides the low level outputin response to the low level common selection signal. The low level output from the OR gate 0G2 brings the output of the AND gate AG2 from the high level to the low level. The low level output from the gate AG2 can-be considered as the same as application of the individual selection signal to the channel CH2. Thus the low level output from the gate AG2 is written into the first stage of the flip-flop F2 as a function of the first clock 4J1 generated in the clock generator CL in response to the said low level output from the gate AG2 and is shifted to the second stage of the flip-flop as a function of the second clock (#2 likewise generated in response to the low level output from the gate AG2. As a result the signal written and stored in the flip-flop F1 is shifted to the adjacent flip-flop F2 in response to the application of the common selection signal and thus of the remote control signalappliedto the common remote control terminal RT. Thus it is readily seen that the signal stored in any one of the flip-flops F1, F2, F3,. Fn is shifted in a cyclic manner in response to the common signal to be applied in a sequential order. Such common signal is obtained by means of the common selection signal source CS in response to a manually generated remote control signal, for example, to be applied tothe terminal RT. Such remote control signal may be transmitted to the terminal RT via any suitable transmission path.

. Thus in accordance with the embodiment of the switch control system shown in FIG. 6, any one of a plurality of the channels or circuits is selectively brought in an active state upon application of either an individual selection signal to the input of the corresponding channel or a remote control signal ora common selection signal to the common input terminal.

In the foregoing description, it was assumed that at an initial condition only one of the flip-flops F1, F2, F3, Fn stored the written signal or was in an active state. It is important that in operation of the system in response to the common selection signal only one of the flip-flops is in an active state at any time. Nevertheless, at the time of turning on the power circuitry of the system how many and which flip-flopswill be brought in an active state are not determined. Thus it is necessary to provide a return control circuit for forcibly returning the system to a desired initial condition in which only a predetermined one of the flip-flops is brought in an active state in response to the turning on of. the power source of the system.

FIG. 7 shows a block diagram of a preferred embodiment of the return control circuit for use in the system shown in FIG. 6. The return control circuit RC comprises a delay circuit DL, an inverter IVl, amonostable circuit MS and the gate AG 1 1. It is well known that the potential appearing at the minus voltage source VD shows a gradual change as shown in FIG. 8(a) at the time of turning on the power source of the system. Such gradual change in voltage at the source VD is delayed by means of the delay circuit DL comprising a resistor and a capacitor connected in series to provide the more gradually changing output therefrom, as shown in FIG. 8(b). After the power circuitry is turned on and during a period of time when the output shown in FIG. 8(b) is more positive than the threshold voltage TH of the field effect transistor forming the inverter N1, the

transistor is in non-conduction and the output shown in FIG. 8(c) is obtained therefrom. From FIG. 8(a), it is seen that the output from the inverter IVl shows the low level or the logic zero for a relatively short period immediately after the turning on of the power circuitry of the system. The output from the inverter [V1 is applied to the monostable circuit MS and is differentiated by a differentiation circuit DIF included therein to provide an output shown in FIG. 8(d) to the input of the inverter 1V2 included in the monostable circuit MS. Since the input of the inverter [V2 is clamped to the minus voltage source -VD, only the positive going pulse of the output shown in FIG. 8(a') is inverted by the inverter lV2 to provide an output shown in FIG. 8(2) to one input of the AND gate AGl 1, the other input of which is connected to the input terminal P1 of the individual selection signal of the channel CI-Il, as described previously. It is readily understood that the output of the low level and of narrow pulse width applied to the AND gate AGll brings the output thereof from the high level to the low level accordingly. Such low level signal is written into the first stage of the flipflop Fl as a function of the first clock qbl generated in response to the said low level signal and is shifted to the second stage of the flip-flop Fl as a function of the second closk (#2 also generated in response to the-said low level signal. Thus it is seen that the return control circuit forcibly returns the system to a desired initial condition in which only predetermined one, the flip-flop F1 in the illustrated embodiment, of the flip-flops is brought in an active state in response to the turning on of the power source of the system. Intuitively, it might be considered to utilize the output shown in FIG. 8(0) as an input to the AND gate AGI! for the abovementioned purpose. However, such utilization of the output shown in FIG. 8(0) is not preferred, because the whole system shown is in a transient condition immediately after the turning-on of the power circuitry of the system. Thus utilization of the output shown in FIG. 8(e) is much more preferred for an assured return control of the system.

Referring to FIG. 9, there is illustrated a switch control system of a further embodiment of the present invention. The embodiment shown comprises an improvement in the common selection signal applied to the common input terminal of the FIG. 6 embodiment.

It is recalled that in the FIG. 6 embodiment a single pulse is applied as a common selection signal for the purpose of shifting an active state in one flip-flop to the next adjacent flip-flop. Thus such a signal should be applied repeatedly until the condition of an active state in one flip-flop is attained in the flip-flop of the desired channel. By contrast, the embodiment shown in FIG. 9 utilizes a chain of pulses as a common selection signal, the number of which chain pulses is determined in a pulse chain generator as to be more fully described subsequently upon individual selection corresponding to the respective channel. Application of such chain of pulses forcibly returns the system to a predetermined initial condition and also shifts the active state in the flip-flops in predetermined relation with the number of pulses included in the said pulse chain. In order to forcibly return the system upon application of a chain of pulses to the remote control terminal RT, a pulse separation circuit PS is provided in the FIG. 9 embodiment, which comprises an output terminal for providing a forcibly returning signal to the AND gate AGll. The

pulse separation circuit PS generates such a forcibly returning signal and a desired corresponding plurality of shift pulses for a shift operation the flip-flops upon application of the said chain of pulses thereto. For example, for the purpose of selecting the ninth flip-flop F9 (not shown) a chain of pulses, the number of which pulses is ten, is generated in the pulse chain generator to be described subsequently. The first two pulses of thus generated chain of pulses are used to generate the forcibly returning signal in the pulse separation circuit PS and the remaining eight pulses are taken out from the circuit PS to be applied tothe flip-flops for eightshift operation so that the ninth flip-flop F9 is in an active state ultimately.

A block diagram of the pulse separation circuit PS is illustrated in FIG. 10 in a block form. The pulse separation circuit PS comprises a pulse chain detection circuit PCD, a monostable circuit MS and a logic circuit LG. The pulse chain detection circuit PCD generates in response to a chain of pulses applied to the terminal RT a pulse having a pulse width substantially corresponding to a period of the said pulse chain. The monostable circuit MS generates in response to the output from the pulse chain detection circuit PCD a pulse having a predetermined pulse width, which covers the first two pulses of the said pulse chain in the abovementioned example. The logic circuit LG selects the first predetermined number of pulses (the first two pulse out of the said chain of pulses in case of the abovementioned example) as a function of the output from the monostable circuit MS, which first group of pulses are taken out from a return pulse terminal RTP as a forcibly returning signal. The logic circuit LG also selects the remaining pulses out of the said chain of pulses as a function of the output from the monostable circuit M5, which latter group of pulses are taken out from a shift pulse terminal SHP as a shift pulse for shift operation in the flip-flops.

FIG. 11 illustrates a schematic diagram of a preferred embodiment of the pulse separation circuit shown in FIG. 10. The pulse chain detection circuit PCD comprises a diode D20, a storage circuit DL21 comprising a resistor and a capacitor connected in parallel and an inverterv IV22 comprising a typical P-channel enhancement MOS transistor. The monostable circuit MS comprises a differentiation circuit DF23 comprising a capacitor and a resistor and an inverter IV24 comprising a typical P-channel enhancement MOS transistor. The logic circuit LG comprises a pair of OR gates OG26 and 0627. One input of the gates OG26 and 0627 is connected to the remote control terminal RT. The other input of the gate OG27 is connected via the inverter IV25 to the output of the inverter IV24 and the other input of the gate OG26 is connected directly to the output of the inverter lV24. The output of the gate OG26 is connected to the return control pulse terminal RTP and the output of the gate OG27 is connected to the shift pulse terminal SI-IP.

The operation of the FIG. 11 embodiment will be described in detail with reference to FIG. 12, which shows waveforms at various portions of the FIG. 11 circuit. A chain of pulses shown in FIG. 12(a) is generated in a pulse chain generator as to be more fully described subsequently and is applied to the terminal RT. The number of the said chain of pulses is determined as desired upon individual selection corresponding to the respective channels. The chain of pulses is further applied to the storage circuit DL21 via the diode D20. Since the diode D20 is inserted in a reverse direction, the capacitor included in the circuit DL21 remains substantially time period of the said chain of pulses the input to the inverter IV22 is less than the threshold thereof and inverted by the inverter to provide at the output thereof a waveform shown in FIG. 12(b). The waveform shown in FIG. 12(b) is differentiated by the differentiation circuit DF23 to provide a waveform shown in FIG. 12(0) to the input of the inverter IV24. Since the input of the inverter [V24 has been normally clamped to a minus voltage source VD, the output of the inverter is normally in a high level and only when the output from the differentiation circuit DF23 is more positive than the threshold TH of the MOS transistor used as the inverter IV24, the output of the inverter is in the low level. A waveform of v the output from the inverter IV24 is shown in FIG. 12(a'). It is pointed out that the time constant of the differentiation circuit DF23 has been so chosen that the period of the low level in the output from the inverter IV24 covers the first two pulses of the said chain of pulses. As a result the OR-gate OG27 masks the first two pulses and only theremaining eight pulses as shown in FIG. 12(2) are obtained at the output thereof as a logical sum of the chain of pulses shown in FIG. 12(a) and an inversion of the waveform shown in FIG. 12(d) as inverted by the inverter IV25. On the other hand the OR gate OG26 provides a logical sum of the chain of pulses shown in FIG. 12(a) and the output from the inverter IV24 shown in FIG. 12(d). Thus only the first two pulses of the chain of pulses, as shown in FIG. 120), are obtained from the gate OG26, while the remaining eight pulses are masked.

As already described, upon application of the chain of pulses to the remote control terminal RT, the pulse separation circuit PS selects the first two pulses of the pulse chain and applies them to the AND gate AGll in the system shown in FIG. 9. As a result only the flipflop F1 is brought in an active state as mentioned previously. Then the remaining eight pulses are applied to the respective OR gates G1, 0G2, 0G3, OGn of the system shown in FIG. 9 and the active state in the flip-flops is shifted as a function of the said eight pulses. Ultimately the active state comes to be in the ninth flipflop F9 (not shown). In the foregoing description it was assumed that the chain of pulses comprises ten pulses. The number of the pulses in the pulse chain is, however, determined, as desired, for selection of any desired flip-flop and thus of any desired channel, as to be more fully described subsequently.

FIG. 13 illustrates in a block form an example of the circumstance wherein the switch control system shown in FIG. 9 can be advantageously employed. More specifically, FIG. 13 shows a block diagram of a television channel selection system of a remote control type employing the present invention. The system shown in FIG. 13 comprises a transmitter TR for generating a chain of pulses, the number of which chain pulses are determined-as desired upon manual selection of the respective channels, and transmitting the chain of pulses along a transmission path TP, and a receiver RV for receiving the said transmitted chain of pulses and for bringing the corresponding channel or circuit in an active state. The transmitter TR comprises a pulse chain generator PCG for generating a chain of pulses upon manual selection of the

respective inputs

1, 2, 3, n, the number of which chain pulses is determined as as sociated with the

inputs

1, 2, 3, n, and a transmitting station TS for transmitting the chain of pulses via the transmission path TP, which may advantageously be an ultrasonic, optic or electromagnetic medium. The receiver RV comprises-a receiving station RS for receiving the chain of pulses, as transmitted along the transmission path TP and a switch control system SCS in accordance with the present invention for providing the individual output corresponding to the manually selected channel in response to the received chain of pulses. The switch control system SCS was described in detail with reference to FIG. 9. The active state output from the switch control system SCS is used to energize the corresponding television broadcast channel. The television channel selection system operable in response to the individual active state output is well known to those skilled in the art. However, it should be pointed out that such individual active state output can be used in many other applications. Therefore, an exemplary application of the present invention to the television channel selection system, as mentioned above, shouldnot be construed by way of limitation.

A preferred embodiment of the pulse chain generator PCG shown in FIG. 13 is illustrated in FIG. 14 in a rather detailed block form. Ten

input terminals

1, 2, 3, 10 for manual individual selection are provided. Such input terminals may be of the same structure as shown in FIG. .3. The number of 10 is sufficient for the purpose of television channel selection, because l2 channels are assigned in the current VHF television system and nevertheless the adjacent channels are not used in a particular area for avoiding the so-called adjacent channel interference. The 10 inputs are encoded by an encoder EC so that the 10 inputs may be identitied by four-bit outputs in accordance with a binary system, for example, and the said four-bit outputs are applied to flipflops FF 1, FF2, FF3 and FF4 to store the said four-bitoutputs therein. The said four-bit outputs are applied via'an OR gate OG31 to a single shot multivibrator S531, which generates a pulse of 20 micro second pulse width. The output from the multivibrator S531 is applied to the flip-flops FFl, F F2, FF3 and FF4 and also to flipflops FF31, FF32, FF33 and FF34 to reset them. Since the said four-bit outputs have been applied to the flip-flops FFl, FF2, FF3 and FF4, the four-bit outputs are stored therein after the end of the output pulse from the single shot multivibrator S831. It is pointed out that usually the manual individual selection of the

input terminals

1, 2, 3, 10 will last for at least one second and thus the said four-bit outputs will be obtained from the encoder EC for the same period of time, whereas the output pulse from the multivibrator $531 will last only for 20 micro second.

The output from the multivibrator S831 is applied to a flip-flop F F21 to set it. The set output from the flipflop FF21 is applied to a pulse generator PG and enables it. The output pulse from the pulse generator PG is applied to one input of an AND gate AG31. The other input of the gate AG31 is from the output of OR gate OG32. The inputs of the OR gate OG32 are from the outputs of coincidence gates C01, C02, C03 and CO4. One input of the gate C01, C02, C03 and CO4 is connected to the output of the corresponding flipflops FF 1, FFZ, FF3 and FF4, respectively, and the other input of the gates C01, C02, C03 and CO4 is connected to the output of flip-flops FF31, FF32, FF33 and FF34, respectively. Since the four-bit outputs have been stored in the flip-flops FFl, FFZ, FF3 and FF4 whereas the flip-flops FF31, F1 32, FF33 and FF34 have been reset, inverted outputs of the logic one are provided from the coincidence gate C01, C02, C03 and CO4, which are applied via the OR gate OG32 to the AND gate AG31. Thus the output pulse from the pulse generator is applied to the flip-flop FF31 and is also taken out as an output of the pulse chain generator PCG. it is pointed out that the flip-flops FF31, FF32, FF33 and FF34 are connected in series to implement a binary counter BC. The pulse generator PG continues to generate the output pulse and the count in the binary counter BC advances. Just when the count in the binary counter BC reaches the same state as the four-bit output from the flip-flops FF 1, FFZ, FF3 and FF4, the inverted output from all the coincidence gates CO1,

. C02, C03 and CO4 is the logic zero and the output pulse from the pulse generator PG is inhibited from being applied via the AND gate AG31 to the binary counter BC and also from being taken out as an output. At the same time the logic zero output from the OR gate 32 is applied via an inverter [V31 to a single shot multivibrator S532 and an output pulse having micro second therefrom is applied to the reset terminal of the flip-flop FF21 to reset it and thus to disable the pulse generator PG. As a result'a chain of pulses is generated in response to the manual individual selection of the input terminals and the number of the pulses included in the chain of pulses is determined in accordance with the selected input terminal.

While specific preferred embodiments of the present invention have been described, it will be apparent that obvious variations and modifications of the invention will occur to those of ordinary skill in the art from a consideration of the foregoing description. It is, therefore, desired that the present invention be limited only by the appended claims.

What is claimed is:

1. A switch control system comprising:

a plurality of individual input means for providing respectively corresponding individual selection signals,

a corresponding plurality of storing means connected to the respectively corresponding input means for receiving as input signals thereto and, as a function of a clock pulse, storing the individual selection signals provided by the respectively corresponding input means, and

clock pulse generating means for generating said clock pulse for supply to said pluralityof storing means in response to an individual selection signal being provided by any of the input means.

2. A switch control system in accordance with claim 1, wherein:

each of said storing means comprises first and second stages,

said clock generating means generates a first clock pulse of a first phase and a second clock pulse of a second phase, and

each of said storing means writes the input signal into the first stage thereof in response to the first clock pulse and shifts the written signal from the first stage to the second stage in response to the second clock pulse.

3. A switch control system in accordance with claim 1, in which said clock pulse generating means comprises:

a logical gate connected to said input means and responsive to an individual selection signal provided by any of said input means for producing an output; and

a clock pulse generator for generating a clock pulse in response to the output of said logical gate.

4. A switch control system in accordance with claim 1, in which each of said storing means is a flip-flop.

5. A switch control system in accordance with claim 4, in which said flip-flop is a delay flip-flop.

6; A switch control system comprising:

a corresponding plurality of storing means connected to the respectively corresponding input means, for receiving as input signals thereto and, as a function of a clock pulse, storing the individual selection signals provided by the respectively corresponding input means,

means applying said clock pulse to said plurality of storing means,

logical connection means connecting said plurality of storing means for implementing a ring counter connection of said storing means, and

a common input means for receiving a common selection signal for shifting a signal storing state from a given to a successive one of said storing means in said ring counter connection.

7. A switch control system in accordance with claim 6, in which each of said storing means stores an input signal received thereby as a function of a clock pulse applied thereto, and which further comprises clock pulse generating means for generating a clock pulse in response to a selection signal being received as an input signal by any of said storing means.

8. A switch control system in accordance with claim 7, in which each of said storing means comprises first and second stages, said clock pulse generating means generates a first clock of a first phase and a second clock of a second phase, and each of said storing means writes the input signal into the first stage thereof in response to the first clock pulse and shifts the written signal from the first stage to the second stage in response to the second clock pulse. 4

9. A switch control system in accordance with claim 7, in which said clock pulse generating means comprises a logical gate responsive to an input signal received by any of said storing means for producing an output; and

10. A switch control system in accordance with claim 7, in which each of said storing means is a flip-flop.

11. A switch control system in accordance with claim 10, in which said flip-flop is a delay flip-flop.

12. A switch control system in accordance with claim 6, which further comprises a return control means for forcibly returning the system to an initial condition in which only one of the storing means is in a signal storing state.

13. A switch control system in accordance with claim 12, in which said return control means is operable in response to energization of the system.

14. A switch'control system in accordance with claim 6, for use in a television channel selection system wherein said plural storing means correspond to channels available for selection, and wherein said channel selection system is operable to effect channel selection in response to the signal storing state of a storing means of said ring counter connection.

15. A switch control system in accordance with claim 6, which further comprises a pulse chain generator for generating a chain of pulses as said common selection signal received by said common input means, whereby a signal storing state in the storing means of the ring counter connection is shifted as a function of said chain of pulses in predetermined relation with the number of pulses in said pulse chain.

16. A switch control system in accordance with claim 15, which further comprises a return control system for forcibly returning the system to an initial condition in which a single predetermined storing means of said ring counter connection is in a signal storing state, in response to said chain of pulses being applied to the common input means, whereby a signal storing state in the storing means of the ring counter connection is shifted as a function of said chain of pulses starting from the predetermined storing means in said initial condition, in predetermined relation with the number of pulses in said pulse chain.

17. A switch control system in accordance with claim 16, in which said return control system comprises a pulse separation means for dividing said chain of pulses into a first portion of the chain corresponding to a predetermined number of the pulses and a second portion comprising the remaining pulses of the chain, and said return control system is operable in response to said first portion of the chain for forcibly returning the system to the initial condition while the second portion comprising the remaining pulses of the chain are supplied to the common input means for shifting the signal storing state of the storing means of the ring counter connection.

18. A switch control system in accordance with claim 16, in which said pulse chain generator comprises a plurality of individual input means for manual selection and means for generating a chain of pulses in response to selection of any one of said individual input means, the number of which pulses corresponds to a selected input means.

19. A switch control system in accordance with claim 18, which further comprises means establishing a transmission path from a remote position for transmitting said chain of pulses therethrough to said common input means.

20. A switch control system in accordance with claim 15, for use in a television channel selection system wherein said plural storing means correspond to channels available for selection, and wherein said channel selection system is operable to effect channel selection in response to the signal storing state of a storing means of said ring counter connection.

Claims

1. A switch control system comprising: a plurality of individual input means for providing respectively corresponding individual selection signals, a corresponding plurality of storing means connected to the respectively corresponding input means for receiving as input signals thereto and, as a function of a clock pulse, storing the individual selection signals provided by the respectively corresponding input means, and clock pulse generating means for generating said clock pulse for supply to said plurality of storing means in response to an individual selection signal being provided by any of the input means.

2. A switch control system in accordance with claim 1, wherein: each of said storing means comprises first and second stages, said clock generating means generates a first clock pulse of a first phase and a second clock pulse of a second phase, and each of said storing means writes the input signal into the first stage thereof in response to the first clock pulse and shifts the written signal from the first stage to the second stage in responSe to the second clock pulse.

3. A switch control system in accordance with claim 1, in which said clock pulse generating means comprises: a logical gate connected to said input means and responsive to an individual selection signal provided by any of said input means for producing an output; and a clock pulse generator for generating a clock pulse in response to the output of said logical gate.

6. A switch control system comprising: a plurality of individual input means for providing respectively corresponding individual selection signals, a corresponding plurality of storing means connected to the respectively corresponding input means, for receiving as input signals thereto and, as a function of a clock pulse, storing the individual selection signals provided by the respectively corresponding input means, means applying said clock pulse to said plurality of storing means, logical connection means connecting said plurality of storing means for implementing a ring counter connection of said storing means, and a common input means for receiving a common selection signal for shifting a signal storing state from a given to a successive one of said storing means in said ring counter connection.

8. A switch control system in accordance with claim 7, in which each of said storing means comprises first and second stages, said clock pulse generating means generates a first clock of a first phase and a second clock of a second phase, and each of said storing means writes the input signal into the first stage thereof in response to the first clock pulse and shifts the written signal from the first stage to the second stage in response to the second clock pulse.

9. A switch control system in accordance with claim 7, in which said clock pulse generating means comprises a logical gate responsive to an input signal received by any of said storing means for producing an output; and a clock pulse generator for generating a clock pulse in response to the output of said logical gate.

14. A switch control system in accordance with claim 6, for use in a television channel selection system wherein said plural storing means correspond to channels available for selection, and wherein said channel selection system is operable to effect channel selection in response to the signal storing state of a storing means of said ring counter connection.