US3801807A

US3801807A - Improved shift register having (n/2 - 1) stages for digitally synthesizing an n-phase sinusoidal waveform

Info

Publication number: US3801807A
Application number: US00301430A
Authority: US
Inventors: J Condon
Original assignee: Bell Telephone Laboratories Inc
Current assignee: AT&T Corp
Priority date: 1972-10-27
Filing date: 1972-10-27
Publication date: 1974-04-02
Anticipated expiration: 1991-04-02

Abstract

A method is disclosed for calculating appropriate output resistor values in the summing circuitry of a transversal filter featuring a shift register configured to digitally synthesize sinusoidal waveforms. Output resistor values calculated according to the method result in an improved circuit by allowing the elimination of the otherwise required last stage of the shift register and a reduction with respect to the prior art in the ratios of the values of the output resistors.

Description

United States Patent 1191 Condon 5] Apr. 2, 1974 [54] IMPROVED SHIFT REGISTER HAVING (N/Z 3,482,190 12/1969 Brenin 333/29 1 STAGES FOR DIGITALLY 3,221,170 7/1970 Leuthold et a1. 328/37 SYNTHESIZING AN N-PHASE SINUSOIDAL 22: 3; WAVEFORM l ORlilGN PATENTS [75] Inventor: Joseph Henry Condon, Summit, NJ.

1,194,899 6/1965 Germany 328/14 [73] Assignee: Bell Telephone Laboratories,

Incorporated, Murray Hill, NJ. OTHEZR PTUBUCATIONS Peckels et al.: Subst1tut1on of a delay line for a whole F1199: 1972 bank of filters, IBM Technical Discl. Bull. Apr. 1966, 21 Appl. No.: 301,430 Pages 1498-1499- Primary ExaminerFelix D. Gruber [52] U.S. Cl 235/197, 235/l50.53, 328/27, Attorney, Agent, phelan 328/37 {51] [1 11. CI G06g 7/28 57 ABSTRACT [58] Field of 'gg A method is disclosed for calculating appropriate out- T 1 put resistor values in the summing circuitry of a transversal filter featuring a shift register configured to dig- [56] References Cited itally synthesize sinusoidal waveforms. Output resistor UNITED STATES PATENTS values calculated according to the method result in an 3,579,117 5/1971 Norris 328/37 improved circuit by allowing the elimination of the 3,623,160 1 H1971 Giles 340/347 DA otherwise required last stage of the shift register and a y reduction with respect to the prior art in the ratios of erreau 3,543,009 11/1970 Voelcker, Jr. 333/29 the values of the output reslstors 3,292,110 12/1966 Becker et a1 333/29 6 Claims, 6 Drawing Figures 20' s' s' s 1 l 2 3 d (t) o 1 271 11 1 a 1| l 1 1 7 F I 1 d 1 I0 I J1 1r 1 I I 50 d e d m; (k)} ,5 I 1 2 3 1 1 .ATENTEDAPR 2mm 4 I 3801.807

SHhEIJ-UFZ N I 20 s s s ("U 5 RIP I L50 T T I l I 2 3 I l Ii A FIG. %R R1? (2 a g? (PRIOR ART) FIG. 2 (PRIOR ART) FIG. 3 (PRIOR ART) PATENTEDAPR 2 I974 SHEEI 2 OF 2 FIG. 6

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IMPROVED SHIFT REGISTER HAVING (N/2 l) STAGES FOR DIGITALLY SYNTHESIZING AN N-PI-IASE SINUSOIDAL WAVEFORM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates, generally, to the art of digitalto-analog waveform conversion circuits and, more specifically, to a method for calculating output resistor values in the summing circuitry of an improved transversal filter which is configured to digitally synthesize sinusoidal waveforms.

2. Prior Art Over the past few years it has become increasingly apparent to circuit designers that, in applications where snall amounts of harmonic distortion can be readily tolerated, sinusoidal waveforms are most economically and dependably generated with digital circuitry. One such application lies in telephone station sets which provide multitone dialing service. In the past, the multifrequency dialing signals utilized in such station sets have been generated with analog circuitry. More recently, however, this analog circuitry has been replaced in experimental station sets with digital circuitry which synthesizes the dialing waveforms by adding together differently shifted and weighted components of digital waveforms having the same frequencies as the dialing waveforms.

This digital circuitry has been advantageously constructed in the general form of a transversal filter which is principally comprised of an N/2 stage serial shift register. The output of each stage of the shift register is equipped with an output resistor connecting to a common summing terminal. A digital waveform of the desired frequency fl, is fed into the signal input of the input stage of the shift register. The digital waveform is then shifted along the register at the frequency Nf The digital waveform appearing at the signal output of each stage of the shift register is continuously summed with the other such waveforms at the summing terminal in a proportion depending upon the value of the output resistor connecting that stage to the summing terminal. As a result, a digital approximation of the desired dialing waveform appears at the summing terminal. N is an even integer of a magnitude which is nominally inversely proportional to the level of harmonic content in the resulting dialing waveform. As N is increased toward infinity the harmonic content of the dialing waveform approaches zero; or, expressed another way, the noise power of the dialing waveform decreases and the power of the fundamental component of the dialing waveform increases as the number of stages, N/2, is increased.

A good measure of the quality or lack of harmonic distortion in the synthesized waveform is the number of differently shifted components, or alternatively, shift register stages, N/2, which contribute to collectively generate the synthesized waveform.

Additional shift register stages are required to achieve a lower harmonic content in the synthesized waveform; a reduction in the number of stages increases the harmonic content of the synthesized waveform.

In prior art circuits of this type, the values of the resistors connecting the outputs of the individual shift register stages to the common summing terminal have been arrived at by empirical design techniques. Unfortunately, however, these empirical design techniques have proved to be unsatisfactory for a number of reasons. One such reason is that they have resulted in large ratios between the values of the respective output resistors. In certain methods for depositing thin film resistors it is desirable that the ratios between the values of the resistors be as close to unity as is possible. Since it is essential that these shift register circuits be suff1- ciently small to be incorporated into telephone station sets, it is desirable that the output resistors be of values which facilitate their fabrication as thin film structures. It would, therefore, be advantageous to discover a method for arriving at output resistor values which results in low ratios between the respective output resistor values.

Commercial implementation of these circuits in multitone station sets would result in the eventual manufacture of literally millions of these shift register circuits. It would, therefore, enable the manufacturers of the station sets to achieve substantial savings by discovering design techniques which would eliminate unnecessary hardware requirements in the shift register circuits. As was pointed out above, however, any reduction in the number of shift register stages or output resistors usually results in a deterioration in the quality of the synthesized waveform.

It is, therefore, an object of this invention to provide a simple, systematic, analytical, technique for designing the aforedescribed shift register circuit with the intent to reduce the hardware requirements of the circuit.

It is a further object of the invention to provide a design teehnique for reducing the hardware requirements of the circuit which will not also result in an increase in the harmonic content of the synthesized waveform.

It is yet another object of the invention to provide a design technique which will facilitate the fabrication of the output resistors in a thin film structure by reducing the ratios of the values of the output resistors.

SUMMARY OF THE INVENTION One aspect of the present invention lies in appropriate values for the output resistors in the summing circuitry of an (N12) stage shift register circuit which is configured to digitally synthesize a sinusoidal waveform. More specifically, it has been discovered that the values of the output resistors are advantageously R, K/(cos(2 1ri/N+ qr/N) cos(2 1r(i-l)/N 1r/N)) where Nis an even integer greater than or equal to six; 1' is an integral index variable corresponding to the shift register stage number to which the particular output resistor having that subscript number is connected, i running from I to (N12) (beginning at the input stage of the shift register); and K is a constant of proportionality.

Output resistor values in accordance with the first aspect of the invention allows the elimination of the last stage of the shift register and its output resistor, resulting in the second aspect of the invention an improved [(N/ 2 )1 ]-stage circuit which is capable of synthesizing the desired sinusoid with substantially the same amount of harmonic distortion as is produced by the prior art, (N/2) stage circuit. An important feature of the invention is that a reduction is achieved with respect to the prior art in the ratios of the largest and smallest output resistors required to synthesize any given sinusoidal waveform.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a schematic diagram of a generalized, prior art, (N/2) stage shift register circuit configured for synthesizing a sinusoidal waveform.

FIG. 2 illustrates a prior art (N/2)-stage shift register circuit, where N=8.

FIG. 3 shows a sinusoidal current waveform s (t) synthesized by the four-stage circuit shown in FIG. 2.

FIG. 4 illustrates an [(N/2 l)-stage ]shift register circuit in accordance with the invention, where N=8.

FIG. 5 depicts the internal voltage waveforms d (t), d (t), and d (t) of the circuit shown in FIG. 4 as it responds to a digital input waveform d(t) to synthesize the current waveform s (t).

FIG. 6 shows an [(N/2 2)]-stage shift register circuit which is achieved in accordance with the invention by eliminating the input stage of the circuit depicted in FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION The prior art (N/2)-stage circuit, shown in generalized schematic form in FIG. 1, is illustrative of the transversal filter circuits which in the past have been utilized to digitally snythesize sinusoidal waveforms. A sinusoidal waveform synthesized by the (N/2)-stage circuit shown in FIG. 1 is conveiently characterized by N distinct phases" of constant amplitude and equal duration per cycle of the resulting synthesized waveform.

A synthesized sinusoid is generated in the circuit shown in FIG. 1 in the following manner. A digital signal d(t), such as a square wave, having the same pulse repetition frequency f as the desired sinusoid is coupled into signal input 10 of input stage 1 of shift register 50. A digital shifting or clocking signal d(t) having a frequency Nf is coupled through lead to shifting inputs S through S of stages 1 through (N/2), respectively, of shift register 50. The differently shifted components of d(t), which appear at the respective output terminals or taps of shift register stages 1 through (N/2), are coupled to a common summing terminal through corresponding ones of output resistors R through R Each such component is summed with the other components at summing terminal 30 in proportion to the conductance of the particular resistor through which the component is coupled to the summing terminal. The summation of the components results in a synthesized sinusoid S(t) being formed at terminal 30.

The four-stage circuit shown in FIG. 2 is a specific example of the generalized circuit shown in FIG. 1. A synthesized current waveform, generated by the fourstage circuit (N=8) shown in FIG. 2, is depicted in FIG. 3. The dashed current waveform shown in FIG. 3 represents the desired waveform and the stepped waveform s (t) represents the synthesized approximation of the desired waveform. V represents the magnitude of voltage waveforms appearing at the signal outputs of shift register stages 1 thorugh 4, respectively, shown in FIG. 2. As is apparent from FIG. 3, each cycle of the synthesized current waveform s,(t) is characterized by eight distinct phases P -P which are all of equal duration, (T/8).

Formulation of the current waveform s (t), shown in FIG. 3, by the circuit shown in FIG. 2, requires the following output resistor values: R 1+ V2) R,,; R R R R and R =(l l 1/ 2 I R is a constant factor found in R through R.,. Although it is not specifically taught in the prior art, it has been observed that the output resistor values in prior art shift register circuits of the type shown in FIGS. 1 and 2 satisfy the formula R, K/(cos 2 vri/N) cos(2 -n'(i1)/N)), (1)

where N is an even integer; i is an index variable corresponding to the number of the stage to which the particular output resistor having that subscript number is connected, 1' running from 1 to N/2 (beginning at the input stage of the register); and K is a constant of proportionality. In the past, deviation from these values would cause an increase in the harmonic content and a resulting deterioration in the quality of the synthesized waveform. It has been recently discovered, however, that the resistance values of output resistors R, through R are more advantageously chosen according to the formula (2) where N is an even integer greater than or equal to six; i is an index variable corresponding to the number of the stage to which the particular output resistor having that subscript number is connected,.i== l, 2, (N12) (beginning at input stage 1 of the shaft register), and K is a constant of proportionality.

A variety of advantages are realized by choosing output resistor values in accordance with formula (2) rather than formula (1 One such advantage is that the last or (N/2)th stage of the shift register and its output resistor can be eliminated without introducing additional harmonic distortion into the synthesized waveform. The reason why the (N2)th stage can be eliminated is that choosing output resistor values according to formula (2) always results in the value of the output resistor associated with the (N2 )th stage becoming infinite. The (N/2)th stage is therefore not necessary and the desired sinusoidal waveform can be synthesized from the remaining [(N/2 l stages of the shift register. Moreover, a synthesized waveform generated by such an [(N/2-l )l-stage circuit is of substantially the same quality or harmonic content as one generated by a corresponding (N/2)-stage circuit, despite the fact that differently formed approximations of the desired sinusoidal waveform are generated by the (N/2)-stage and [(N/2-l )]-stage circuits, as is apparent from a comparison of current waveforms s,(t) and s (t) depicted in FIGS. 3 and 5, respectively. This important feature is achievable in the [(N/2-1 )]-stage circuit for any even integer value of N greater than or equal to six.

A more important advantage achieved by selecting the values of the remaining [(N/2-l output resistors according to formula (2) is that the ratio of the values of the largest and smallest remaining output resistors is reduced or minimized with respect to the prior art. This feature is of significant importance in manufacturing this type of shift register because, as is pointed out above, manufacturing tolerance constraints on the output resistors are more easily met as the ratios of the respective resistor values decrease.

A comparison of formulas (1) and (2) reveals that formula (2) differs from formula l in the respect that the argument of each cosine term in formula (2) includes the phase angle (rr/N) radians. The primary physical effect of including this phase angle in formula (2), other than changing the resulting values of the output resistors, is that a waveform generated by a circuit designed in accordance with formula (2) is shifted in phase by (7T/N) radians with respect to a waveform generated by a circuit designed in accordance with formula l A minor physical effect is that, for the same digital input waveform, the amplitude of the resulting synthesized waveform is decreased slightly by an amount depending upon the value of N. Since the relative phase and amplitude of such waveforms are usually not of any particular significance, however, in the type of applications in which such waveforms are normally utilized, the reduced hardware requirements are achieved in the [(N/2-l )]-stage shift register at the expense of adjusting parameters which are under no critical design constraints.

A sinusoidal waveform s (t) (N=8), synthesized in accordance with the invention in the circuit shown in FIG. 4, is depicted in FIG. 5. The eight distinct phases per cycle of the waveform are indicated by reference characters P,P As is apparent from FIG. 5, current waveform s (t) is synthesized from three differently shifted and weighted digital voltage waveforms d (t), d (t), and d (t), all having a frequency f [f =(lT and a magnitude V. Voltage waveforms d (t), d (t), and d t) are respectively generated at the outputs of shift register stages 1, 2', and 3 of three-stages serial shift register 50. Waveforms d (t), d (t), and d (t) are generated in response to (a) the coupling of the digital signal d(t), having the frequency f through lead 1 into the signal input of stage 1, and (b) the coupling of the digital shifting signal d(t), having a frequency Nf through lead 20 into shifting inputs S S and S of

stages

1', 2, and 3, respectively. The resulting waveforms d,(t), d (t), and d (t) are coupled through output resistors R,, R and R respectively, to summing terminal 30 to form s-,,(t). The values of resistors R R and R calculated in accordance with formula (2), are as follows: R \QR R R and R VTR R is a common factor found in R, through R as well as in R through R, (shown in FIG. 2).

A Fourier analysis of current waveform s (t) reveals that it has the same amount of harmonic distortion as current waveform s,(t), shown in FIG. 3, which is generated by the four-stage prior art shift register circuit illustrated in FIG. 2. It is therefore apparent that a synthesized sinusoidal waveform having a quality equal to that of s (t), which is generated in a four-stage [(N/2=4)] shift register circuit, can be generated in but a three-stage [(N/2-l=3)] shift register circuit. Moreover, it is further apparent that the ratio between the largest and smallest output resistors,

required to generate s (t) in the [(N/Z-I )]-stage shift register circuit shown in FIG. 4 is reduced with respect to the ratio between the largest and smallest output resistors,

required to generate s,(t) in the (N/2)stage shift register circuit shown in FIG. 2. As was pointed out in the foregoing review of the prior art, this results in significant advantages in manufacturing the [(N/ 2-1 )]-stage shift register circuit.

An equivalent embodiment of the invention is achieved which obviates the need for stage 1 of shift register 50', shown in FIG. 4, without causing any deterioration'in the resultant waveform s (t). In this embodiment of the invention, component d (t) is generated externally and fed directly into the signal input of stage 2. The circuit shown in FIG. 4 is then reduced to [(N/22).]-stage register 50", shown in FIG. 6. As can be seen in FIG. 6, shift register 50" features but two shift register stages, 2" and 3", and three resistors R,", R and R whose values are calculated in accordance with formula (2). Output resistor R is connected directly to the signal input of shift register stage 2", into which is coupled d,(t). It is apparent, however, that in the equivalent embodiment of the invention shown in FIG. 6, the summing circuit receives the same number of differently shifted components as in the embodiment of the invention shown in FIG. 4. Moreover, it should be further apparent that the amplitudes of the components coupled to the summing circuit in the embodiment of the invention shown in FIG. 6 are the same as in the embodiment of the invention shown in FIG. 4.

integer greater than or equal to six, said circuit comprising:

a shift register having plural serially connected stages;

means for coupling a shifting signal having a frequency Nfi, to each of said stages;

means for coupling a digital signal having a repetition frequency f into the signal input of a first one of said stages;

a summing terminal; and

no more than [(N/2l)] output resistors, each of said resistors connecting from said summing terminal to the signal output of a different one of said stages.

2. A shift register circuit comprising:

a plurality of shift register stages connected in a serial string;

means for coupling a shifting signal to the shifting signal input of each of said stages;

means for coupling a digital waveform into the signal input of the first stage in said serial string of stages;

a summing terminal; and

no more than [(N/21)] resistors, each of which connects tw said sqt m aetst nina an he signal output of a different one of said stages and the values of which relate to one another in accordance with the formula where N is an even integer greater than or equal to six, i is an integral index variable corresponding to the number of the stage to which ,the resistor having that subscript number is connected, i ranging from 1 to [(N/2-1 (beginning at the first stage of said string of stages), and K is a constant of proportionality.

3. A tapped delay circuit for digitally synthesizing a sinusoidal waveform, comprising:

a serial shift register for providing at tapped signal outputs thereof plural differently delayed components of a digital waveform;

a common summing terminal;

resistive means for coupling said differently delayed components from said tapped outputs to said common summing terminal, including plural resistors having values in accordance with the formula where i is an integral index variable, K is a constant of proportionality, and N is an even integer of greater than or equal to six and of a magnitude selected in accordance with the degree of harmonic distortion in the resulting synthesized waveform.

4. A circuit in accordance with claim 3 wherein said shift register comprises [(N/2-l stages; and

said resistive means includes [(N/2-l output resistors.

5. A circuit in accordance with claim 3 wherein said shift register comprises no more than [(N/ 2-2 stages; and

said resistive means includes [(N/2-1 output resistors.

6. A circuit in accordance with claim 4 wherein said shift register comprises [(N/22)] stages; and said resistive means includes no more than [(N/22)] output resistors.

no more than

Claims

1. A circuit for digitally synthesizing a stepped approximation of a sinusoidal waveform having a fundamental frequency F0 and having N phases of equal duration per cycle of the waveform, where N is an even integer greater than or equal to six, said circuit comprising: a shift register having plural serially connected stages; means for coupling a shifting signal having a frequency Nf0 to each of said stages; means for coupling a digital signal having a repetition frequency f0 into the signal input of a first one of said stages; a summing terminal; and no more than ((N/2-1)) output resistors, each of said resistors connecting from said summing terminal to the signal output of a different one of said stages.

2. A shift register circuit comprising: a plurality of shift register stages connected in a serial string; means for coupling a shifting signal to the shifting signal input of each of said stages; means for coupling a digital waveform into the signal input of the first stage in said serial string of stages; a summing terminal; and no more that ((N/2-1)) resistors, each of which commects between said summing terminal and the signal output of a different one of said stages and the values of which relate to one another in accordance with the formula Ri K/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N+ pi /N)), where N is an even integer greater than or equal to six, i is an integral index variable corresponding to the number of the stage to which the resistor having that subscript number is connected, i ranging from 1 to ((N/2-1)) (beginning at the first stage of said string of stages), and K is a constant of proportionality.

3. A tapped delay circuit for digitally synthesizing a sinusoidal waveform, comprising: a serial shift register for providing at tapped signal outputs thereof plural differently delayed components of a digital waveform; a common summing terminal; resistive means for coupling said differently delayed components from said tapped outputs to said common summing terminal, including plural resistors having values in accordance with the formula Ri K/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N + pi /N)), where i is an integral index variable, K is a constant of proportionality, and N is an even integer of greater than or equal to six and of a magnitude selected in accordance with the degree of harmonic distortion in the resulting synthesized waveform.

4. A circuit in accordance with claim 3 wherein said shift register comprises ((N/2-1)) stages; and said resistive means includes ((N/2-1)) output resistors.

5. A circuit in accordance with claim 3 wherein said shift register comprises no more than ((N/2-2)) stages; and said resistive means includes no more than ((N/2-1)) output resistors.

6. A circuit in accordance with claim 4 wherein said shift register comprises ((N/2-2)) stages; and said resistive means includes no more than ((N/2-2)) output resistors.