US3871168A

US3871168A - Electronic circuit for correction of the time display on an electronic timepiece

Info

Publication number: US3871168A
Application number: US276317A
Authority: US
Inventors: Pierre-Andre Maire; Hubert Portmann
Original assignee: Compagnie des Montres Longines Francillon SA
Current assignee: Longines Watch Co Francillon Ltd
Priority date: 1971-08-27
Filing date: 1972-07-31
Publication date: 1975-03-18
Anticipated expiration: 1992-03-18
Also published as: FR2150706A1; DE2238827C3; FR2150706B1; CH555562B; CH1258471A4; DE2238827A1; DE2238827B2; JPS4832567A; GB1395373A

Abstract

An electronic circuit for correction of the time display on an electronic timepiece, this circuit including a selector switch having a rest position for which the timepiece advances normally, and operating positions for minute setting, hour setting and day setting. Delay means are connected between said selector switch and the setting means of one or more display means for minutes, hours or days in order that such setting means only start to operate when the selector switch has been shifted to the operating position for a sufficiently long time, but are inoperative if the selector switch is rapidly shifted through this operating position.

Description

United States Patent Maire et al.

[ ELECTRONIC CIRCUIT FOR CORRECTION I OF THE TIME DISPLAY ON AN ELECTRONIC TIMEPIECE [75] Inventors: gz g fi tz g m z- :13:5 Primary E.\'aminerRichard B. Wilkinson switzerland Assistant Examiner-U. Weldon Attorney, Agent, or Firmlmirie, Smiley & Linn [73] Assignee: Compagnie des Montres Longines Francillon S.A., Saint-Imier, Switzerland [57] v ABSTRACT [22] Filed: July 31, 1972 An electronic circuit for correction of the time display on an electronic timepiece, this circuit including a se- [211 App! 276317 lector switch having a rest position for which the timepiece advances normally, and operating positions for [30] Foreign Application Priority Data minute setting, hour setting and day setting. Delay Aug 27, 1971 Switzerland H 12584/71 means are connected between said selector switch and the setting means of one or more display means for [52 US. Cl. 58/23 R, 58/855 minutes, hours or day in Order that Such Setting (51] Int. Cl G04c 3/00 means only Start to Operate when the Selector Switch [58] Field of Search 58/23 R, 23 A, 33, 34, has been shifted to the Operating position'for Suffi- 58/63, 55 ciently long time, but are inoperative if the selector switch is rapidly shifted through this operating posi- [56] References Cited UNITED STATES PATENTS 9 Claims, 3 Drawing Figures 3,643,418 2/1972 Polin et a1 58/23 R I l 2 l B OSCILLATOR FREQ- DlVlDER PATENTED MAR 1 8 I975 ca k SEQ BACKGROUND OF THE INVENTION The present invention relates to an electronically driven watch having electronic hour setting.

In an'electrically driven watch or clock, the operation of time indication resetting can be effected in two main ways; one is to accelerate the rate of counting of the display system, either forward or reverse until correspondence between the indicated hour and the correct hour is obtained; the other involves stopping the display system until the time indication is correct, and then putting it into operation again. In a mechanically driven watch the hour and minute hands can be moved by the intermediary of a coupling system operated manually by the winder stem; the movement of the hands depends on the movement of the stem.

When a watch or a clock has a digital display, the electronic drive systems may permit accelerated movement of the display mechanism. Here a single accelerated counting speed is not utilisable, being either too slow for correcting the display, but controllable by the user, or too quick for precise indication setting.

Several impulse rates are thus necessary, of different speeds of counting, the speed diminishing as the correct setting is approached.

Various solutions are possible, two being given below.

la. Press button stopping the actuation of the watch. b. One push button for accelerating the counting (factor 1000).

0. One push button for accelerating the counting (factor d. One push button providing resetting to zero of the seconds counter.

2a. One push button for supplying a frequency of lHZ to the minutes counter.

b. One push button supplying a frequency of lHZ to the hours counter.

c. One push button for stopping and starting the watch.

It is clear that the button 2c can be combined with a zero setter of the seconds counter after the stopping function.

The inconvenience of these difference systems is that in each case several buttons are necessary. If the watch indicates the date, a further button is required.

SUMMARY OF THE INVENTION It is the object of the present invention to provide a solution which avoids such inconvenience. It is concerned with an electronic watch having an electronic.

time resetting means which is characterised in that it comprises a single commutator or rotatable switch all the functions necessary for indication resetting as well as an appropriate circuitry allowing rotation of the commutator through intermediate positions without undesired actuation.

Normally a rotating commutator only provides two functions without risk of disturbing the others; to right or to left of a neutral position.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings show two possible em bodiments of electronic circuits as well as one embodiment of a commutator in accordance with the present invention.

The two circuits shown are for a watch having digital display. It is possible to adapt them to watches having a conventional or hand display.

In the drawings, FIG. 1 shows a first electronic circuit in block diagram for use with a drive oscillator.

FIG. 2 is an alternative diagram without an oscillator, and

FIG. 3 shows a commutator.

DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows clearly the different elements of'an electronic watch. These include a counting chain 1. comprising an oscillator l, for instance a quartz oscillator, a frequency divider 2, a seconds counter 3 with output 30 providing a display of seconds, a minute counter 4 with its output 4a providing a display of minutes, an hour counter 5 with its output 50, providing a display of hours, as well asa date counter 6 with its output 6a providing a display of the date. There is an AND gate 7 and three line selectors 8, 9 and 10. The detailed circuits of the different elements, the display decoders and the displays are not shown as these are known elements. For example, suitable line or data selectors which may be used with the present invention are disclosed in the 1970 Texas Instruments catalogue, at pages 367-372, which is incorporated herein by reference.

There is also a commutator switch II with a position 11 for normal watch operation, a position 12 for minute setting and for setting to zero the seconds, position 13 for setting the hours, and a position 14 for setting the date indicator. The switching arm of the commutator II is designated 15 and is connected to ground.

Positions

12, 13, and 14 are connected through suitable resistors to a voltage source P so as to have potentials 1 unless grounded by arm 15. A block flip-flop assembly III comprises a flip-flop 21, two

AND gates

22 and 23 and an inverter 24. Flip-flop 21 is set and reset respectively whenever its input potential changes from 1 to 0.

The delay circuit IV comprises a timer 31 which in this embodiment is a counter, two

AND gates

32 and 33 and two inverters 34 and 35.

The operation of the device is as follows.

During normal operation of the watch the arm 15 of the commutator I1 is located in the position shown in FIG. 1, in the normal working position 11. In this position the flip-flop 21 is in a set condition with similar potentials on its output 021 and its input T21. Consequently the AND gate 22 has potential applied to both inputs A22 and B22 so that the output C22 is energised. This applies potential to input B7 of the AND gate 7. Input A7 is fed at a frequency of lHZ from output B2 of the divider 2, this being determined by the frequency of the oscillator l and the dividing factor of frequency divider 2. When the AND gate 7 has simultaneously input signals on its two inputs its output C7 is energised, so that the seconds counter 3 is advanced by one step per second. Since the reset input B3 of counter 3 is inoperative it has no influence on the said counter. That means when a potential 0 is applied to the reset input B3, the counter 3 is reset to zero and cannot count again before a potential 1 appears at B3.

Since the inputA22 of the AND gate 22 is set (digit 1) and the input A23 of the gate 23 is at reset signal (digit the output C23 is reset (digit 0). Therefore For the commutator II: The point 13 becomes 0. The input A35 of the inverter 35 becomes 0 Le. A3

the input B8 of the line selector 8 is at O. The input C8 5 and by consequence of the selector 8 is connected to the output Q21 of flipflop 21, and inposition 11 of the arm 15 of the commutator II, a potential 1 is applied to the flip-flop so that its output 021 and output D8 of the said selector 8 is at l.

The two line selectors 9 and 10 are similarly energised under normal conditions, since the potentials at their inputs C9 and C10 are also 1 s. The counting chain 1 thus works continuously under normal conditions, and is not influenced by other parts of the circuit.

The following table gives the effects of moving the arm to its various positions.

For the flip-flop block III, when arm 15 is in the position 11 as shown in FIG. 1,

B24 =A23=(O) and v B23 B2 (l (starting condition) For the delay circuit IV l3 =A35 ==C9;-(l) (starting condition) since A35=(l) B35 B3l B32 =(0) (3i =A34 =B33 =(O) (starting condition) since A34=(0) B34=A32 (I) since A32=C32 =(l) but B32=(0) D32 =A3l (0) since A33=(l) (starting condition) and B33=C3l (0) For the date setting 14 and the line selector 1'0 B10 B2 (l) Thus all the line selectors 8, 9 and 10 have potentials 1 at their inputs C8, C9 and C10 respectively, so that their outputs D8, D9 and D10 are responsive to the inputs A8, A9 and A10 respectively. The potential 1 on one input B7 of the AND gate 7 and a potential 1 on the other input ensure that the output C7 also is at potential 1. Consequently the counting chain 1 is not disturbed by signals not appertaining to a time count.

if for one reason or another a correction of the hour display is necessary, the arm 15 is turned to position 13 (hour setting). The action of the circuit is now as follows:

In the counting chain,

The hour display is advanced by 1 hour each second due to the changing of the potentials in B9 and C9 of the line selector (see the explanation which follows).

since A32 C32 B32 (l) at this moment the timer 31 starts to count the seconds impulses which are being supplied thereto from output B2 through AND gate 32. This counting continues for a predetermined suitable number after which the potential at the output C31 changes and becomes C31 (l) by consequence A34 l) and B34 A32 (0) which blocks again AND gate 32; the output C31 of the timer 31 remains in the state 1 until the counter is returned to zero. Since now C3l B33 (l) and A33 (1) (starting condition) C33 B9 (l) which means that the l Hz input to the AND gate 33 is injected into the line selector 9, and since C9 (0) input B9 is connected to the output D9. In this manner the hour counter 5 is advanced at a frequency of 1 Hz, instead of a frequency of one impulse per hour; the hour display thus advances by one step per second.

At the instant when the display shows the required hour number, the arm 15 of the commutator II is replaced into the normal working position 11 whereby the output C31 of the timer 31 returns to 0. At this in stant the AND gate 33 is blocked, due to the fact that the inputs A33 and B33 have different potentials, so that the regulator is again blocked in itsin'itial state. When changing the position of arm 15 to position 11,

the point 13 and the input C9, of the line selector 9 be-.

come 1, so that the input A9 is again connected to the output D9. The watch resumes its normal working rate.

If at the end ofa month of 28, 29 or 30 days it is desired to advance the date indication, it is neccessary to operate in the following manner. The arm 15 of the.

commutator II is brought into the date setting position 14, passing through the hour hand setting position 13.

Due to the change of the potential of the point 14 and at input C10 of the line selector 10, the input B10 to which pulses at a frequency of 1 Hz are applied, is connected to the output D10, so that the date counter 6 advances by one step per second instead of one step per day. When the date display is correct the arm 15 is put back into the normal working position 11 so that the watch resumes its normal working rate.

Although there are two passages of the arm 15 past the setting position 13, the hour indication is not disturbed by this operation, since the time during which the potential of point 13 and by consequence the input A31 of the timer or counter 31 is changed, is not long enough to supply the number of impulses necessary to change the potential of the output C31 of the counter 31. This is the case even if the passage of the arm 15 over the point 13 is repeated several times because the counter 31 of the regulator 31 is reset to zero after each passage.

If finally, the minute display must be changed, the arm 15 of the commutator ii is first brought into the position 11, if not already there, and then moved to the minute setting position 12. The action of the circuit is as follows. The point 12 changes its potential and consequently the input T21 of the flip-flop 21 to 0, or

The changing of the potential on T21 produces a change of the potential at Q21 so that the two'inputs A22 and B22 of the AND gate 22 have a potential 0, so that the output C22 of the said gate becomes 0, and C22 B3 =B7 so that the two inputs A7 and B7 of the AND gate 7 now have different potentials. The output C7 A3 (input of the seconds counter 3), (O), which together with B3 (0) produces resetting to zero of the counter 3 (starting condition).

T21 A22 =A24 (0), and the output B24 of the inverter has now a potential B24 I) so that the AND FIG. 3 shows a transverse section of a commutator II,

a the following parts being represented; the arm l gate 23 now transmits second pulses from output B2 to the input B8 of the line selector 8.

The input C8 of the selector 8 having now a potential 0 due to. the changing of the potential of Q21, which has become 0 by reason of an impulse received as a result of the changing of state of T21, the output D8 is connected with the input B8 so that the pulses at a frequency of 1 Hz are injected into the minutes counter.

At the instant where the minute display indicates the .required number, the arm of the selector II is re- 'instant, the arm 15' is passed back into position 12 which again changes the potentials 12, T21, A22, A24, B24 andA23, and since flip-flop '21 is now reset that of the points 021, B22 and C8. The result of those changes of potential is that the line selector 8 changes state and-reconnects the outlet D8 to the input A8. The AND gates 22 and 7 remain blocked. Thereafter the arm 15 is brought to the normal working position 11,

so that the AND gates 22 and 7 change state and the watch starts working normally again.

It can thus be seen that it is possible to correct each display element .without disturbing the others.

FIG. 2 shows a block diagram not requiring a flip-flop.

tor II has an extrajposition. These are a minute setting position 12a, a zero setting position 12b, normal working 11, hour setting 13 and date setting 14.'Point 12a of commutator II is directly connected to terminals B3 and B7, while point 12b is connected to the input A35 of a delay circuit IV and to terminal C8 respectively, the output C33 of this delay circuit IV being connected to input B8 of theline selector 8. In this case, minute setting is effected by shifting arm 15 to position 12b for a sufficiently long time exceeding thev delay time of circuit IV. Delay networks IV are identical to the correspondingly identified circuits of FIG. 1 and are not illustrated in detail for the sake of brevity. The seconds display may be reset to zero and maintained in this starting condition as long asarm 15 is shifted to position 12a. In this case rapid passage of the arm 15 over point 12b remains without effect due to the delay circuit IV connected to point 12b. Otherwise the operation ofthis circuitand ancillary connections are similar to that of FIG. 1 and are not, for this reason, described in detail.

formed as a bent spring, positioning balls 15a, a stem 17 allowing adjustment of arm 15 from the outside of the back 18 of the watch casing, and a sealing element 19. The arm 15 is shown in contact with a fixed conductor 16, which can be either the point of normal working 11, or one of the

points

12, 12a, 12b, 13 or 14' of FIGS. 1 and 2. These conductors 16 can be mounted directly on the insulating base 16a of the electronic circuit of the watch. Spring 15 is connected to the watch casing by its stem Hand is thus maintained at O p,oten-- tial. To avoid disturbing impulses at the instant of commutation, the flip-flops of the circuit comprising the flip-flop 21 (FIG. 1) and the flip-flops of the timer or timers IV (FIG. 1, 2) can be synchronously'operated.

What we claim is:

1. An electronically driven watch comprising a counting chain having an oscillator as a time-base connected to a divider for providing seconds pulses to drive a series of counters in sequence, setting means including a single commutator having an arm movable to a normal position contact and a plurality of setting position contacts, circuit means connected with said counters, said divider, and said setting position contacts of said commutator for applying the seconds pulses of said divider to selected ones of said counters in response to movement of said arm from said normal position contact to respective ones of said setting position contacts for individually changing the setting of corresponding ones of said counters, and delay means interposed between at least one of said setting position contacts and said circuit means for delaying the changing of the counter associated with said one position contact upon movement of said commutator arm past said one position contact.

2. A watch in accordance with claim 1 wherein said circuit means includes a flip-flop connected with at least a first one of said series of counters for resetting said first counter to.zero and interrupting the counting of said counting chain in response to movement ofsaid commutator arm to afirst setting position contact.

3. A watch in accordance with claim 2 wherein'the commutator arm is rotatable and has a plurality of positions. I

4. A watch in accordance with claim 3', wherein the contacts of the commutator are mounted on an insulating base of saidc'ircuit means.

5. A watch in accordance with claim 3, wherein the arm of the commutatoris mounted on the back ofa casing for the watch. j

6. A watch in accordance with claim 13, wherein said commutator has four position contacts whereof the two middle position contacts are said normal position contact and said one position contact respectively.

7. A watch in accordance with claim 2, wherein said commutator has five position contacts whereof the middle position contact is said normal contact while one of the two position contacts adjacent said middle position contact is connected to said delay means and the other is connected to a second delay means. v

8. A watch in accordance with claim 2, wherein said delay means includes a counter.

9. A watch according to claim 2, wherein said circuit means includes a flip-flop circuit connected with its input to a contact of said commutator corresponding to a first setting position for correction of a first and a second counter in said series of counters, means controllable by the signal on said contact for connection of said setting to zero said first counter during the set condiseconds pulses output from said divider to an'input tion of said flip-flop. feeding said second counter, and means connected to the output of said flip-flop circuit for stopping and re-v UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3,871,168 DATED March 18, 1975 INVENTOR(S) Pierre-Andre Maire et a1 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Claim 6, line 1:

"A watch in accordance with claim g instead of 13 Signed and sealed this 1st day of July 1975.

$2911...) ittest:

C. ZLXRSILALL DANE Commissioner of Patents and Trademarks UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3,871,168 DATED March 18, 1975 INVENTOR(S) Pierre-Andre Maire et a1 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Claim 6 line 1:

"A watch in accordance with claim 2 instead of 13 Signed and sealed this 1st day of July 1975.

fittest:

C Z L-.RSI-L1LL DANE RUTH C. 1135-31? Commissioner of Patents Attesting Officer and Trademarks

Claims

2. A watch in accordance with claim 1 wherein saId circuit means includes a flip-flop connected with at least a first one of said series of counters for resetting said first counter to zero and interrupting the counting of said counting chain in response to movement of said commutator arm to a first setting position contact.

3. A watch in accordance with claim 2 wherein the commutator arm is rotatable and has a plurality of positions.

4. A watch in accordance with claim 3, wherein the contacts of the commutator are mounted on an insulating base of said circuit means.

5. A watch in accordance with claim 3, wherein the arm of the commutator is mounted on the back of a casing for the watch.

7. A watch in accordance with claim 2, wherein said commutator has five position contacts whereof the middle position contact is said normal contact while one of the two position contacts adjacent said middle position contact is connected to said delay means and the other is connected to a second delay means.

9. A watch according to claim 2, wherein said circuit means includes a flip-flop circuit connected with its input to a contact of said commutator corresponding to a first setting position for correction of a first and a second counter in said series of counters, means controllable by the signal on said contact for connection of said seconds pulses output from said divider to an input feeding said second counter, and means connected to the output of said flip-flop circuit for stopping and resetting to zero said first counter during the set condition of said flip-flop.