US3876208A - Gaming machine - Google Patents

Gaming machine Download PDF

Info

Publication number
US3876208A
US3876208A US399333A US39933373A US3876208A US 3876208 A US3876208 A US 3876208A US 399333 A US399333 A US 399333A US 39933373 A US39933373 A US 39933373A US 3876208 A US3876208 A US 3876208A
Authority
US
United States
Prior art keywords
memory
output
gate
inputs
stages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US399333A
Inventor
Gunter Wachtler
Wolfgang Straszer
Peter Uri
Russi Tschernev
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19722245969 external-priority patent/DE2245969C3/en
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of US3876208A publication Critical patent/US3876208A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07FCOIN-FREED OR LIKE APPARATUS
    • G07F17/00Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F1/00Card games
    • GPHYSICS
    • G07CHECKING-DEVICES
    • G07FCOIN-FREED OR LIKE APPARATUS
    • G07F17/00Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G07F17/3286Type of games
    • G07F17/3293Card games, e.g. poker, canasta, black jack
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F1/00Card games
    • A63F2001/008Card games adapted for being playable on a screen

Definitions

  • An electronically controlled gaming machine having poker-like rules of play, the machine comprises a matrix of card memory stages in rows and columns, each [30] Foreign Application Priority Data memory stage having three conditions and an output Sam 20 1972 Germany H 2245969 which is energised in one of the conditions.
  • An indicator device includes a plurality of indicators one con- [52 115, CL 273 133 373 E nected to each memory stage for illumination, when 1511 Int. Cl. A63f 9/00 the Output of the associated memory Stage is s 5 pi of Seamh H 273 1 5 1 R 1 M 13 A ised.
  • a dealing unit provides five sequential impulses 273/139 142 B 143 R 143 A 143 B [43 C to energise a random selection of five of the memory 143 D 143 E stages to represent five cards being dealt
  • a card return unit allows up to three of the memory stagesso [56] Ref Ci d energised to be de-energised and subsequently UNITED STATES PATENTS blocked from re-energisation and the dealing unit can 2998757 8196' M v 773 I R then be reoperated randomly to energise different 197!
  • the present invention relates to a gaming machine with poker-like rules of play, in accordance with which firstly five cards are dealt, then there is the possibility of returning up to three cards again and in return buying a corresponding number of new cards and finally the score is determined in accordance with the final distribution of the points and suits of the cards which has been dealt.
  • One aim of the present invention is to provide a gaming machine which so imitates the game of poker, the most-played card game of the World, in a simplified form that each individual player can play against chance, there is the greatest possible urge to play further games and cheating is practically impossible,
  • an electronically controlled gaming machine adapted to play card games with poker-like rules of play, comprises an indicating unit having a plurality of selectively operable cardrepresenting indicator devices, one for each card of a group of possible cards; a card memory having a plurality of memory stages one for each indicator device, each card memory stage having an input thereto and an output connected to the associated indicator device, and being operable to assume one of three memory conditions, a reception condition, a memory condition, and a blocking condition, each said memory stage operating to produce an output signal when in said memory condition and no output signal when in said reception condition or said blocking condition, and switching to said memory condition on the occurrence of a signal on said input if it is in said reception condition but not if it is in said blocking condition; a dealing unit having a plurality of outputs each connected to the inputs of a respective card memory stage, said dealing unit comprising in combination, a random signal generator, means connecting said random signal generator to all said outputs from said dealing unit, means for cyclically enabling said outputs from said
  • the stake unit comprises preferably a token input and checking device, for example a coin checker, and a credit balance memory, which stores the credit balance and indicates what credit balance can be made up from the amount placed by the player in the form of tokens in the gaming machine and also from the winnings.
  • a token input and checking device for example a coin checker
  • a credit balance memory which stores the credit balance and indicates what credit balance can be made up from the amount placed by the player in the form of tokens in the gaming machine and also from the winnings.
  • the gaming machine can furthermore comprise a pay-out unit with an operating element, which makes it possible for the player to have paid out the credit balance present or a desired part of it.
  • FIG. I shows a block circuit diagram of a gaming machine in accordance with the invention, comprising a card memory, an indicating unit, a card return unit, a dealing unit, a result read-out unit, a controlled unit, and a paying out unit.
  • FIG. 2 shows a somewhat simplified circuit of the card memory, the indicating unit and the card return unit.
  • FIG. 3 is a block circuit diagram of dealing unit.
  • FIGS. 4a to 4f show circuit diagrams of parts of the result read-out unit.
  • FIG. 5 shows a circuit of the control unit.
  • FIG. 6 shows a diagrammatic representation of the credit balance unit and the paying out unit.
  • the player pays his stake by inserting coins of money, which are checked by a coin checker and which on receipt of the inserted coins supplies corresponding count signals to a credit balance memory. It is naturally possible to use other tokens, such as chips or banknotes and the like. Instead of the coin checker use will then be made of a suitable token input and checking device, which can be constructed in a conventional manner.
  • the gaming machine shown in block form in FIG. 1 comprises a stake unit 11 with a coin checker l3 and a credit balance register 14, and furthermore a card memory 15 with a card indicating device 17, and also a dealing unit 19, a card return unit 21, a result readout unit 23, a control unit 25, which controls the course of the game in as far as it is not to be influenced by the player himself, and a paying out unit 27, which comprises a coin store 29 and a coin delivery device 31.
  • the coin store 29 preferably accepts the coins accepted by the coin checker 13.
  • the indicating unit 17 comprises fields 18, which can be illuminated, for the 32 cards of a skat game.
  • the card memory 15 correspondingly comprises 32 memory stages and the card return unit 21 comprises 32 card return buttons or switches.
  • the card memory still stores the results of the preceding game and correspondingly the indicator unit 17 indicates the cards drawn in the preceding game. In the case of an objection by a player this makes possible a check of the result of play by the supervisiing staff.
  • the credit balance memory 14 For playing a game it is necessary for the credit balance memory 14 to have a sufficient credit balance. In the case of the embodiment described for the initial dealing of five cards one coin unit (for example 1 DM) is required and a further coin unit is required for each newly bought card after card return.
  • the necessary credit balance in the credit balance memory 14 can be built up by inserting coins 35 into the stake unit 11 or can be drawn from an earlier win.
  • the commencement of play takes place by actuating a start button 37, which is coupled with the control unit 25.
  • the actuation of the start button 37 ensures that all stages of the card memory 15 are returned to the resting condition and correspondingly all fields 18 of the indicating device are dark, that is to say switched off.
  • the control unit then gives a dealing command to the dealing unit 19, which in a purely statistical manner sets five memory stages of the card memory 15 in sequence.
  • the cards dealt in this manner in a completely random fashion are indicated by illuminated fields 18 of the indicating device 17.
  • the dealing unit will be explained in more detail presently.
  • the player has the possibility, after issue of the first five cards, of returning up to three of the cards dealt by actuation of corresponding return buttons in the card return unit 21.
  • the card return button By operation of the card return button the memory stage associated with the return card is switched over from the first memory condition into the second one and the associated field 18 in the indicating device 17 becomes dark.
  • the result read-out unit 23 is caused to check the memory stages which are in the first memory condition, that is to say the dealt cards, to see whether a score has been obtained or not.
  • the credit balance memory 14 is empty, that the coin store 29 contains a certain amount of coins, and that in the card memory the five cards drawn in the preceding game are stored.
  • the indicating unit 17 therefore shows the views of these five cards by means of the corresponding illuminated fields l8, and preferably also any score or winning obtained.
  • the coin checker can be of a conventional construction (see for example the German Pat. No. 2,029,751) and on accepting a coin passes an electrical pulse to the coin gate which is normally comprised in a coin checker so that the accepted coin passes through a receiving channel 41 (FIG. 6) into the coin store 29, which can consist for example of a vertically placed tube.
  • the pulse produced on acceptance is also supplied to a forward count input VZ of a reversible counter 43 contained in the credit balance memory 14 and the counter 43 is provided with an indicating device 45, which indicates the credit balance.
  • the credit balance unit 14 furthermore comprises a decoder connected with the counter 43 which supplies an output signal at an output line 49 when the counter 43 is at zero.
  • the line 49 leads to an inverter 51, at whose output, therefore, a credit balance signal GU is produced when the counter 43 stores a credit balance different from zero.
  • the player After the insertion of one or more coins the player then actuates the starting button 37 (FIG. 5) which cuases a monostable multivibrator (referred to below as "monoflop") 53 which on actuation supplies a pulse of predetermined length at one of two inputs of an AND- gate 55.
  • a monostable multivibrator referred to below as "monoflop" 53 which on actuation supplies a pulse of predetermined length at one of two inputs of an AND- gate 55.
  • the credit balance signal GU At the second input of the AND-gate the credit balance signal GU is present and, since it was assumed that the credit balance differed from zero, the pulse from the monofiop 53 can pass through the AND-gate 55.
  • the output pulse of the AND-gate serves as a resetting pulse RS, which resets the card memory and the score determining circuit with the associated indicating means at zero.
  • the output pulse RS furthermore passes through a delay member 57 and an OR-gate 59 and then passes to the setting input of the flip-flop 61, which is accordingly set.
  • a dealing command signal AB which is supplied to an AND-gate 63 (FIG. 3) in the dealing unit 19.
  • the AND-gate 63 has two further inputs, of which one receives clock pulses (with the frequency of for example 10 kHz) from an oscillator 65, while at the third input a dealing termination signal is present, which vanishes when five cards have been dealt.
  • the production of the dealing termination signal will be described presently in conjunction with FIG. 2.
  • the five stages of the counter each have a respective l-output and a O-output.
  • the signal L (binary number 1) occurs when the stage is set, while when the stage is reset an L" occurs at the 0-output".
  • the random signal generator 69 consists of a conventional circuit arrangement, for example a shift register provided with feed-back loops, which supplies a quasistatistical binary sign sequence with a very large cycle duration (see for example Gernam Pat. Nos. 1,188,123, 1,054,491 and 1,095,876).
  • the quasistatistical sign sequence produced by the random signal generator 69 is supplied to frequency divider 71, which reduces the frequency of the quasi-statistical pulse sequence to such a degree that the dealing" of the cards can be carried out with a sufficiently low speed in order to be observed.
  • the quasi-statistical pulse sequence divided as to frequency is shaped in a pulse-shaping and delay circuit 73 and brought into such a phase position with respect to the clock pulses TP fed to the counter 67 that the respective quasi-statistical pulses only occur after the counter 67 has terminated the switching over operation which was initiated by the corresponding clock pulse TP.
  • the quasi-statistical pulses (referred to in what follows as random pulses) Z are supplied from the output of the pulse-shaping and delay circuit 73 to a respective input of 32 AND-gates, which are arranged so as to correspond to a respective stage of the card memory (FIG. 2).
  • AND-gate 75 which is associated with the memory stage for the card T7 (seven of clubs).
  • THe AND-gates each have 8 inputs, of which five are connected with corresponding outputs of the stages of the counter 67, as is indicated in the table contained in FIG. 3.
  • the relevant five inputs of the AND-gate 75 of a first memory stage (that is to say in this case the memory stage T7) are connected therefore with the 1- output of the counter-stage l and with the O-outputs of the counter-stages 2 to 5.
  • signals only of the value L are present when the counter 67 is at (decimal) 1.
  • the clock pulses CP therefore the five inputs of the 32 AND-gates 75 are switched first into the enabled condition.
  • the remaining inputs of the AND-gate 75 are connected with the O-outputs of two flip-flops FFla and FFlb (FIG. 2) which together form the memory stage T7.
  • the card memory comprises 32 memory stages, which are arranged in four lines and eight columns, as shown in the following table and which respectively comprise two flip-flops corresponding to the flip-flops FFla and FF).
  • the setting input 8 of the flip-flop FFla is connected with the output of the associated AND-gate 75.
  • the flip-flop FFla is thus set if 1 the counter 67 is at the number coordinated with the relevant memory stage,
  • the signal L occurs at its l-output, while the signal at the O-output becomes zero and the AND-member is in the blocking condition.
  • the signal from the l-output of the flipflop FFla firstly switches an indicating device 79, for example an incandescent lamp of the corresponding field 18 of the indicatinig unit 17, which then indicates that the card in question has been dealt.
  • the signal passes from the l-output of the flip-flop 1a to one of 32 inputs of an OR-gate 81, whose output is connected with the forward counting input VZ ofa reversible counter 83.
  • the counter 83 can count to 5 and then always switches on one step it counts, one each time one of the first flip-flops of a memory stage is set (that is to say one of the flip-flops corresponding to the flip-flop FFla).
  • the counter 83 is at 5.
  • the counter 83 is connected with a decoder 85, which in the case of the counter condition 5 provides a signal 5k (five cards), which passes via an OR-gate 87 to the set input of the flip-flop 77 and sets the latter.
  • the signal AS vanishes and the card dealing is terminated by blocking of the AND-gate 63.
  • the signal AS can control an indicating means in a manner which is not shown.
  • the indicating means informs the player that he can return three of the dealt five cards and buy new cards in exchange. For this he is allowed a certain period of time, which in the case of the present example amounts to 20 seconds. If within 20 seconds the player does not return any card, the reading out of the result is started, as will be described presently.
  • the player desires to return cards.
  • the return of cards assumes that at least a credit balance of one coin unit is contained or stored in the credit balance memory.
  • Card return is carried out by actuating card return ittons 91 in the card return unit 21 (bottom of FIG.
  • the card return buttons 91 respectively drive or )ntrol a single-pole reversing switch 93, which are so )nnected in series in the manner shown in FIG. 2 that simultaneous return of two cards is impossible.
  • the return card switch 93 associated with the 1rd which is to be returned for example T7
  • the :ttng operation S of the second flip-flop of the releint memory stage that is to say of the flip-flop 1b of ie memory stage T7
  • a card return signal KRS is sup lied, which sets the relevant second flip-flop.
  • the clock pulses TP from the oscillator 65 are allowed to pass by the AND-gate 63 and the above-described dealing operation begins again.
  • the flip-flop 77 is set by the signal 5K again and the dealing operation is again terminated.
  • the lines (for example line 97) leading from the reersing switches 93 to the setting inputs S of the second lip-flops of the memory stages are connected with the nputs of an OR-gate 99, which for each returned card upplies an output pulse.
  • This putput pulse is supplied ifter shaping by a pulse shaping circuit 101 to the reerse count input of the counter 83 as a reverse count .ignal RZS.
  • the counter 83 therefore makes one backyard count for each returned card amounting to one .tep.
  • the return of more than three cards is prevented iy the fact that the decoder 85 supplies a signal 2K two cards") in the case of the count 2 and this signal ,witches off the card return signal KRS from the card 'eturn unit 21.
  • the signal KRS is produced by the cir- :uit shown in FIG. 5.
  • It comprises an ANDgate 105 at whose output the signal NAS from the l-output of the flip-flop 103 the signal 514 of the decoder and the clock pulses TP of the oscillator 65 are present.
  • the clock pulses are therefore only allowed to pass when the flip-flop 103 is set and five cards have been dealt.
  • the clock pulses allowed to pass by the AND-gate 105 are passed to the setting input of a flip-flop 107, which is set by the first clock pulse allowed to pass.
  • the leading edge of the pulse occurring at its l-output triggers a monostable multivibrator 108 or monoflop, which supplies a memory signal to all eight stages of an eight-stage shift register 109.
  • the inputs of the eight stages of the shift register 109 are respectively connected with the output of an OR-gate 111a to 11112.
  • the inputs of each OR-gate are coupled with the loutputs of the first flip-flops of the memory stages of a column (see table 1).
  • the input, denoted T7, of the OR-gate 111a is thus connected with the l-output of the flip-flop FFla (FIG. 2).
  • a column signal SP1 therefore occurs when a card which has been dealt is found in the first column (see table 1), that is to say when a seven has been dealt.
  • the column signal SP8 thus occurs when an ace has been dealt.
  • the column signals SP1 to SP8 are stored by the memory signal produced by the monoflop 108, in parallel in the eight stages of the shift register 109.
  • the clock pulses from the output of the AND-gate 105 are furthermore supplied via a delay member 113 to shift inputs of the eight stages of the shift register 109.
  • the delay member is so dimensioned that the first clock pulse only occurs at the shift inputs when the storing operation of the column signals SP1 to SP8 is terminated.
  • the clock pulses then shift the content of the shift register into a counter 115, which can count to and is provided with a decoder 117, which has three outputs, at which a respective signal 28, 3S and 58 occurs when the cards dealt are in two, three and five columns respectively.
  • the column signals SP1, SP2, SP3, SP6, SP7 and SP8 are futhermore inverted by an inverter 119 and supplied in groups of three to the four NAND-gates 121 to 124 shown in FIG. 4a and these gates then only all supply an output signal L to an AND-gate 125, if the unoccupied columns are so distributed that a sequence is possible.
  • the AND-gate 125 has furthermore the signal 58 supplied to it as a fifth input signal; it therefore only supplies a sequence signal SQ when a sequence (independent of the suit of the cards), is present.
  • the circuit arrangement shown in FIG. 4b serves for determining poker, that is to say four cards of the same value (corresponding to a full column).
  • the output signals of the first flip-flop of the memory stages are supplied respectively in accordance with the columns to eight AND-gates 127a to 127h.
  • the AND-gate 127a therefore only supplies a signal VSl (column 1 full), when all four sevens have been dealt.
  • the outputs of the AND-gates 127a to I27): are connected with corresponding outputs of an OR-gate 129, at whose output a poker signal PS only occurs when a full column is present.
  • the circuit shown in FIG. 4C consists of an AND- gate 131 and supplies a signal 2A (two aces signal) when the ace of clubs and the ace of spades have been dealt.
  • the inputs of the AND-gate 131 could be connected with any two ace memory stages, since the circuit in accordance with FIG. 4c only serves for determining the ace poker.
  • the circuit in accordance with FIG. 4d serves for determining whether the cards dealt are distributed in one or more lines. This circuit supplies a signal 1 ZS (1 line) only when all cards dealt are to be found in a single line.
  • the circuit in accordance with FIG. 4d comprises for each line of the memory stage matrix (see table I) an OR-gate with eight inputs, of which only the upper gate 133 for the first line is shown.
  • the inputs of the OR-gate 133 have the signals of the l output of the first flip-flop of all memory stages of the first line supplied to them.
  • a line signal Z1 is always supplied when the first line (clubs) comprises a dealt card.
  • OR-gates which are not shown much the same applies.
  • the line signals Z1 to Z4 are supplied to corresponding inputs of a threshold gate 135, which supplies an output signal when two or more line signals are present at its outputs.
  • the output signal of the threshold gate .135 is inverted by an inverter 137. At the output of the inverter 137 a signal of the value L is therefore only present when all drawn cards are located in a single line.
  • the circuit in accordance with FIG. 42 serves for determining whether three of a kind have been dealt.
  • the four signals of each column in groups of three are supplied to three respective AND-gates I39, I40, 141, as is shown in FIG. 4e.
  • the outputs of the AND-members 139 to 141 are connected with the inputs of an OR-gate 143, which always supplies a signal D1 (three of a kind in column 1) when the first column comprises a three of a kind, that is to say when three sevens have been drawn.
  • GDR Three of a Kind winning score GFH Full House winning score GFL Flush Winning score GPI-I Poker winning score (single) GAP Ace poker winning score GSF Straight Flush winning score GRF Royal Flush winning score The winning scores can be indicated.
  • the player can cause his credit balance registered in the counter 43 to be paid out completely or partly at any time.
  • he actuates a paying out button 153, by means of which a circuit 155 is closed and a voltage U is supplied to an input of the AND-gate 157.
  • the credit balance signal GU is present.
  • the voltage U passes to a paying out device 159, which for example can comprise a reciprocating slight 161, which ejects the coins 35 stored in the coin stored 29 one after the other into a delivery pan.
  • the ejected coins are detected by a photoelectric light beam device and pulses produced as a result pass through a pulse shaping circuit 167 and an OR-gate 169 to the reverse count input of the counter 43. Therefore for each coin delivered the counter 43 is set back by one step. When the count reaches zero, the credit balance signal GU vanishes and the AND-gate 157 blocks and further delivery of coins is thus prevented.
  • the delayed signal from the output of the delay member 113 is supplied to a further delay member 170, which delivers a end of game reset signal RSS for the resetting circuit units of the gaming machine (with the exception of the card memory and the score indication means, which on resetting of the counter 115 is put out by the signal RS).
  • the duration of the delay is so selected that the above-described determination of the winning score is terminated before the signal RSS occurs.
  • the player does not return any cards, the win or score is determined after the expiry of seconds, after the card return signal KRS (FIG. 5) has disappeared.
  • the signal KRS is then supplied for this purpose via an inverter 172 and an OR-gate 174 to the AND-gate 105 and starts the same operation as after card return by the NAS-signal (which is supplied via the second input of the OR-gate 175 to the AND-gate 105).
  • An electronically controlled gaming machine adapted to play card games with poker-like rules of play, comprising:
  • an indicating unit having a plurality of selectively operable card-representing indicator devices, one for each card of a group of possible cards;
  • a card memory having a plurality of memory stages one for each indicator device, each card memory stage having an input thereto and an output connected to the associated indicator device, and being operable to assume one of three memory conditions, a reception condition, a memory condition, and a blocking condition, each said memory stage operating to produce an output signal when in said memory condition and no output signal when in said reception condition or said blocking condition, and switching to said memory condition on the occurrence of a signal on said input if it is in said reception condition but not if it is in said blocking condition,
  • a dealing unit having a plurality of outputs each connected to the inputs of a respective card memory stage, said dealing unit comprising in combination; a random signal generator, means connecting said random signal generator to all said outputs from said dealing unit,
  • a counter circuit connected to the outputs of all said memory stages and operable to produce an output pulse when a predetermined number of memory stages have been switched to their memory conditions
  • a card return unit having,
  • a new deal operating member connected to said dealing unit and operable to energise said dealing unit, when actuated, to randomly switch further memory stages to their said memory conditions until the said predetermined number of memory stages in the memory condition is re-established,
  • a stake unit having a coin or token receiving mechanism and means for producing an output signal when coins or tokens are held in said stake unit
  • inhibit means interconnecting the output of said stake unit and said dealing unit, operating to inhibit said dealing unit unless there is an output signal from said stake unit, and
  • result read-out means connected to said memory stages and operating to indicate the score obtained in dependence on which of said memory stages are in said memory condition.
  • each said card memory stage comprises first and second bistable circuits each having set and reset inputs and set and reset outputs, the set input of said first bistable circuit being connected to said dealing unit and the set input of said second bistable circuit being connected to a corresponding operating member of said card return unit, said set output of said first bistable circuit being connected to the corresponding indicating device, said reset outputs of both said first and said second bistable circuits being connected to respective inputs of the corresponding multiple input AND gate, whereby said memory stage is in said reception condition when both said bistable circuits are in their reset state, in said memory condition when said first bistable circuit is in its set state and said second bistable circuit is in its reset state, and in its blocking condition when said first bistable circuit is in its reset state and said second bistable circuit is in its set state.
  • a counter having a serial input connected to the output from said oscillator, said counter having a plurality of parallel binary outputs on which appear, in binary form, signals representing the number of pulses counted by said counter,
  • said dealing means additionally comprises a reversible counter having a forward input and a reverse input, and an output connected to a first decoder circuit having two outputs, one energised on a forward count of five signals and the other energised on a forward count of two signals,
  • said inhibit means includes a third bistable circuit having set and reset inputs and set and reset outputs, means connecting said set input to said one output of said first decoding circuit, means connecting said reset input to said other output from said decoding circuit, and
  • an AND gate having one input connected to said oscillator and an output connected to said counter, another input of said AND gate being connected to said reset output of said third bistable circuit whereby said AND gate is enabled when said third bistable circuit is in its reset state, and disabled when said third bistable circuit is switched to its set state upon the occurrence of an output signal on the said one output of said decoder circuit.
  • said operating members of said card return unit each comprise a single pole reversing switch for each memory stage, resilient biasing means biasing each reversing switch to one position, all said reversing switches being connected in series in a line when in said one position, and
  • an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register,
  • a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2,3 or 5 stages of said shift register in a binary 1 condition,
  • a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix,
  • a line number determining circuit operating to produce an output signal when all the memory stages of said matrix in said memory condition are disposed in a single line, said circuit comprising eight second OR gates each having eight inputs connected to the outputs of respective memory stages in a corresponding line,
  • threshold circuit having eight inputs connected to the outputs of the eight second OR circuits and operating to produce an output signal if there is a signal on two or more inputs thereof
  • a second invertor circuit connected to the output of said threshold circuit, the output of said second invertor circuit producing an output signal only when a signal is present on one input only of said threshold circuit
  • a second AND gate having three inputs respectively connected to the outputs of said second and third invertor circuits and said third output of said second decoder circuit.
  • an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary l state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a mamory condition, means for providing a train of clock pulses to the serial input of said shift register,
  • a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
  • a sequence determining circuit comprising six first invertor circuits, three of which are connected to the ouputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix,
  • an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition
  • a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
  • a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix,
  • a fourth AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first AND gate and the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces.
  • an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stges in the associated column is in a memory condition
  • a second decoder circuit connected to the output of said counter circuit.
  • said second decoder having first, second and third outputs respectively, energ ised an a output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or stages of said shift register in a binary 1 condition,
  • a seventh AND gate having two inputs respectively connected to the outputs of said sixth invertor circuit and said second OR gate, said seventh AND gate producing an output signal representing poker.
  • the gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has an ace poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
  • an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition
  • a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
  • an eighth AND gate having two inputs connected respectively to the output of said sixth AND gate and to the output of said second OR gate and producing an output signal representing ace poker.
  • the gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has a full house determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
  • an eight stage shift register having a serial input a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition
  • a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
  • a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a seventh invertor circuit connected to the output of said third OR gate,
  • a tenth AND gate having three inputs respectively connected to the outputs of said seventh inverter circuit, the output of said fourth OR gate and the first output of said decoder circuit, said tenth AND gate producing an output signal representing full house.
  • the gaming machine of claim 13 wherein the nemory stages of said card memory are arranged in a natrix of lines and columns, said lines corresponding to :he suits, and said columns corresponding to the card lalues in sequential order, and wherein said result read- )ut unit has a three-of-a-kind determining circuit com- )rising in combination a column number determining :ircuit including eight first OR gates each having four nputs, the inputs of each said first OR gate being coniected to the outputs of the memory stages ofa corre- ;ponding column,
  • an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition
  • a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
  • an eleventh AND gate having two inputs respectively connected to said second output of said second decoder circuit and the output of said fifth OR gate.
  • a coin or token checking device having an output which is energised upon insertion of a valid coin or token into said coin or token checking device
  • a credit meter having a reversible counter and an indicator showing the count in the counter, said counter having a forward input connected to the output of said coin or token checking device and a backward input connected to said coin or token payout device and to said card return unit,
  • a decoder circuit having an output which is energised when the count in said counter is zero
  • a payout inhibit device connected to said output of said decoder and operating to inhibit payout when the count in said counter is zero.

Abstract

An electronically controlled gaming machine having poker-like rules of play, the machine comprises a matrix of card memory stages in rows and columns, each memory stage having three conditions and an output which is energised in one of the conditions. An indicator device includes a plurality of indicators one connected to each memory stage for illumination, when the output of the associated memory stage is energised. A dealing unit provides five sequential impulses to energise a random selection of five of the memory stages to represent five cards being dealt. A card return unit allows up to three of the memory stages so energised to be de-energised and subsequently blocked from re-energisation and the dealing unit can then be reoperated randomly to energise different memory stages until five stages are energised. Control circuits connected to the rows and columns of the memory stage matrix then determine the score in accordance with poker-like rules.

Description

Wiichtler et al.
Apr. 8, 1975 [541 GAWNG MACHINE FOREIGN PATENTS OR APPLlCATlONS 1 lnvenwrsr Gunter Wiichtler Fischersmlsse 1 268,377 6/1966 Australia v. 273/[38 A Rottach-Egern; Wolfgang Straszer, gi g g ia Primary Exunu'ner-Paul E. Shapiro 552; a f s g Attorney. Agent, or Firm--Brisebois & Kruger l2. Neukeferioh, all of Germany 122 Filed: Sept. 20. 1973 {57} ABSTRACT [2]] App No 399 333 An electronically controlled gaming machine having poker-like rules of play, the machine comprises a matrix of card memory stages in rows and columns, each [30] Foreign Application Priority Data memory stage having three conditions and an output Sam 20 1972 Germany H 2245969 which is energised in one of the conditions. An indicator device includes a plurality of indicators one con- [52 115, CL 273 133 373 E nected to each memory stage for illumination, when 1511 Int. Cl. A63f 9/00 the Output of the associated memory Stage is s 5 pi of Seamh H 273 1 5 1 R 1 M 13 A ised. A dealing unit provides five sequential impulses 273/139 142 B 143 R 143 A 143 B [43 C to energise a random selection of five of the memory 143 D 143 E stages to represent five cards being dealt A card return unit allows up to three of the memory stagesso [56] Ref Ci d energised to be de-energised and subsequently UNITED STATES PATENTS blocked from re-energisation and the dealing unit can 2998757 8196' M v 773 I R then be reoperated randomly to energise different 197! A memory stages until five stages are energised Control 2 1 3 M971 'g' z 5 R circuits connected to the rows and columns of the 1,5 3/1972 jjj Ia X memory stage matrix then determine the score in ac- 3.733.075 5/1973 Hooker et al. .l 273 143 R x cordanfie with P rules- 3135382 5/l973 Gerfin i t 1 1 1 273M E 3.770.269 11/1973 Elder 273/1 E Drawmg J5 (F 37 J9 i ?ffifi? 53% F -I ffiir? STAKE U/V/T 5 L4 l l J I 25 age r504 353 I} 27;, 25 g rm 77' fit/3 s 1.1 1
l 1 24 JZIEELME IV p I /a;
--mn 11 l ii A; 2/ a no --11 a4/vi,er--L- T JL6! w E M! $53472 52% ,ejfrzew "New DEAL" BUTTON S W 5 MOI M m 7 m E w I! v D S t P k 7 5T 5 A T J F J 5 1 r 6 Wm FIG. 5.
GAMING MACHINE The present invention relates to a gaming machine with poker-like rules of play, in accordance with which firstly five cards are dealt, then there is the possibility of returning up to three cards again and in return buying a corresponding number of new cards and finally the score is determined in accordance with the final distribution of the points and suits of the cards which has been dealt.
One aim of the present invention is to provide a gaming machine which so imitates the game of poker, the most-played card game of the World, in a simplified form that each individual player can play against chance, there is the greatest possible urge to play further games and cheating is practically impossible,
According to the present invention an electronically controlled gaming machine adapted to play card games with poker-like rules of play, comprises an indicating unit having a plurality of selectively operable cardrepresenting indicator devices, one for each card of a group of possible cards; a card memory having a plurality of memory stages one for each indicator device, each card memory stage having an input thereto and an output connected to the associated indicator device, and being operable to assume one of three memory conditions, a reception condition, a memory condition, and a blocking condition, each said memory stage operating to produce an output signal when in said memory condition and no output signal when in said reception condition or said blocking condition, and switching to said memory condition on the occurrence of a signal on said input if it is in said reception condition but not if it is in said blocking condition; a dealing unit having a plurality of outputs each connected to the inputs of a respective card memory stage, said dealing unit comprising in combination, a random signal generator, means connecting said random signal generator to all said outputs from said dealing unit, means for cyclically enabling said outputs from said dealing unit whereby an output signal on one of said output lines is produced if a random signal occurs when said one of said output lines is enabled, said output signal operating to switch the card memory stage connected to said one of said output lines to its memory condition if it is in its reception condition, a counter circuit connected to the outputs of all said memory stages and operable to produce an output pulse when a predetermined number of memory stages have been switched to their memory conditions, and means interconnecting said counter and said random signal generator to inhibit the generation of further random signals upon the occurrence of said output signal from said counter indicating that said predetermined number of memory stages have been swtiched to their memory condition to represent the dealing of a predetermined number of cards, a card return unit having a plurality of operating members each connected to a respective memory stage and operating, when actuated, to switch the associated memory stage to its blocking condition from its memory condition, and a new deal operating member connected to said dealing unit and operable to energise said dealing unit, when actuated, to randomly switch further memory stages to their said memory conditions until the said predetermined number of memory stages in the memory condition is re-established, a stake unit having a coin or token receiving mechanism and means for producing an output signal when coins or tokens are held in said stake unit, inhibit means interconnecting the output of said stake unit and said dealing unit, operating to inhibit said dealing unit, unless there is an output from said stake unit, and result read-out means connected to said memory stages and operating to indicate the score obtained in dependence on which of said memory stages are in said memory condition.
The stake unit comprises preferably a token input and checking device, for example a coin checker, and a credit balance memory, which stores the credit balance and indicates what credit balance can be made up from the amount placed by the player in the form of tokens in the gaming machine and also from the winnings.
The gaming machine can furthermore comprise a pay-out unit with an operating element, which makes it possible for the player to have paid out the credit balance present or a desired part of it.
The principle of the invention and further advantages, forms and further developments of it are described in detail in what follows with reference to an embodiment shown in the drawings.
FIG. I shows a block circuit diagram ofa gaming machine in accordance with the invention, comprising a card memory, an indicating unit, a card return unit, a dealing unit, a result read-out unit, a controlled unit, and a paying out unit.
FIG. 2 shows a somewhat simplified circuit of the card memory, the indicating unit and the card return unit.
FIG. 3 is a block circuit diagram of dealing unit.
FIGS. 4a to 4f show circuit diagrams of parts of the result read-out unit.
FIG. 5 shows a circuit of the control unit.
FIG. 6 shows a diagrammatic representation of the credit balance unit and the paying out unit.
In the case of the following embodiments of the in vention the player pays his stake by inserting coins of money, which are checked by a coin checker and which on receipt of the inserted coins supplies corresponding count signals to a credit balance memory. It is naturally possible to use other tokens, such as chips or banknotes and the like. Instead of the coin checker use will then be made of a suitable token input and checking device, which can be constructed in a conventional manner.
The gaming machine shown in block form in FIG. 1 comprises a stake unit 11 with a coin checker l3 and a credit balance register 14, and furthermore a card memory 15 with a card indicating device 17, and also a dealing unit 19, a card return unit 21, a result readout unit 23, a control unit 25, which controls the course of the game in as far as it is not to be influenced by the player himself, and a paying out unit 27, which comprises a coin store 29 and a coin delivery device 31. The coin store 29 preferably accepts the coins accepted by the coin checker 13.
The indicating unit 17 comprises fields 18, which can be illuminated, for the 32 cards of a skat game. The card memory 15 correspondingly comprises 32 memory stages and the card return unit 21 comprises 32 card return buttons or switches.
Before giving a detailed description of the construction of the various units of the gaming machine only shown diagrammatically in FIG. 1, the rules of play and the general manner of operation of this gaming machine are to be explained.
Before commencing play all circuit units of the gaming machine are set in their resting conditions with the exception of the card memory. The card memory still stores the results of the preceding game and correspondingly the indicator unit 17 indicates the cards drawn in the preceding game. In the case of an objection by a player this makes possible a check of the result of play by the supervisiing staff.
For playing a game it is necessary for the credit balance memory 14 to have a sufficient credit balance. In the case of the embodiment described for the initial dealing of five cards one coin unit (for example 1 DM) is required and a further coin unit is required for each newly bought card after card return. The necessary credit balance in the credit balance memory 14 can be built up by inserting coins 35 into the stake unit 11 or can be drawn from an earlier win.
The commencement of play takes place by actuating a start button 37, which is coupled with the control unit 25. The actuation of the start button 37 ensures that all stages of the card memory 15 are returned to the resting condition and correspondingly all fields 18 of the indicating device are dark, that is to say switched off. After a certain delay (for example 0.5 seconds) the control unit then gives a dealing command to the dealing unit 19, which in a purely statistical manner sets five memory stages of the card memory 15 in sequence. The cards dealt in this manner in a completely random fashion are indicated by illuminated fields 18 of the indicating device 17. The dealing unit will be explained in more detail presently. Within a certain period (in this case for example 20 seconds), which is determined by the control unit 25, the player has the possibility, after issue of the first five cards, of returning up to three of the cards dealt by actuation of corresponding return buttons in the card return unit 21. By operation of the card return button the memory stage associated with the return card is switched over from the first memory condition into the second one and the associated field 18 in the indicating device 17 becomes dark.
After actuation of a new dealing button 39 (on the assumption that the credit balance in the balance memory I4 is sufficient) the same number of new cards are dealt as have been returned. The card memory is so constructed that the return cards cannot be dealt a second time. Therefore, in any event the player receives cards different to those which he has surrendered.
If the player does not require to return any cards, he actuates the new deal button 39 without having previously actuated a card return button.
When following the actuation of the card return button in the card memory 15 five memory stages are in the first memory condition, the result read-out unit 23 is caused to check the memory stages which are in the first memory condition, that is to say the dealt cards, to see whether a score has been obtained or not.
In the case of the present embodiment of the invention the following card combinations win. They are given in the order of increasing win quotas:
1 Three of a kind (three cards of the same value, that is to say for example three kings).
2 Full House (respectively three and two cards of the same value, for example three queens and two nines).
3 Flush (five cards of the same suit, which however do not form a sequence).
4 Ordinary poker (four cards of the same value, for example four queens, but not however four aces).
5 Ace poker (four aces).
6 Straight Flush (five sequentially following card values of the same suit, for example seven of hearts to jack of hearts) without an ace.
7 Royal Flush (five card values in sequence of the same suit including the ace).
The means for carrying out the above-mentioned functions and the course of play described are explained in what follows with reference to FIGS. 2 to 6.
In the case of the following description of the manner of operation of the present gaming machine with reference to a typical game it is to be assumed that the credit balance memory 14 is empty, that the coin store 29 contains a certain amount of coins, and that in the card memory the five cards drawn in the preceding game are stored. The indicating unit 17 therefore shows the views of these five cards by means of the corresponding illuminated fields l8, and preferably also any score or winning obtained.
At the beginning of the game the player should preferably insert several coins 35 into the coin checker 13. The coin checker can be of a conventional construction (see for example the German Pat. No. 2,029,751) and on accepting a coin passes an electrical pulse to the coin gate which is normally comprised in a coin checker so that the accepted coin passes through a receiving channel 41 (FIG. 6) into the coin store 29, which can consist for example of a vertically placed tube. The pulse produced on acceptance is also supplied to a forward count input VZ of a reversible counter 43 contained in the credit balance memory 14 and the counter 43 is provided with an indicating device 45, which indicates the credit balance. The credit balance unit 14 furthermore comprises a decoder connected with the counter 43 which supplies an output signal at an output line 49 when the counter 43 is at zero. The line 49 leads to an inverter 51, at whose output, therefore, a credit balance signal GU is produced when the counter 43 stores a credit balance different from zero.
After the insertion of one or more coins the player then actuates the starting button 37 (FIG. 5) which cuases a monostable multivibrator (referred to below as "monoflop") 53 which on actuation supplies a pulse of predetermined length at one of two inputs of an AND- gate 55. At the second input of the AND-gate the credit balance signal GU is present and, since it was assumed that the credit balance differed from zero, the pulse from the monofiop 53 can pass through the AND-gate 55. The output pulse of the AND-gate serves as a resetting pulse RS, which resets the card memory and the score determining circuit with the associated indicating means at zero. The output pulse RS furthermore passes through a delay member 57 and an OR-gate 59 and then passes to the setting input of the flip-flop 61, which is accordingly set. When the flip-flop 61 has been set, there appears at its l-output a dealing command signal AB, which is supplied to an AND-gate 63 (FIG. 3) in the dealing unit 19. The AND-gate 63 has two further inputs, of which one receives clock pulses (with the frequency of for example 10 kHz) from an oscillator 65, while at the third input a dealing termination signal is present, which vanishes when five cards have been dealt. The production of the dealing termination signal will be described presently in conjunction with FIG. 2.
At the point in time in consideration all three input signals are present at the AND-gate 63 so that the clock pulses are allowed to pass through and can pass on the one hand to a random signal generator 69 and on the other hand to a five stage counter 67.
The five stages of the counter each have a respective l-output and a O-output. At the l-output the signal L (binary number 1) occurs when the stage is set, while when the stage is reset an L" occurs at the 0-output".
The random signal generator 69 consists of a conventional circuit arrangement, for example a shift register provided with feed-back loops, which supplies a quasistatistical binary sign sequence with a very large cycle duration (see for example Gernam Pat. Nos. 1,188,123, 1,054,491 and 1,095,876). The quasistatistical sign sequence produced by the random signal generator 69 is supplied to frequency divider 71, which reduces the frequency of the quasi-statistical pulse sequence to such a degree that the dealing" of the cards can be carried out with a sufficiently low speed in order to be observed. The quasi-statistical pulse sequence divided as to frequency is shaped in a pulse-shaping and delay circuit 73 and brought into such a phase position with respect to the clock pulses TP fed to the counter 67 that the respective quasi-statistical pulses only occur after the counter 67 has terminated the switching over operation which was initiated by the corresponding clock pulse TP. The quasi-statistical pulses (referred to in what follows as random pulses) Z are supplied from the output of the pulse-shaping and delay circuit 73 to a respective input of 32 AND-gates, which are arranged so as to correspond to a respective stage of the card memory (FIG. 2). FIGS. 2 and 3 show only one such respective AND-gate 75, which is associated with the memory stage for the card T7 (seven of clubs). THe AND-gates each have 8 inputs, of which five are connected with corresponding outputs of the stages of the counter 67, as is indicated in the table contained in FIG. 3. The relevant five inputs of the AND-gate 75 of a first memory stage (that is to say in this case the memory stage T7) are connected therefore with the 1- output of the counter-stage l and with the O-outputs of the counter-stages 2 to 5. At the relevant five inputs of the AND-gate 75 signals only of the value L are present when the counter 67 is at (decimal) 1. On switching on the counter 67 further by the clock pulses CP therefore the five inputs of the 32 AND-gates 75 are switched first into the enabled condition.
The remaining inputs of the AND-gate 75 are connected with the O-outputs of two flip-flops FFla and FFlb (FIG. 2) which together form the memory stage T7. The card memory comprises 32 memory stages, which are arranged in four lines and eight columns, as shown in the following table and which respectively comprise two flip-flops corresponding to the flip-flops FFla and FF).
Table l-Continued Column 7 2 3 4 5 6 7 8 It is therefore a question of abbreviations of the designations of a pack of 32 cards.
Since the 32 memory stages of the card memory 15 are identical in construction, it is sufficient to explain the memory stage T7.
The setting input 8 of the flip-flop FFla is connected with the output of the associated AND-gate 75. The flip-flop FFla is thus set if 1 the counter 67 is at the number coordinated with the relevant memory stage,
2 a random pulse Z occurs, and
3 both flip-flops of the respective memory stage are reset.
Owing to the setting of the flip-flop la the signal L occurs at its l-output, while the signal at the O-output becomes zero and the AND-member is in the blocking condition. The signal from the l-output of the flipflop FFla firstly switches an indicating device 79, for example an incandescent lamp of the corresponding field 18 of the indicatinig unit 17, which then indicates that the card in question has been dealt. Furthermore, the signal passes from the l-output of the flip-flop 1a to one of 32 inputs of an OR-gate 81, whose output is connected with the forward counting input VZ ofa reversible counter 83. The counter 83 can count to 5 and then always switches on one step it counts, one each time one of the first flip-flops of a memory stage is set (that is to say one of the flip-flops corresponding to the flip-flop FFla).
In the above-mentioned manner in sequence five random cards are dealt" from the store or magazine of 32 cards in a statistical sequence in accordance with the random pulses Z one after the other. When the five cards have been dealt, that is to say when the first flipflops of five memory stages have been set, the counter 83 is at 5. The counter 83 is connected with a decoder 85, which in the case of the counter condition 5 provides a signal 5k (five cards), which passes via an OR-gate 87 to the set input of the flip-flop 77 and sets the latter. When the flip-flop 77 has been set, the signal AS vanishes and the card dealing is terminated by blocking of the AND-gate 63.
The signal AS can control an indicating means in a manner which is not shown. The indicating means informs the player that he can return three of the dealt five cards and buy new cards in exchange. For this he is allowed a certain period of time, which in the case of the present example amounts to 20 seconds. If within 20 seconds the player does not return any card, the reading out of the result is started, as will be described presently.
In the present case it is, however, assumed for the present time that the player desires to return cards. The return of cards assumes that at least a credit balance of one coin unit is contained or stored in the credit balance memory.
Card return is carried out by actuating card return ittons 91 in the card return unit 21 (bottom of FIG. The card return buttons 91 respectively drive or )ntrol a single-pole reversing switch 93, which are so )nnected in series in the manner shown in FIG. 2 that simultaneous return of two cards is impossible. By aclation of the return card switch 93 associated with the 1rd which is to be returned (for example T7) the :ttng operation S of the second flip-flop of the releint memory stage, that is to say of the flip-flop 1b of ie memory stage T7, a card return signal KRS is sup lied, which sets the relevant second flip-flop. If therere the reversing switch 93 associated with the memreset state (due to the 2K signal from decoder 85), the clock pulses TP from the oscillator 65 are allowed to pass by the AND-gate 63 and the above-described dealing operation begins again. When again the number of cards dealt equals the number which has been returned, that is to say when in all five cards have been dealt, the flip-flop 77 is set by the signal 5K again and the dealing operation is again terminated.
The determination of the score by means of the score determining circuit shown in FIGS 4a to 4f can now begin.
The determination of the score is carried out on the basis of the criteria given in the following table:
Threc Number of the Poker Num' her of Sequ hlfld in in l ucc Z of columns encc column column ices lines Threc of the kind no yes no i Full House 2 no )Bs no Flush 5 no no no l Poker 2 no yes es no Ace Poker 2 no yes yes yes Straight Flush 5 yes no no no l Royal Flush 5 yes no no yes i l ry stage T7, is actuated, the flip-flop lb is set and at s l-output a signal ocurs, which via an OR-gate 95 asses to the resetting input R of the first flip-flop FFla f the corresponding stage and resets this flip-flop. Acordingly the indicating device 79 in the indicating unit ecomes dark. Owing to the setting of the flip-flop 'Flb the signal L now vanishes at its -output and the ssociated AND-gate 75 can therefore still not allow he passage of any pulse for setting the first flip-flop Fla, if the relevant memory stage is selected by the ounter 67 and simultaneously a random pulse Z is pro- IUCfid during the new deal stage of operation which folows.
The lines (for example line 97) leading from the reersing switches 93 to the setting inputs S of the second lip-flops of the memory stages are connected with the nputs of an OR-gate 99, which for each returned card upplies an output pulse. This putput pulse is supplied ifter shaping by a pulse shaping circuit 101 to the reerse count input of the counter 83 as a reverse count .ignal RZS. The counter 83 therefore makes one backyard count for each returned card amounting to one .tep. The return of more than three cards is prevented iy the fact that the decoder 85 supplies a signal 2K two cards") in the case of the count 2 and this signal ,witches off the card return signal KRS from the card 'eturn unit 21. The signal KRS is produced by the cir- :uit shown in FIG. 5.
After card return the player actuates the new deal )utton 39 (FIG. which sets a flip-flop 103. The sigial occurring at the l-output of the flip-flop when the atter is set is differentiated in a differentiating circuit l05 and supplied via the OR-gate 59 to the setting nput of the flip-flop 61, which has previously been eset by the signal 5K. Owing to the setting of the flip- 1op 61 the dealing command signal AB again occurs and since furthermore the flip-flop 77 is again in the For determining the number of lines and the presence of a sequence (five sequentially following values) use is made of the circuit arrangement shown in FIG. 4a. It comprises an ANDgate 105 at whose output the signal NAS from the l-output of the flip-flop 103 the signal 514 of the decoder and the clock pulses TP of the oscillator 65 are present. The clock pulses are therefore only allowed to pass when the flip-flop 103 is set and five cards have been dealt.
The clock pulses allowed to pass by the AND-gate 105 are passed to the setting input of a flip-flop 107, which is set by the first clock pulse allowed to pass. The leading edge of the pulse occurring at its l-output triggers a monostable multivibrator 108 or monoflop, which supplies a memory signal to all eight stages of an eight-stage shift register 109. The inputs of the eight stages of the shift register 109 are respectively connected with the output of an OR-gate 111a to 11112. The inputs of each OR-gate are coupled with the loutputs of the first flip-flops of the memory stages of a column (see table 1). The input, denoted T7, of the OR-gate 111a is thus connected with the l-output of the flip-flop FFla (FIG. 2). At the output of the OR- gate 111a a column signal SP1 therefore occurs when a card which has been dealt is found in the first column (see table 1), that is to say when a seven has been dealt. The same applies for the other OR-gates, that is to say the column signal SP8 thus occurs when an ace has been dealt.
The column signals SP1 to SP8 are stored by the memory signal produced by the monoflop 108, in parallel in the eight stages of the shift register 109.
The clock pulses from the output of the AND-gate 105 are furthermore supplied via a delay member 113 to shift inputs of the eight stages of the shift register 109. The delay member is so dimensioned that the first clock pulse only occurs at the shift inputs when the storing operation of the column signals SP1 to SP8 is terminated. The clock pulses then shift the content of the shift register into a counter 115, which can count to and is provided with a decoder 117, which has three outputs, at which a respective signal 28, 3S and 58 occurs when the cards dealt are in two, three and five columns respectively.
The column signals SP1, SP2, SP3, SP6, SP7 and SP8 are futhermore inverted by an inverter 119 and supplied in groups of three to the four NAND-gates 121 to 124 shown in FIG. 4a and these gates then only all supply an output signal L to an AND-gate 125, if the unoccupied columns are so distributed that a sequence is possible. The AND-gate 125 has furthermore the signal 58 supplied to it as a fifth input signal; it therefore only supplies a sequence signal SQ when a sequence (independent of the suit of the cards), is present.
The circuit arrangement shown in FIG. 4b serves for determining poker, that is to say four cards of the same value (corresponding to a full column). The output signals of the first flip-flop of the memory stages are supplied respectively in accordance with the columns to eight AND-gates 127a to 127h. The AND-gate 127a therefore only supplies a signal VSl (column 1 full), when all four sevens have been dealt. The outputs of the AND-gates 127a to I27): are connected with corresponding outputs of an OR-gate 129, at whose output a poker signal PS only occurs when a full column is present.
The circuit shown in FIG. 4C consists of an AND- gate 131 and supplies a signal 2A (two aces signal) when the ace of clubs and the ace of spades have been dealt. The inputs of the AND-gate 131 could be connected with any two ace memory stages, since the circuit in accordance with FIG. 4c only serves for determining the ace poker.
The circuit in accordance with FIG. 4d serves for determining whether the cards dealt are distributed in one or more lines. This circuit supplies a signal 1 ZS (1 line) only when all cards dealt are to be found in a single line. The circuit in accordance with FIG. 4d comprises for each line of the memory stage matrix (see table I) an OR-gate with eight inputs, of which only the upper gate 133 for the first line is shown. The inputs of the OR-gate 133 have the signals of the l output of the first flip-flop of all memory stages of the first line supplied to them. A line signal Z1 is always supplied when the first line (clubs) comprises a dealt card. For the other OR-gates which are not shown much the same applies.
The line signals Z1 to Z4 are supplied to corresponding inputs of a threshold gate 135, which supplies an output signal when two or more line signals are present at its outputs. The output signal of the threshold gate .135 is inverted by an inverter 137. At the output of the inverter 137 a signal of the value L is therefore only present when all drawn cards are located in a single line.
The circuit in accordance with FIG. 42 serves for determining whether three of a kind have been dealt. In this case the four signals of each column in groups of three are supplied to three respective AND-gates I39, I40, 141, as is shown in FIG. 4e. The outputs of the AND-members 139 to 141 are connected with the inputs of an OR-gate 143, which always supplies a signal D1 (three of a kind in column 1) when the first column comprises a three of a kind, that is to say when three sevens have been drawn.
For each of the eight columns a circuit in accordance with the ANDgates 139 to 141 and the OR-gate 143 is provided. These circuits are, however, only hinted at in FIG. 4e. There are therefore in all eight OR-gates which are connected in accordance with the 0R-gate 143 and these OR-gates supply signals D1 to D8. The signals D1 to D8 are supplied to the eight inputs of an OR-gate 145, at whose output a three of a kind signal DR occurs when a three of a kind hand is to be found in any column.
The evaluation of the score criteria signals produced in the above-described manner is carried out by means of the circuit shown in FIG. 4f, which consists of inverters and AND-gates. The construction and the manner of operation of these circuits is obvious, and they supply the following score signals:
GDR Three of a Kind winning score GFH Full House winning score GFL Flush Winning score GPI-I Poker winning score (single) GAP Ace poker winning score GSF Straight Flush winning score GRF Royal Flush winning score The winning scores can be indicated.
Preferably, however, besides or instead of the indication there is a winning score payment or winning score credit in the credit balance memory 14. For this purpose the score signals can be respectively supplied for example to a coder 147 (FIG. 6), which comprises a counter 149 with respect to a number corresponding to the win quota. The count of the counter is then transferred into the counter 43 of the credit balance unit 14, as is indicated by the connection xx. In the case of very large winning scores there is preferably no payment or crediting but instead an optical or acoustic indication is provided by means of an alarm device 151 (FIG. 4f), since very large sums are difficult to pay out using coin.
In the case of the present gaming machine the player can cause his credit balance registered in the counter 43 to be paid out completely or partly at any time. For this purpose he actuates a paying out button 153, by means of which a circuit 155 is closed and a voltage U is supplied to an input of the AND-gate 157. At the other input of the AND-gate the credit balance signal GU is present. When a credit balance is present, the voltage U passes to a paying out device 159, which for example can comprise a reciprocating slight 161, which ejects the coins 35 stored in the coin stored 29 one after the other into a delivery pan. The ejected coins are detected by a photoelectric light beam device and pulses produced as a result pass through a pulse shaping circuit 167 and an OR-gate 169 to the reverse count input of the counter 43. Therefore for each coin delivered the counter 43 is set back by one step. When the count reaches zero, the credit balance signal GU vanishes and the AND-gate 157 blocks and further delivery of coins is thus prevented.
The delayed signal from the output of the delay member 113 is supplied to a further delay member 170, which delivers a end of game reset signal RSS for the resetting circuit units of the gaming machine (with the exception of the card memory and the score indication means, which on resetting of the counter 115 is put out by the signal RS). The duration of the delay is so selected that the above-described determination of the winning score is terminated before the signal RSS occurs.
If the player does not return any cards, the win or score is determined after the expiry of seconds, after the card return signal KRS (FIG. 5) has disappeared. The signal KRS is then supplied for this purpose via an inverter 172 and an OR-gate 174 to the AND-gate 105 and starts the same operation as after card return by the NAS-signal (which is supplied via the second input of the OR-gate 175 to the AND-gate 105).
We claim:
1. An electronically controlled gaming machine adapted to play card games with poker-like rules of play, comprising:
an indicating unit having a plurality of selectively operable card-representing indicator devices, one for each card of a group of possible cards;
a card memory having a plurality of memory stages one for each indicator device, each card memory stage having an input thereto and an output connected to the associated indicator device, and being operable to assume one of three memory conditions, a reception condition, a memory condition, and a blocking condition, each said memory stage operating to produce an output signal when in said memory condition and no output signal when in said reception condition or said blocking condition, and switching to said memory condition on the occurrence of a signal on said input if it is in said reception condition but not if it is in said blocking condition,
a dealing unit having a plurality of outputs each connected to the inputs of a respective card memory stage, said dealing unit comprising in combination; a random signal generator, means connecting said random signal generator to all said outputs from said dealing unit,
means for cyclically enabling said outputs from said dealing unit whereby an output signal on one of said output lines is produced if a random signal occurs when said one of said output lines is enabled, said output signal operating to switch the card memory stage connected to said one of said output lines to its memory condition if it is in its reception condition,
a counter circuit connected to the outputs of all said memory stages and operable to produce an output pulse when a predetermined number of memory stages have been switched to their memory conditions, and
means interconnecting said counter and said random signal generator to inhibit the generation of further random signals upon the occurrence of said output signal from said counter indicating that said predetermined number of memory stages have been switched to their memory condition to represent the dealing of a predetermined number of cards, a card return unit having,
a plurality of operating members each connected to a respective memory stage and operating, when actuated, to switch the associated memory stage to its blocking condition from its memory condition, and
a new deal operating member connected to said dealing unit and operable to energise said dealing unit, when actuated, to randomly switch further memory stages to their said memory conditions until the said predetermined number of memory stages in the memory condition is re-established,
a stake unit having a coin or token receiving mechanism and means for producing an output signal when coins or tokens are held in said stake unit,
inhibit means interconnecting the output of said stake unit and said dealing unit, operating to inhibit said dealing unit unless there is an output signal from said stake unit, and
result read-out means connected to said memory stages and operating to indicate the score obtained in dependence on which of said memory stages are in said memory condition.
2. The gaming machine of claim 1, wherein said dealing unit includes a plurality of multiple input AND gates the outputs from which constitute the outputs of said dealing unit and are connected to the inputs of corresponding card memory stages, and wherein each said card memory stage comprises first and second bistable circuits each having set and reset inputs and set and reset outputs, the set input of said first bistable circuit being connected to said dealing unit and the set input of said second bistable circuit being connected to a corresponding operating member of said card return unit, said set output of said first bistable circuit being connected to the corresponding indicating device, said reset outputs of both said first and said second bistable circuits being connected to respective inputs of the corresponding multiple input AND gate, whereby said memory stage is in said reception condition when both said bistable circuits are in their reset state, in said memory condition when said first bistable circuit is in its set state and said second bistable circuit is in its reset state, and in its blocking condition when said first bistable circuit is in its reset state and said second bistable circuit is in its set state.
3. The gaming machine of claim 2, wherein said means for cyclically enabling said outputs of said deal ing unit comprise:
an oscillator producing a train of output pulses,
a counter having a serial input connected to the output from said oscillator, said counter having a plurality of parallel binary outputs on which appear, in binary form, signals representing the number of pulses counted by said counter,
means interconnecting said parallel outputs of said counter and some of the inputs of each of said multiple input AND gates the remaining input of said multiple input AND gates being connected to said random signal generator whereby, when said first and second bistable circuits of the corresponding card memory stages are both in a reset state said multiple input AND gates are enabled by said counter when it has counted at corresponding number of pulses from said oscillator circuit.
4. The gaming machine of claim 2, wherein said dealing means additionally comprises a reversible counter having a forward input and a reverse input, and an output connected to a first decoder circuit having two outputs, one energised on a forward count of five signals and the other energised on a forward count of two signals,
means interconnecting the set output of the first bistable circuit of each said memory stage of said card memory to said forward input of said reversible counter, and
means interconnecting said one output of said first decoder circuit with said inhibit means whereby said dealing unit is stopped after five memory stages have been switched to their memory condition, representing five cards dealt.
5. The gaming machine of claim 1 wherein said inhibit means includes a third bistable circuit having set and reset inputs and set and reset outputs, means connecting said set input to said one output of said first decoding circuit, means connecting said reset input to said other output from said decoding circuit, and
an AND gate having one input connected to said oscillator and an output connected to said counter, another input of said AND gate being connected to said reset output of said third bistable circuit whereby said AND gate is enabled when said third bistable circuit is in its reset state, and disabled when said third bistable circuit is switched to its set state upon the occurrence of an output signal on the said one output of said decoder circuit.
6. The gaming machine of claim 1 wherein said operating members of said card return unit each comprise a single pole reversing switch for each memory stage, resilient biasing means biasing each reversing switch to one position, all said reversing switches being connected in series in a line when in said one position, and
means applying a card return signal to the movable contact of the reversing switch at one end of said line of switches for a predetermined time after the dealing unit has stopped.
7. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has a flush determining circuit comprising in combination a column member determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2,3 or 5 stages of said shift register in a binary 1 condition,
a sequence determining circuitcomprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix,
four first NAND gates each having three inputs, the
outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a se quence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and
a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third output of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns,
a line number determining circuit operating to produce an output signal when all the memory stages of said matrix in said memory condition are disposed in a single line, said circuit comprising eight second OR gates each having eight inputs connected to the outputs of respective memory stages in a corresponding line,
threshold circuit having eight inputs connected to the outputs of the eight second OR circuits and operating to produce an output signal if there is a signal on two or more inputs thereof, and
a second invertor circuit connected to the output of said threshold circuit, the output of said second invertor circuit producing an output signal only when a signal is present on one input only of said threshold circuit,
a third invertor circuit connected to the output of said first AND gate,
a fourth invertor circuit connected to the output of said second invertor circuit, and
a second AND gate having three inputs respectively connected to the outputs of said second and third invertor circuits and said third output of said second decoder circuit.
8. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has a straight flush determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the ouputs of the memory stages of a corresponding cloumn,
an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary l state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a mamory condition, means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
a sequence determining circuit comprising six first invertor circuits, three of which are connected to the ouputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix,
four first NAND gates each having three inputs, the
outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and
a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third ouput of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns,
a fifth invertor circuit connected to the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces, and
a third AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first ANd gate and the output of said fifth invertor circuit.
9. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has a royal flush determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix,
four first NAND gates each having three inputs, the
outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and
a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third output of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, and
a fourth AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first AND gate and the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces.
10. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has a poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stges in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit. said second decoder having first, second and third outputs respectively, energ ised an a output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or stages of said shift register in a binary 1 condition,
eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and
a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition,
a sixth AND gate having two inputs connected to the outputs of two of the memory stages in the column of said memory matrix representing aces,
a sixth invertor connected to the output of said sixth AND gate, and
a seventh AND gate having two inputs respectively connected to the outputs of said sixth invertor circuit and said second OR gate, said seventh AND gate producing an output signal representing poker.
11. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has an ace poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and
a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition,
a sixth AND gate having two inputs connected to the outputs of two of the memory stages in the column representing aces, and
an eighth AND gate having two inputs connected respectively to the output of said sixth AND gate and to the output of said second OR gate and producing an output signal representing ace poker.
12. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result readout unit has a full house determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column,
an eight stage shift register having a serial input a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and
a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a seventh invertor circuit connected to the output of said third OR gate,
eight groups of three ninth AND gates each having three inputs, the inputs of each group being connected to the memory stages of a corresponding column whereby an output signal from one of said ninth AND gates of a group is produced if any three of said memory stages in said corresponding column are in said memory condition,
a group of eight fourth OR gates connected to the outputs or respective groups of said ninth AND gates,
a fifth OR gate connected to the outputs of said fourth OR gates, and
a tenth AND gate having three inputs respectively connected to the outputs of said seventh inverter circuit, the output of said fourth OR gate and the first output of said decoder circuit, said tenth AND gate producing an output signal representing full house.
13. The gaming machine of claim 1 wherein the nemory stages of said card memory are arranged in a natrix of lines and columns, said lines corresponding to :he suits, and said columns corresponding to the card lalues in sequential order, and wherein said result read- )ut unit has a three-of-a-kind determining circuit com- )rising in combination a column number determining :ircuit including eight first OR gates each having four nputs, the inputs of each said first OR gate being coniected to the outputs of the memory stages ofa corre- ;ponding column,
an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of said shift register,
a counter connected to said serial output of said shift register, and
a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition,
eight groups of three ninth AND gates each having three inputs, the inputs of each group being connected to the memory stages of a corresponding column whereby an output signal from one of said ninth AND gates of a group is produced if any three of said memory stages in said corresponding column are in said memory condition,
a group of eight fourth OR gates connected to the outputs of respective groups of said ninth AND gates,
a fifth OR gate connected to the outputs of said fourth OR gates, and
an eleventh AND gate having two inputs respectively connected to said second output of said second decoder circuit and the output of said fifth OR gate.
14. The gaming machine of claim 1 wherein said stake unit comprises,
a coin or token checking device having an output which is energised upon insertion of a valid coin or token into said coin or token checking device,
a coin or token payout device,
a credit meter having a reversible counter and an indicator showing the count in the counter, said counter having a forward input connected to the output of said coin or token checking device and a backward input connected to said coin or token payout device and to said card return unit,
a decoder circuit having an output which is energised when the count in said counter is zero, and
a payout inhibit device connected to said output of said decoder and operating to inhibit payout when the count in said counter is zero.

Claims (14)

1. An electronically controlled gaming machine adapted to play card games with poker-like rules of play, comprising: an indicating unit having a plurality of selectively operable cardrepresenting indicator devices, one for each card of a group of possible cards; a card memory having a plurality of memory stages one for each indicator device, each card memory stage having an input thereto and an output connected to the associated indicator device, and being operable to assume one of three memory conditions, a reception condition, a memory condition, and a blocking condition, each said memory stage operating to produce an output signal when in said memory condition and no output signal when in said reception condition or said blocking condition, and switching to said memory condition on the occurrence of a signal on said input if it is in said reception condition but not if it is in said blocking condition, a dealing unit having a plurality of outputs each connected to the inputs of a respective card memory stage, said dealing unit comprising in combination; a random signal generator, means connecting said random signal generator to all said outputs from said dealing unit, means for cyclically enabling said outputs from said dealing unit whereby an output signal on one of said output lines is produced if a random signal occurs when said one of said output lines is enabled, said output signal operating to switch the card memory stage connected to said one of said output lines to its memory condition if it is in its reception condition, a counter circuit connected to the outputs of all said memory stages and operable to produce an output pulse when a predetermined number of memory stages have been switched to their memory conditions, and means interconnecting said counter and said random signal generator to inhibit the generation of further random signals upon the occurrence of said output signal from said counter indicating that said predetermined number of memory stages have been switched to their memory condition to represent the dealing of a predetermined number of cards, a card return unit having, a plurality of operating members each connected to a respective memory stage and operating, when actuated, to switch the associated memory stage to its blocking condition from its memory condition, and a new deal operating member connected to said dealing unit and operable to energise said dealing unit, when actuated, to randomly switch further memory stages to their said memory conditions until the said predetermined number of memory stages in the memory condition is re-established, a stake unit having a coin or token receiving mechanism and means for producing an output signal when coins or tokens are held in said stake unit, inhibit means interconnecting the output of said stake unit and said dealing unit, operating to inhibit said dealing unit unless there is an output signal from said stake unit, and result read-out means connected to said memory stages and operating to indicate the score obtained in dependence on which of said memory stages are in said memory condition.
2. The gaming machine of claim 1, wherein said dealing unit includes a plurality of multiple input AND gates the outputs from which constitute the outputs of said dealing unit and are connected to the inputs of corresponding card memory stages, and wherein each said card memory stage comprises first and second bistable circuits each having set and reset inputs and set and reset outputs, the set input of said first bistable circuit being connected to said dealing unit and the set input of said second bistable circuit being connected to a corresponding operating member of said card return unit, said set output of said first bistable circuit being connected to the corresponding indicating device, said reset outputs of both said first and said second bistable circuits being connected to respective inputs of the corresponding multiple input AND gate, whereby said memory stage is in said reception condition when both said bistable circuits are in their reset state, in said memory condition when said first bistable circuit is in its set state and said second bistable circuit is in its reset state, and in its blocking condition when said first bistable circuit is in its reset state and said second bistable circuit is in its set state.
3. The gaming machine of claim 2, wherein said means for cyclically enabling said outputs of said dealing unit comprise: an oscillator producing a train of output pulses, a counter having a serial input connected to the output from said oscillator, said counter having a plurality of parallel binary outputs on which appear, in binary form, signals representing the number of pulses counted by said counter, means interconnecting said parallel outputs of said counter and some of the inputs of each of said multiple input AND gates the remaining input of said multiple input AND gates being connected to said random signal generator whereby, when said first and second bistable circuits of the corresponding card memory stages are both in a reset state said multiple input AND gates are enabled by said counter when it has counted a corresponding number of pulses from said oscillator circuit.
4. The gaming machine of claim 2, wherein said dealing means additionally comprises a reversible counter having a forward input and a reverse input, and an output connected to a first decoder circuit having two outputs, one energised on a forward count of five signals and the other energised on a forward count of two signals, means interconnecting the set output of the first bistable circuit of each said memory stage of said card memory to said forward input of said reversible counter, and means interconnecting said one output of said first decoder circuit with said inhibit means whereby said dealing unit is stopped after five memory stages have been switched to their memory condition, representing five cards dealt.
5. The gaming machine of claim 1 wherein said inhibit means includes a third bistable circuit having set and reset inputs and set and reset outputs, means connecting said set input to said one output of said first decoding circuit, means connecting said reset input to said other output from said decoding circuit, and an AND gate having one input connected to said oscillator and an output connected to said counter, another input of said AND gate being connected to said reset output of said third bistable circuit whereby said AND gate is enabled when said third bistable circuit is in its reset state, and disabled when said third bistable circuit is switched to its set state upon the occurrence of an output signal on the said one output of said decoder circuit.
6. The gaming machine of claim 1 wherein said operating members of said card return unit each comprise a single pole reversing switch for each memory stage, resilient biasing means biasing each reversing switch to one position, all said reversing switches being connected in series in a line when in said one position, and means applying a card return signal to the movable contact of the reversing switch at one end of said line of switches for a predetermined time after the dealing unit has stopped.
7. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a flush determining circuit comprising in combination a column member determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2,3 or 5 stages of said shift register in a binary 1 condition, a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix, four first NAND gates each having three inputs, the outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third output of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, a line number determining circuit operating to produce an output signal when all the memory stages of said matrix in said memory condition are disposed in a single line, said circuit comprising eight second OR gates each having eight inputs connected to the outputs of respective memory stages in a corresponding line, a threshold circuit having eight inputs connected to the outputs of the eight second OR circuits and operating to produce an output signal if there is a signal on two or more inputs thereof, and a second invertor circuit connected to the output of said threshold circuit, the output of said second invertor circuit producing an output signal only when a signal is present on one input only of said threshold circuit, a third invertor circuit connected to the output of said first AND gate, a fourth invertor circuit connected to the output of said second invertor circuit, and a second AND gate having three inputs respectively connected to the outputs of said second and third invertor circuits and said third output of said second decoder circuit.
8. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a straight flush determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the ouputs of the memory stages of a corresponding cloumn, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a mamory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, a sequence determining circuit comprising six first invertor circuits, three of which are connected to the ouputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix, four first NAND gates each having three inputs, the outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third ouput of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, a fifth invertor circuit connected to the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces, and a third AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first ANd gate and the output of said fifth invertor circuit.
9. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a royal flush determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, a sequence determining circuit comprising six first invertor circuits, three of which are connected to the outputs of the three first OR gates connected to the three columns at a first end of said memory stage matrix and three of which are connected to the three first OR gates connected to the three columns at a second end of said memory stage matrix, four first NAND gates each having three inputs, the outputs of said first invertor circuits being connected in different groups of three to said inputs of said first NAND gates whereby each NAND gate produces an output signal if the corresponding columns of said memory stage matrix having no memory stage in said memory condition leave five remaining columns in which it is possible for memory stages to be in said memory condition to form a sequence of five, and no signal if the distribution of columns having no memory stage in said memory condition is such that no sequence of five different adjacent columns can have memory stages in said memory condition, and a first AND gate having five inputs, four of said inputs being connected to the outputs of said first NAND gates and the fifth being connected to said third output of said second decoder circuit whereby said first AND gate produces an output signal when said memory stages of said matrix in said memory condition all lie in five different adjacent columns, and a fourth AND gate having three inputs respectively connected to said third output of said second decoder circuit, said output of said first AND gate and the output of that one of said first OR gates the inputs of which are connected to the column of said matrix of memory stages representing aces.
10. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stges in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively, energised an a output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a sixth AND gate having two inputs connected to the outputs of two of the memory stages in the column of said memory matrix representing aces, a sixth invertor connected to the output of said sixth AND gate, and a seventh AND gate having two inputs respectively connected to the outputs of said sixth invertor circuit and said second OR gate, said seventh AND gate producing an output signal representing poker.
11. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has an ace poker determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first, second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a sixth AND gate having two inputs connected to the outputs of two of the memory stages in the column representing aces, and an eighth AND gate having two inputs connected respectively to the output of said sixth AND gate and to the output of said second OR gate and producing an output signal representing ace poker.
12. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a full house determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight fifth AND gates each having four inputs connected to the outputs of respective memory stages in corresponding columns of said matrix whereby a fifth AND gate produces an output signal if all said memory stages in the corresponding column are in said memory condition, and a third OR gate having eight inputs connected to the outputs of said eight fifth AND gates, said third OR gate producing an output signal when all the memory stages of any column of said matrix are all in said memory condition, a seventh invertor circuit connected to the output of said third OR gate, eight groups of three ninth AND gates each having three inputs, the inputs of each group being connected to the memory stages of a corresponding column whereby an output signal from one of said ninth AND gates of a group is produced if any three of said memory stages in said corresponding column are in said memory condition, a group of eight fourth OR gates connected to the outputs or respective groups of said ninth AND gates, a fifth OR gate connected to the outputs of said fourth OR gates, and a tenth AND gate having three inputs respectively connected to the outputs of said seventh inverter circuit, the output of said fourth OR gate and the first output of said decoder circuit, said tenth AND gate producing an output signal representing full house.
13. The gaming machine of claim 1 wherein the memory stages of said card memory are arranged in a matrix of lines and columns, said lines corresponding to the suits, and said columns corresponding to the card values in sequential order, and wherein said result read-out unit has a three-of-a-kind determining circuit comprising in combination a column number determining circuit including eight first OR gates each having four inputs, the inputs of each said first OR gate being connected to the outputs of the memory stages of a corresponding column, an eight stage shift register having a serial input, a serial output, and a parallel input to each stage, said parallel inputs being connected to the output of a corresponding first OR gate whereby a stage is switched to a binary 1 state by an output from the corresponding first OR gate indicating that one of said memory stages in the associated column is in a memory condition, means for providing a train of clock pulses to the serial input of said shift register, a counter connected to said serial output of said shift register, and a second decoder circuit connected to the output of said counter circuit, said second decoder having first second and third outputs respectively energised with an output signal, when said counter has counted the contents of said shift register, if said counter output indicates 2, 3 or 5 stages of said shift register in a binary 1 condition, eight groups of three ninth AND gates each having three inputs, the inputs of each group being connected to the memory stages of a corresponding column whereby an output signal from one of said ninth AND gates of a group is produced if any three of said memory stages in said corresponding column are in said memory condition, a group of eight fourth OR gates connected to the outputs of respective groups of said ninth AND gates, a fifth OR gate connected to the outputs of said fourth OR gates, and an eleventh AND gate having two inputs respectively connected to said second output of said second decoder circuit and the output of said fifth OR gate.
14. The gaming machine of claim 1 wherein said stake unit comprises, a coin or token checking device having an output which is energised upon insertion of a valid coin or token into said coin or token checking device, a coin or token payout device, a credit meter having a reversible counter and an indicator showing the count in the counter, said counter having a forward input connected to the output of said coin or token checking device and a backward input connected to said coin or token payout device and to said card return unit, a decoder circuit having an output which is energised when the count in said counter is zero, and a payout inhibit device connected to said output of said decoder and operating to inhibit payout when the count in said counter is zero.
US399333A 1972-09-20 1973-09-20 Gaming machine Expired - Lifetime US3876208A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19722245969 DE2245969C3 (en) 1972-09-20 Electronic slot machine with rules similar to poker

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US9329370A Continuation-In-Part 1970-11-27 1970-11-27

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US05/576,101 Continuation-In-Part US4036244A (en) 1973-05-08 1975-06-12 Vertical arch shelter
US05/597,970 Continuation-In-Part US4034772A (en) 1973-05-08 1975-07-21 Vaulted membrane shelter

Publications (1)

Publication Number Publication Date
US3876208A true US3876208A (en) 1975-04-08

Family

ID=5856770

Family Applications (1)

Application Number Title Priority Date Filing Date
US399333A Expired - Lifetime US3876208A (en) 1972-09-20 1973-09-20 Gaming machine

Country Status (2)

Country Link
US (1) US3876208A (en)
GB (1) GB1447550A (en)

Cited By (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052057A (en) * 1974-08-20 1977-10-04 Trevor William Castle Electronic amusement machine
US4072310A (en) * 1976-01-15 1978-02-07 Beam Dale R Control apparatus for a card game simulator
US4093215A (en) * 1976-06-04 1978-06-06 Ballard Chester P Chance operated simulated card game
US4095795A (en) * 1974-06-24 1978-06-20 Saxton James C Amusement apparatus and method
US4099722A (en) * 1975-07-30 1978-07-11 Centronics Data Computer Corp. Electronic slot machine
US4121830A (en) * 1977-08-29 1978-10-24 Random Electronic Games Co. Bingo computer apparatus and method
US4157829A (en) * 1975-01-28 1979-06-12 System Operations, Inc. Instant lottery game employing vending machines which are centrally controlled by computers
US4173342A (en) * 1977-04-29 1979-11-06 Corlieu Ferran Jeanne De Device for simulating a card game
US4206920A (en) * 1977-11-04 1980-06-10 Toll Karl D Multiple digit electronic game
US4238127A (en) * 1977-01-17 1980-12-09 Bally Manufacturing Corporation Electronic gaming apparatus
WO1980002804A1 (en) * 1979-06-20 1980-12-24 Bliss D Electronic control for rotatable reel gaming device
WO1981001664A1 (en) * 1979-12-17 1981-06-25 Remote Dynamics A remote gaming system
WO1981001895A1 (en) * 1979-12-31 1981-07-09 Mattel Inc Electronic card game simulator
US4339134A (en) * 1977-07-05 1982-07-13 Rockwell International Corporation Electronic card game
US4380334A (en) * 1980-03-24 1983-04-19 Mattel, Inc. Electronic card game simulator
US4467424A (en) * 1979-12-17 1984-08-21 Hedges Richard A Remote gaming system
EP0181158A2 (en) * 1984-11-02 1986-05-14 Kabushiki Kaisha Universal Slot machine
US4648604A (en) * 1985-04-29 1987-03-10 Professional Video Association, Inc. Elimination draw poker game
US4743022A (en) * 1986-03-06 1988-05-10 Wood Michael W 2nd chance poker method
US4760527A (en) * 1983-04-05 1988-07-26 Sidley Joseph D H System for interactively playing poker with a plurality of players
EP0333338A2 (en) * 1988-02-23 1989-09-20 James Phillips Mc Cann Improvements in and relating to video game machines
US4948134A (en) * 1988-04-18 1990-08-14 Caribbean Stud Enterprises, Inc. Electronic poker game
US5159549A (en) * 1984-06-01 1992-10-27 Poker Pot, Inc. Multiple player game data processing system with wager accounting
US5188363A (en) * 1991-12-30 1993-02-23 Rio Properties, Inc. Wheel of fortune poker game apparatus and method
US5364104A (en) * 1988-04-18 1994-11-15 D&D Gaming Patents, Inc. Apparatus for progressive jackpot gaming
US5364105A (en) * 1988-04-18 1994-11-15 D & D Gaming Patents, Inc. Method of progressive jackpot twenty-one
US5374067A (en) * 1988-04-18 1994-12-20 Jones; Daniel A. Method for playing a card game
US5377973A (en) * 1988-04-18 1995-01-03 D&D Gaming Patents, Inc. Methods and apparatus for playing casino card games including a progressive jackpot
US5382025A (en) * 1988-04-18 1995-01-17 D & D Gaming Patents, Inc. Method for playing a poker game
US5544893A (en) * 1988-04-18 1996-08-13 Progressive Games, Inc. Apparatus for progressive jackpot gaming
US5577731A (en) * 1995-07-24 1996-11-26 Progressive Games, Inc. Method of progressive jackpot twenty-one wherein the predetermined winning arrangement of cards include two aces, three aces and four aces
US5711715A (en) * 1995-10-11 1998-01-27 Ringo; Dock E. Method and apparatus for tournament play of coin operated games
US5725216A (en) * 1995-10-13 1998-03-10 Progressive Games, Inc. Methods of playing poker games
US5743798A (en) * 1996-09-30 1998-04-28 Progressive Games, Inc. Apparatus for playing a roulette game including a progressive jackpot
US5836818A (en) * 1988-04-18 1998-11-17 Progressive Games, Inc. Coin acceptor including multi-state visual indicator apparatus and method
US6019374A (en) * 1993-02-25 2000-02-01 Shuffle Master, Inc. Multi-tiered wagering method and game
US6082887A (en) * 1996-09-20 2000-07-04 Merit Industries, Inc. Game machine with automated tournament mode
US6273424B1 (en) 1993-02-25 2001-08-14 John G. Breeding Bet withdrawal casino game and apparatus
US6336859B2 (en) 1993-03-31 2002-01-08 Progressive Games, Inc. Method for progressive jackpot gaming
US6375189B1 (en) 1997-11-20 2002-04-23 Progressive Games, Inc. Methods for providing a jackpot component in a casino game in which an initial set of cards and additional cards are dealt
US6454266B1 (en) 1993-02-25 2002-09-24 Shuffle Master, Inc. Bet withdrawal casino game with wild symbol
US20030107174A1 (en) * 2001-12-11 2003-06-12 Loewenstein David Allen Poker game
US20030193141A1 (en) * 2002-02-22 2003-10-16 David Loewenstein Method and apparatus to play card game
US20040061288A1 (en) * 1993-02-25 2004-04-01 Shuffle Master, Inc. Method of playing a poker-type wagering game with multiple betting options
US6729620B2 (en) 1995-07-24 2004-05-04 Donald W. Jones Methods for providing a jackpot component in a casino game in which an initial set of cards and additional cards are dealt
US20040084843A1 (en) * 2002-10-31 2004-05-06 Shuffle Master, Inc. Wagering game with table bonus
US20040090003A1 (en) * 2002-11-12 2004-05-13 Shuffle Master, Inc. Wagering game with table bonus
US20050026665A1 (en) * 2003-07-31 2005-02-03 Peter Gerrard Apparatus and method for poker game with additional draw card options
US20050029744A1 (en) * 1995-07-19 2005-02-10 Shuffle Master, Inc. Bet withdrawal game with three card poker side bet
US20050040601A1 (en) * 1993-02-25 2005-02-24 Shuffle Master, Inc. Interactive simulated stud poker apparatus and method
US20050051963A1 (en) * 2003-09-09 2005-03-10 Shuffle Master, Inc. Casino card game with parlay bet feature
US20050127606A1 (en) * 1993-02-25 2005-06-16 Shuffle Master, Inc. High-low poker wagering games
US20050236774A1 (en) * 2002-02-22 2005-10-27 Loewenstein David A Card game with moving cards
US20060025191A1 (en) * 2004-08-02 2006-02-02 Shuffle Master, Inc. High-low poker wagering games
US20060066051A1 (en) * 2004-09-15 2006-03-30 Wagerworks, Inc. Casino card game
US20070060358A1 (en) * 2005-08-10 2007-03-15 Amaitis Lee M System and method for wireless gaming with location determination
US20070066402A1 (en) * 2004-02-25 2007-03-22 Cfph, Llc System and Method for Convenience Gaming
US20070093296A1 (en) * 2005-10-21 2007-04-26 Asher Joseph M System and method for wireless lottery
US20070257101A1 (en) * 2006-05-05 2007-11-08 Dean Alderucci Systems and methods for providing access to wireless gaming devices
US7300347B1 (en) 2003-08-26 2007-11-27 Creative Gaming Concepts, Inc. Wagering gaming and method of play
US20080026806A1 (en) * 2006-07-13 2008-01-31 Steven Terrance Gold Poker-type game and method
US20080207295A1 (en) * 1993-02-25 2008-08-28 Yoseloff Mark L Interactive simulated stud poker apparatus and method
US20080224402A1 (en) * 2007-03-14 2008-09-18 Shuffle Master, Inc. Bad beat side bet on house-banked casino card games
US20080224822A1 (en) * 2007-03-14 2008-09-18 Gelman Geoffrey M Game account access device
US20090075724A1 (en) * 1993-02-25 2009-03-19 Shuffle Master, Inc. Wireless bet withdrawal gaming system
US20090224478A1 (en) * 2008-03-10 2009-09-10 Igt Gaming system, gaming device and method for providing draw poker game
US20090279851A1 (en) * 2008-04-09 2009-11-12 Sony Corporation Captured image data management method and image capturing apparatus
US20090295091A1 (en) * 2002-05-20 2009-12-03 Abbott Eric L Poker games with player qualification
US7637810B2 (en) 2005-08-09 2009-12-29 Cfph, Llc System and method for wireless gaming system with alerts
US7644861B2 (en) 2006-04-18 2010-01-12 Bgc Partners, Inc. Systems and methods for providing access to wireless gaming devices
US20100016050A1 (en) * 2008-07-15 2010-01-21 Snow Roger M Chipless table split screen feature
US20100062845A1 (en) * 2008-09-05 2010-03-11 Wadds Nathan J Automated table chip-change screen feature
US20100090405A1 (en) * 2008-07-15 2010-04-15 Snow Roger M Automated House Way Indicator and Activator
US20100113120A1 (en) * 2008-11-06 2010-05-06 Snow Roger M Egregious error mitigation system
US20100244382A1 (en) * 2008-07-15 2010-09-30 Snow Roger M Automated house way indicator and commission indicator
US8070604B2 (en) 2005-08-09 2011-12-06 Cfph, Llc System and method for providing wireless gaming as a service application
US8092303B2 (en) 2004-02-25 2012-01-10 Cfph, Llc System and method for convenience gaming
US8226469B2 (en) 2010-09-29 2012-07-24 Igt Gaming system, gaming device, and method for providing a poker game with a bonus gaming session having re-draw option
US8292741B2 (en) 2006-10-26 2012-10-23 Cfph, Llc Apparatus, processes and articles for facilitating mobile gaming
US8475253B1 (en) 2011-12-15 2013-07-02 Igt Gaming system, gaming device, and method providing a card game having a discarded card re-insertion feature
US8490973B2 (en) 2004-10-04 2013-07-23 Shfl Entertainment, Inc. Card reading shoe with card stop feature and systems utilizing the same
US8510567B2 (en) 2006-11-14 2013-08-13 Cfph, Llc Conditional biometric access in a gaming environment
US8512116B2 (en) 2011-08-22 2013-08-20 Shfl Entertainment, Inc. Methods of managing play of wagering games and systems for managing play of wagering games
US8511684B2 (en) 2004-10-04 2013-08-20 Shfl Entertainment, Inc. Card-reading shoe with inventory correction feature and methods of correcting inventory
US8581721B2 (en) 2007-03-08 2013-11-12 Cfph, Llc Game access device with privileges
US8590900B2 (en) 2004-09-10 2013-11-26 Shfl Entertainment, Inc. Methods of playing wagering games
US8613658B2 (en) 2005-07-08 2013-12-24 Cfph, Llc System and method for wireless gaming system with user profiles
US8645709B2 (en) 2006-11-14 2014-02-04 Cfph, Llc Biometric access data encryption
US8784197B2 (en) 2006-11-15 2014-07-22 Cfph, Llc Biometric access sensitivity
US8840018B2 (en) 2006-05-05 2014-09-23 Cfph, Llc Device with time varying signal
US8956231B2 (en) 2010-08-13 2015-02-17 Cfph, Llc Multi-process communication regarding gaming information
US8974302B2 (en) 2010-08-13 2015-03-10 Cfph, Llc Multi-process communication regarding gaming information
US9183693B2 (en) 2007-03-08 2015-11-10 Cfph, Llc Game access device
US9183705B2 (en) 2004-09-10 2015-11-10 Bally Gaming, Inc. Methods of playing wagering games
US9306952B2 (en) 2006-10-26 2016-04-05 Cfph, Llc System and method for wireless gaming with location determination
US9373220B2 (en) 2004-09-10 2016-06-21 Bally Gaming, Inc. Methods of playing wagering games and related apparatuses
US10357706B2 (en) 2002-05-20 2019-07-23 Bally Gaming, Inc. Four-card poker with variable wager over a network
US10460566B2 (en) 2005-07-08 2019-10-29 Cfph, Llc System and method for peer-to-peer wireless gaming

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2009202562A1 (en) 2008-06-25 2010-01-14 Aristocrat Technologies Australia Pty Limited Method of gaming, a gaming system and a game controller
US10817851B2 (en) 2009-12-23 2020-10-27 Aristocrat Technologies Australia Pty Limited System and method for cashless gaming
AU2020244440A1 (en) 2020-03-04 2021-09-23 Aristocrat Technologies Australia Pty Limited Gaming device with dynamic awards based on symbol position state

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2998252A (en) * 1959-01-27 1961-08-29 Martin Thomas R St Electrically driven random indicium selector
US3580581A (en) * 1968-12-26 1971-05-25 Raven Electronics Corp Probability-generating system and game for use therewith
US3606337A (en) * 1969-03-24 1971-09-20 Standard Telephones Cables Ltd Poker machine having binary coded rotatable drums
US3653026A (en) * 1970-06-03 1972-03-28 Frederick A Hurley Random selection system for bingo and the like
US3733075A (en) * 1970-05-07 1973-05-15 Waukegan Electronics Device for displaying randomly selected symbol combinations and randomly operative player operated symbol changing means therefor
US3735982A (en) * 1972-03-29 1973-05-29 J N Gerfin Electronic card game machine
US3770269A (en) * 1968-06-17 1973-11-06 C Elder Random unit generator amusement device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2998252A (en) * 1959-01-27 1961-08-29 Martin Thomas R St Electrically driven random indicium selector
US3770269A (en) * 1968-06-17 1973-11-06 C Elder Random unit generator amusement device
US3580581A (en) * 1968-12-26 1971-05-25 Raven Electronics Corp Probability-generating system and game for use therewith
US3606337A (en) * 1969-03-24 1971-09-20 Standard Telephones Cables Ltd Poker machine having binary coded rotatable drums
US3733075A (en) * 1970-05-07 1973-05-15 Waukegan Electronics Device for displaying randomly selected symbol combinations and randomly operative player operated symbol changing means therefor
US3653026A (en) * 1970-06-03 1972-03-28 Frederick A Hurley Random selection system for bingo and the like
US3735982A (en) * 1972-03-29 1973-05-29 J N Gerfin Electronic card game machine

Cited By (212)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4095795A (en) * 1974-06-24 1978-06-20 Saxton James C Amusement apparatus and method
US4052057A (en) * 1974-08-20 1977-10-04 Trevor William Castle Electronic amusement machine
US4157829A (en) * 1975-01-28 1979-06-12 System Operations, Inc. Instant lottery game employing vending machines which are centrally controlled by computers
US4099722A (en) * 1975-07-30 1978-07-11 Centronics Data Computer Corp. Electronic slot machine
US4072310A (en) * 1976-01-15 1978-02-07 Beam Dale R Control apparatus for a card game simulator
US4093215A (en) * 1976-06-04 1978-06-06 Ballard Chester P Chance operated simulated card game
US4238127A (en) * 1977-01-17 1980-12-09 Bally Manufacturing Corporation Electronic gaming apparatus
US4173342A (en) * 1977-04-29 1979-11-06 Corlieu Ferran Jeanne De Device for simulating a card game
US4339134A (en) * 1977-07-05 1982-07-13 Rockwell International Corporation Electronic card game
US4121830A (en) * 1977-08-29 1978-10-24 Random Electronic Games Co. Bingo computer apparatus and method
US4206920A (en) * 1977-11-04 1980-06-10 Toll Karl D Multiple digit electronic game
WO1980002804A1 (en) * 1979-06-20 1980-12-24 Bliss D Electronic control for rotatable reel gaming device
US4299388A (en) * 1979-06-20 1981-11-10 Concorde Manufacturing Company Apparatus for controlling a reeled chance based amusement device
WO1981001664A1 (en) * 1979-12-17 1981-06-25 Remote Dynamics A remote gaming system
US4467424A (en) * 1979-12-17 1984-08-21 Hedges Richard A Remote gaming system
US4339798A (en) * 1979-12-17 1982-07-13 Remote Dynamics Remote gaming system
EP0042864A1 (en) * 1979-12-31 1982-01-06 Mattel, Inc. Electronic card game simulator
US4314336A (en) * 1979-12-31 1982-02-02 Mattel, Inc. Electronic card game simulator
EP0042864A4 (en) * 1979-12-31 1983-12-01 Mattel Inc Electronic card game simulator.
WO1981001895A1 (en) * 1979-12-31 1981-07-09 Mattel Inc Electronic card game simulator
US4380334A (en) * 1980-03-24 1983-04-19 Mattel, Inc. Electronic card game simulator
US4760527A (en) * 1983-04-05 1988-07-26 Sidley Joseph D H System for interactively playing poker with a plurality of players
US5159549A (en) * 1984-06-01 1992-10-27 Poker Pot, Inc. Multiple player game data processing system with wager accounting
EP0181158A3 (en) * 1984-11-02 1987-07-01 Kabushiki Kaisha Universal Slot machine
EP0181158A2 (en) * 1984-11-02 1986-05-14 Kabushiki Kaisha Universal Slot machine
EP0398767A2 (en) * 1984-11-02 1990-11-22 Kabushiki Kaisha Universal Slot machine
EP0398767A3 (en) * 1984-11-02 1990-12-19 Kabushiki Kaisha Universal Slot machine
US4648604A (en) * 1985-04-29 1987-03-10 Professional Video Association, Inc. Elimination draw poker game
US4743022A (en) * 1986-03-06 1988-05-10 Wood Michael W 2nd chance poker method
EP0333338A2 (en) * 1988-02-23 1989-09-20 James Phillips Mc Cann Improvements in and relating to video game machines
EP0333338A3 (en) * 1988-02-23 1990-03-14 James Phillips Mc Cann Improvements in and relating to video game machines
US5626341A (en) * 1988-04-18 1997-05-06 Progressive Games, Inc. Methods of progressive jackpot gaming
US6234895B1 (en) 1988-04-18 2001-05-22 Daniel A. Jones Methods of progressive jackpot gaming
US5364104A (en) * 1988-04-18 1994-11-15 D&D Gaming Patents, Inc. Apparatus for progressive jackpot gaming
US5364105A (en) * 1988-04-18 1994-11-15 D & D Gaming Patents, Inc. Method of progressive jackpot twenty-one
US5374067A (en) * 1988-04-18 1994-12-20 Jones; Daniel A. Method for playing a card game
US5377973A (en) * 1988-04-18 1995-01-03 D&D Gaming Patents, Inc. Methods and apparatus for playing casino card games including a progressive jackpot
US5380012A (en) * 1988-04-18 1995-01-10 Jones; Daniel A. Method for playing a card game
US5382025A (en) * 1988-04-18 1995-01-17 D & D Gaming Patents, Inc. Method for playing a poker game
US5544893A (en) * 1988-04-18 1996-08-13 Progressive Games, Inc. Apparatus for progressive jackpot gaming
US4948134A (en) * 1988-04-18 1990-08-14 Caribbean Stud Enterprises, Inc. Electronic poker game
US6312330B1 (en) 1988-04-18 2001-11-06 Progessive Games, Inc. Methods of progressive jackpot gaming
US6073930A (en) * 1988-04-18 2000-06-13 Progressive Games, Inc. Apparatus for progressive jackpot gaming
US6070878A (en) * 1988-04-18 2000-06-06 Progressive Games, Inc. Apparatus for progressive jackpot gaming
US6045130A (en) * 1988-04-18 2000-04-04 Progressive Games, Inc. Methods of progressive jackpot gaming
US5794964A (en) * 1988-04-18 1998-08-18 Progressive Games, Inc. Apparatus for progressive jackpot gaming
US5795225A (en) * 1988-04-18 1998-08-18 Progressive Games, Inc. Methods of progressive jackpot gaming
US5836818A (en) * 1988-04-18 1998-11-17 Progressive Games, Inc. Coin acceptor including multi-state visual indicator apparatus and method
US5913726A (en) * 1988-04-18 1999-06-22 Progressive Games, Inc. Methods of progressive jackpot gaming
US5188363A (en) * 1991-12-30 1993-02-23 Rio Properties, Inc. Wheel of fortune poker game apparatus and method
US7246799B2 (en) 1993-02-25 2007-07-24 Shuffle Master, Inc. Method of playing a poker-type wagering game with multiple betting options
US6273424B1 (en) 1993-02-25 2001-08-14 John G. Breeding Bet withdrawal casino game and apparatus
US20090075724A1 (en) * 1993-02-25 2009-03-19 Shuffle Master, Inc. Wireless bet withdrawal gaming system
US20080207295A1 (en) * 1993-02-25 2008-08-28 Yoseloff Mark L Interactive simulated stud poker apparatus and method
US20050040601A1 (en) * 1993-02-25 2005-02-24 Shuffle Master, Inc. Interactive simulated stud poker apparatus and method
US6454266B1 (en) 1993-02-25 2002-09-24 Shuffle Master, Inc. Bet withdrawal casino game with wild symbol
US20040061288A1 (en) * 1993-02-25 2004-04-01 Shuffle Master, Inc. Method of playing a poker-type wagering game with multiple betting options
US20050127606A1 (en) * 1993-02-25 2005-06-16 Shuffle Master, Inc. High-low poker wagering games
US7510190B2 (en) 1993-02-25 2009-03-31 Shuffle Master, Inc. High-low poker wagering games
US6334614B1 (en) 1993-02-25 2002-01-01 Shuffle Master Inc Multi-tiered wagering method and game
US6019374A (en) * 1993-02-25 2000-02-01 Shuffle Master, Inc. Multi-tiered wagering method and game
US7367563B2 (en) 1993-02-25 2008-05-06 Shuffle Master, Inc. Interactive simulated stud poker apparatus and method
US6336859B2 (en) 1993-03-31 2002-01-08 Progressive Games, Inc. Method for progressive jackpot gaming
US20050029744A1 (en) * 1995-07-19 2005-02-10 Shuffle Master, Inc. Bet withdrawal game with three card poker side bet
US6729620B2 (en) 1995-07-24 2004-05-04 Donald W. Jones Methods for providing a jackpot component in a casino game in which an initial set of cards and additional cards are dealt
US5577731A (en) * 1995-07-24 1996-11-26 Progressive Games, Inc. Method of progressive jackpot twenty-one wherein the predetermined winning arrangement of cards include two aces, three aces and four aces
US5711715A (en) * 1995-10-11 1998-01-27 Ringo; Dock E. Method and apparatus for tournament play of coin operated games
US6206374B1 (en) 1995-10-13 2001-03-27 Progressive Games, Inc. Methods of playing poker games
US5725216A (en) * 1995-10-13 1998-03-10 Progressive Games, Inc. Methods of playing poker games
US5964464A (en) * 1995-10-13 1999-10-12 Progressive Games, Inc. Methods of playing poker games
US6082887A (en) * 1996-09-20 2000-07-04 Merit Industries, Inc. Game machine with automated tournament mode
US5743798A (en) * 1996-09-30 1998-04-28 Progressive Games, Inc. Apparatus for playing a roulette game including a progressive jackpot
US6375189B1 (en) 1997-11-20 2002-04-23 Progressive Games, Inc. Methods for providing a jackpot component in a casino game in which an initial set of cards and additional cards are dealt
US6402150B1 (en) 1997-11-20 2002-06-11 Progressive Ggames, Inc. Methods for providing a jackpot component in a casino game in which an initial set of cards are dealt
US20040222590A9 (en) * 2001-12-11 2004-11-11 Loewenstein David Allen Poker game
US20030107174A1 (en) * 2001-12-11 2003-06-12 Loewenstein David Allen Poker game
US20030193141A1 (en) * 2002-02-22 2003-10-16 David Loewenstein Method and apparatus to play card game
US20050236774A1 (en) * 2002-02-22 2005-10-27 Loewenstein David A Card game with moving cards
US7341254B2 (en) 2002-02-22 2008-03-11 David Loewenstein Method and apparatus to play card game
US7258342B2 (en) 2002-02-22 2007-08-21 David Allen Loewenstein Card game with moving cards
US20090295091A1 (en) * 2002-05-20 2009-12-03 Abbott Eric L Poker games with player qualification
US10357706B2 (en) 2002-05-20 2019-07-23 Bally Gaming, Inc. Four-card poker with variable wager over a network
US20040084843A1 (en) * 2002-10-31 2004-05-06 Shuffle Master, Inc. Wagering game with table bonus
US20050269783A1 (en) * 2002-10-31 2005-12-08 Snow Roger M Wagering game with table bonus
US7537456B2 (en) 2002-10-31 2009-05-26 Shuffle Master, Inc. Wagering game with table bonus
US6923446B2 (en) 2002-10-31 2005-08-02 Shuffle Master, Inc. Wagering game with table bonus
US20040090003A1 (en) * 2002-11-12 2004-05-13 Shuffle Master, Inc. Wagering game with table bonus
US8092291B2 (en) 2003-07-31 2012-01-10 Igt Apparatus and method for poker game with additional draw card options
US20050026665A1 (en) * 2003-07-31 2005-02-03 Peter Gerrard Apparatus and method for poker game with additional draw card options
US7297057B2 (en) * 2003-07-31 2007-11-20 Igt Apparatus and method for poker game with additional draw card options
US7300347B1 (en) 2003-08-26 2007-11-27 Creative Gaming Concepts, Inc. Wagering gaming and method of play
US7306517B1 (en) 2003-08-26 2007-12-11 Creative Gaming Concepts, Inc. Wagering gaming and method of play
US20050051963A1 (en) * 2003-09-09 2005-03-10 Shuffle Master, Inc. Casino card game with parlay bet feature
US10726664B2 (en) 2004-02-25 2020-07-28 Interactive Games Llc System and method for convenience gaming
US10391397B2 (en) 2004-02-25 2019-08-27 Interactive Games, Llc System and method for wireless gaming with location determination
US9430901B2 (en) 2004-02-25 2016-08-30 Interactive Games Llc System and method for wireless gaming with location determination
US8696443B2 (en) 2004-02-25 2014-04-15 Cfph, Llc System and method for convenience gaming
US10360755B2 (en) 2004-02-25 2019-07-23 Interactive Games Llc Time and location based gaming
US11514748B2 (en) 2004-02-25 2022-11-29 Interactive Games Llc System and method for convenience gaming
US10783744B2 (en) 2004-02-25 2020-09-22 Cfph, Llc System and method for wireless lottery
US9355518B2 (en) 2004-02-25 2016-05-31 Interactive Games Llc Gaming system with location determination
US11024115B2 (en) 2004-02-25 2021-06-01 Interactive Games Llc Network based control of remote system for enabling, disabling, and controlling gaming
US8308568B2 (en) 2004-02-25 2012-11-13 Cfph, Llc Time and location based gaming
US8616967B2 (en) 2004-02-25 2013-12-31 Cfph, Llc System and method for convenience gaming
US10653952B2 (en) 2004-02-25 2020-05-19 Interactive Games Llc System and method for wireless gaming with location determination
US8162756B2 (en) 2004-02-25 2012-04-24 Cfph, Llc Time and location based gaming
US8504617B2 (en) 2004-02-25 2013-08-06 Cfph, Llc System and method for wireless gaming with location determination
US10515511B2 (en) 2004-02-25 2019-12-24 Interactive Games Llc Network based control of electronic devices for gaming
US8092303B2 (en) 2004-02-25 2012-01-10 Cfph, Llc System and method for convenience gaming
US20070066402A1 (en) * 2004-02-25 2007-03-22 Cfph, Llc System and Method for Convenience Gaming
US10347076B2 (en) 2004-02-25 2019-07-09 Interactive Games Llc Network based control of remote system for enabling, disabling, and controlling gaming
US20060025191A1 (en) * 2004-08-02 2006-02-02 Shuffle Master, Inc. High-low poker wagering games
US10339766B2 (en) 2004-09-10 2019-07-02 Bally Gaming, Inc. Methods of playing wagering games and related systems
US9373220B2 (en) 2004-09-10 2016-06-21 Bally Gaming, Inc. Methods of playing wagering games and related apparatuses
US8590900B2 (en) 2004-09-10 2013-11-26 Shfl Entertainment, Inc. Methods of playing wagering games
US9183705B2 (en) 2004-09-10 2015-11-10 Bally Gaming, Inc. Methods of playing wagering games
US9898896B2 (en) 2004-09-10 2018-02-20 Bally Gaming, Inc. Methods of playing wagering games and related systems
US7862417B2 (en) 2004-09-15 2011-01-04 Igt Card game enabling separate evaluations for multiple game outcome combinations
US20060066051A1 (en) * 2004-09-15 2006-03-30 Wagerworks, Inc. Casino card game
US20100016051A1 (en) * 2004-09-15 2010-01-21 Igt Card game enabling separate evaluations for multiple game outcome combinations
US7614946B2 (en) 2004-09-15 2009-11-10 Igt Card game enabling separate evaluations for multiple game outcome combinations
US8490973B2 (en) 2004-10-04 2013-07-23 Shfl Entertainment, Inc. Card reading shoe with card stop feature and systems utilizing the same
US9162138B2 (en) 2004-10-04 2015-10-20 Bally Gaming, Inc. Card-reading shoe with inventory correction feature and methods of correcting inventory
US8511684B2 (en) 2004-10-04 2013-08-20 Shfl Entertainment, Inc. Card-reading shoe with inventory correction feature and methods of correcting inventory
US10733847B2 (en) 2005-07-08 2020-08-04 Cfph, Llc System and method for gaming
US10460566B2 (en) 2005-07-08 2019-10-29 Cfph, Llc System and method for peer-to-peer wireless gaming
US8506400B2 (en) 2005-07-08 2013-08-13 Cfph, Llc System and method for wireless gaming system with alerts
US10510214B2 (en) 2005-07-08 2019-12-17 Cfph, Llc System and method for peer-to-peer wireless gaming
US8708805B2 (en) 2005-07-08 2014-04-29 Cfph, Llc Gaming system with identity verification
US11069185B2 (en) 2005-07-08 2021-07-20 Interactive Games Llc System and method for wireless gaming system with user profiles
US8613658B2 (en) 2005-07-08 2013-12-24 Cfph, Llc System and method for wireless gaming system with user profiles
US8690679B2 (en) 2005-08-09 2014-04-08 Cfph, Llc System and method for providing wireless gaming as a service application
US11636727B2 (en) 2005-08-09 2023-04-25 Cfph, Llc System and method for providing wireless gaming as a service application
US8070604B2 (en) 2005-08-09 2011-12-06 Cfph, Llc System and method for providing wireless gaming as a service application
US7637810B2 (en) 2005-08-09 2009-12-29 Cfph, Llc System and method for wireless gaming system with alerts
US20070060358A1 (en) * 2005-08-10 2007-03-15 Amaitis Lee M System and method for wireless gaming with location determination
US20070093296A1 (en) * 2005-10-21 2007-04-26 Asher Joseph M System and method for wireless lottery
US7811172B2 (en) 2005-10-21 2010-10-12 Cfph, Llc System and method for wireless lottery
US7644861B2 (en) 2006-04-18 2010-01-12 Bgc Partners, Inc. Systems and methods for providing access to wireless gaming devices
US8403214B2 (en) 2006-04-18 2013-03-26 Bgc Partners, Inc. Systems and methods for providing access to wireless gaming devices
US10460557B2 (en) 2006-04-18 2019-10-29 Cfph, Llc Systems and methods for providing access to a system
US10957150B2 (en) 2006-04-18 2021-03-23 Cfph, Llc Systems and methods for providing access to wireless gaming devices
US8899477B2 (en) 2006-05-05 2014-12-02 Cfph, Llc Device detection
US8939359B2 (en) 2006-05-05 2015-01-27 Cfph, Llc Game access device with time varying signal
US11024120B2 (en) 2006-05-05 2021-06-01 Cfph, Llc Game access device with time varying signal
US10286300B2 (en) 2006-05-05 2019-05-14 Cfph, Llc Systems and methods for providing access to locations and services
US10535223B2 (en) 2006-05-05 2020-01-14 Cfph, Llc Game access device with time varying signal
US8397985B2 (en) 2006-05-05 2013-03-19 Cfph, Llc Systems and methods for providing access to wireless gaming devices
US11229835B2 (en) 2006-05-05 2022-01-25 Cfph, Llc Systems and methods for providing access to wireless gaming devices
US20070257101A1 (en) * 2006-05-05 2007-11-08 Dean Alderucci Systems and methods for providing access to wireless gaming devices
US8695876B2 (en) 2006-05-05 2014-04-15 Cfph, Llc Systems and methods for providing access to wireless gaming devices
US7549576B2 (en) 2006-05-05 2009-06-23 Cfph, L.L.C. Systems and methods for providing access to wireless gaming devices
US8840018B2 (en) 2006-05-05 2014-09-23 Cfph, Llc Device with time varying signal
US8740065B2 (en) 2006-05-05 2014-06-03 Cfph, Llc Systems and methods for providing access to wireless gaming devices
US10751607B2 (en) 2006-05-05 2020-08-25 Cfph, Llc Systems and methods for providing access to locations and services
US20090209325A1 (en) * 2006-05-05 2009-08-20 Dean Alderucci Systems and methods for providing access to wireless gaming devices
US20080026806A1 (en) * 2006-07-13 2008-01-31 Steven Terrance Gold Poker-type game and method
US7803041B2 (en) 2006-07-13 2010-09-28 Igt Poker-type game and method
US8292741B2 (en) 2006-10-26 2012-10-23 Cfph, Llc Apparatus, processes and articles for facilitating mobile gaming
US10535221B2 (en) 2006-10-26 2020-01-14 Interactive Games Llc System and method for wireless gaming with location determination
US11017628B2 (en) 2006-10-26 2021-05-25 Interactive Games Llc System and method for wireless gaming with location determination
US9306952B2 (en) 2006-10-26 2016-04-05 Cfph, Llc System and method for wireless gaming with location determination
US9280648B2 (en) 2006-11-14 2016-03-08 Cfph, Llc Conditional biometric access in a gaming environment
US8645709B2 (en) 2006-11-14 2014-02-04 Cfph, Llc Biometric access data encryption
US10706673B2 (en) 2006-11-14 2020-07-07 Cfph, Llc Biometric access data encryption
US8510567B2 (en) 2006-11-14 2013-08-13 Cfph, Llc Conditional biometric access in a gaming environment
US10546107B2 (en) 2006-11-15 2020-01-28 Cfph, Llc Biometric access sensitivity
US11182462B2 (en) 2006-11-15 2021-11-23 Cfph, Llc Biometric access sensitivity
US8784197B2 (en) 2006-11-15 2014-07-22 Cfph, Llc Biometric access sensitivity
US9411944B2 (en) 2006-11-15 2016-08-09 Cfph, Llc Biometric access sensitivity
US11055958B2 (en) 2007-03-08 2021-07-06 Cfph, Llc Game access device with privileges
US8581721B2 (en) 2007-03-08 2013-11-12 Cfph, Llc Game access device with privileges
US10332155B2 (en) 2007-03-08 2019-06-25 Cfph, Llc Systems and methods for determining an amount of time an object is worn
US9183693B2 (en) 2007-03-08 2015-11-10 Cfph, Llc Game access device
US10424153B2 (en) 2007-03-08 2019-09-24 Cfph, Llc Game access device with privileges
US20080224402A1 (en) * 2007-03-14 2008-09-18 Shuffle Master, Inc. Bad beat side bet on house-banked casino card games
US10366562B2 (en) 2007-03-14 2019-07-30 Cfph, Llc Multi-account access device
US11055954B2 (en) 2007-03-14 2021-07-06 Cfph, Llc Game account access device
US20080224822A1 (en) * 2007-03-14 2008-09-18 Gelman Geoffrey M Game account access device
US8319601B2 (en) 2007-03-14 2012-11-27 Cfph, Llc Game account access device
US8210533B2 (en) 2008-03-10 2012-07-03 Igt Gaming system, gaming device and method for providing draw poker game
US7993191B2 (en) 2008-03-10 2011-08-09 Igt Gaming system, gaming device and method for providing draw poker game
US8210532B2 (en) 2008-03-10 2012-07-03 Igt Gaming system, gaming device and method for providing draw poker game
US20090224478A1 (en) * 2008-03-10 2009-09-10 Igt Gaming system, gaming device and method for providing draw poker game
US20090279851A1 (en) * 2008-04-09 2009-11-12 Sony Corporation Captured image data management method and image capturing apparatus
US8597114B2 (en) 2008-07-15 2013-12-03 Shfl Entertainment, Inc. Systems and methods for assisting players in arranging hands for table games
US9569924B2 (en) 2008-07-15 2017-02-14 Bally Gaming, Inc. Systems and methods for play of casino table card games
US8251802B2 (en) 2008-07-15 2012-08-28 Shuffle Master, Inc. Automated house way indicator and commission indicator
US20100090405A1 (en) * 2008-07-15 2010-04-15 Snow Roger M Automated House Way Indicator and Activator
US8342529B2 (en) 2008-07-15 2013-01-01 Shuffle Master, Inc. Automated house way indicator and activator
US20100016050A1 (en) * 2008-07-15 2010-01-21 Snow Roger M Chipless table split screen feature
US9101821B2 (en) 2008-07-15 2015-08-11 Bally Gaming, Inc. Systems and methods for play of casino table card games
US10410465B2 (en) 2008-07-15 2019-09-10 Bally Gaming, Inc. Physical playing card gaming systems and related methods
US20100244382A1 (en) * 2008-07-15 2010-09-30 Snow Roger M Automated house way indicator and commission indicator
US9159185B2 (en) 2008-07-15 2015-10-13 Bally Gaming, Inc. Physical playing card gaming systems and related methods
US9649549B2 (en) 2008-07-15 2017-05-16 Bally Gaming, Inc. Physical playing card gaming systems and related methods
US8262475B2 (en) 2008-07-15 2012-09-11 Shuffle Master, Inc. Chipless table split screen feature
US8251801B2 (en) 2008-09-05 2012-08-28 Shuffle Master, Inc. Automated table chip-change screen feature
US20100062845A1 (en) * 2008-09-05 2010-03-11 Wadds Nathan J Automated table chip-change screen feature
US20100113120A1 (en) * 2008-11-06 2010-05-06 Snow Roger M Egregious error mitigation system
US8591305B2 (en) 2008-11-06 2013-11-26 Shfl Entertainment, Inc. Method, apparatus and system for egregious error mitigation
US8287347B2 (en) 2008-11-06 2012-10-16 Shuffle Master, Inc. Method, apparatus and system for egregious error mitigation
US8974302B2 (en) 2010-08-13 2015-03-10 Cfph, Llc Multi-process communication regarding gaming information
US10744416B2 (en) 2010-08-13 2020-08-18 Interactive Games Llc Multi-process communication regarding gaming information
US8956231B2 (en) 2010-08-13 2015-02-17 Cfph, Llc Multi-process communication regarding gaming information
US10406446B2 (en) 2010-08-13 2019-09-10 Interactive Games Llc Multi-process communication regarding gaming information
US8226469B2 (en) 2010-09-29 2012-07-24 Igt Gaming system, gaming device, and method for providing a poker game with a bonus gaming session having re-draw option
US9105161B2 (en) 2010-09-29 2015-08-11 Igt Gaming system, gaming device, and method for providing a poker game with a bonus gaming session having re-draw option
US8535135B2 (en) 2010-09-29 2013-09-17 Igt Gaming system, gaming device, and method for providing a poker game with a bonus gaming session having re-draw option
US8512116B2 (en) 2011-08-22 2013-08-20 Shfl Entertainment, Inc. Methods of managing play of wagering games and systems for managing play of wagering games
US8758107B2 (en) 2011-12-15 2014-06-24 Igt Gaming system, gaming device, and method providing a card game having a discarded card re-insertion feature
US8475253B1 (en) 2011-12-15 2013-07-02 Igt Gaming system, gaming device, and method providing a card game having a discarded card re-insertion feature

Also Published As

Publication number Publication date
GB1447550A (en) 1976-08-25
DE2245969B2 (en) 1975-06-19
DE2245969A1 (en) 1974-04-18

Similar Documents

Publication Publication Date Title
US3876208A (en) Gaming machine
US3819186A (en) Automatic electronic gaming machine of the roulette type
US5626341A (en) Methods of progressive jackpot gaming
US5695402A (en) Game of chance
US5255915A (en) Six-card draw-poker-like video game
US4861041A (en) Methods of progressive jackpot gaming
US5544893A (en) Apparatus for progressive jackpot gaming
JPH01198584A (en) Game machine with coins put in
US6450883B1 (en) Operation of gaming machines
US5078405A (en) Apparatus for progressive jackpot gaming
GB2106685A (en) Gaming or amusement machine
GB2072395A (en) Gaming or amusement machine
AU2004209124A1 (en) Method, system, and program product for conducting bingo games
GB2147442A (en) Coin operated gaming or amusement machines
JPH0221883A (en) Progressive jack pot gambling apparatus
AU2005277564A1 (en) Bingo system with dynamic game play result ordering
JP2018153549A (en) Game machine
US20070149277A1 (en) Interactive slot machine
JP6653873B1 (en) Gaming machine
JP5918832B1 (en) Game machine
EP0233298B1 (en) Improvements relating to amusement arcade machines for use in amusement and/or gaming or the like
JP2517350Y2 (en) Pachinko ball counting device
JP7170324B2 (en) game machine
JP6133723B2 (en) Game information management device
JP4437334B2 (en) Pachinko machine