US3882492A - Data signalling systems - Google Patents
Data signalling systems Download PDFInfo
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- US3882492A US3882492A US351882A US35188273A US3882492A US 3882492 A US3882492 A US 3882492A US 351882 A US351882 A US 351882A US 35188273 A US35188273 A US 35188273A US 3882492 A US3882492 A US 3882492A
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- 230000011664 signaling Effects 0.000 title claims abstract description 9
- 239000011159 matrix material Substances 0.000 claims description 20
- 230000002401 inhibitory effect Effects 0.000 claims description 9
- 230000008034 disappearance Effects 0.000 claims description 8
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- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B25/00—Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
- G08B25/14—Central alarm receiver or annunciator arrangements
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- ABSTRACT 1 1 Appl- N04 351,882 In a security alarm signalling system in which a signal may be transmitted from any one of a number of re 52 US. (:1. 340/413; 340/150 mote Stations to a central receiving Station the receiv- 51 1m. (:1.
- G08b 19/00; H04g 3/00 Station includes a multiple input encoder respon- [58] Field of Search 340/413, 412, 408, 213.1, Sive a change of State any one of its inputs for 340/150 151, I63 presenting a coded output representative of the number of the input on which the change of state has 00- [56] References Cited curred, and a digital display device including means UNITED STATES PATENTS for scanning the coded output to obtain a digital read- I out of the said number and thereby, in use, identifying 3,483,555 12/1969 1311310....
- the central receiving station normally includes one or more indicator panels having indicator lights to identify the different remote station.
- Such panels are generally bulky.
- more than one security officer is often required to maintain adequate supervision of the different panels.
- the appearance or disappearance of input signals from the remote stations trigger respective bistable devices, and a gating circuit is connected between each of the bistable devices and respective inputs of the encoder.
- the system then includes a shift register for enabling each of the gating circuits in turn and means for inhibiting the shift register whenever a signal is transferred into the encoder. This prevents further signals being transferred into the encoder before the original signal has been encoded and read out on the display device.
- the encoder may comprise, for example, amatrix, each input being connected to a pair of mutually perpendicular coordinate lines, and the scanning means then includes a pair of counters arranged to hunt synchronously along the coordinate lines until a coincidence is obtained for each counter. The two counters then give a combined read out in which the two digits represent the least significant digit and the most significant digit of the line number on which a change of state has occured.
- FIG. 1 is a block circuit diagram of a multiple line alarm security system which presents a visual digital read-out and prints information relating to the date, time and place at which an alarm signal was generated.
- FIG. 2 is a waveform diagram illustrating the operation of the circuit in FIG. 1.
- the flip-flops acts as a binary store and a l in the store is transferred to a preselected address in a matrix through NAND gates I la, 1 lb, etc., by the appearance of enabling shift register signalsfl,j2, etc., on the second NAND gate input.
- a signal is transferred to a particular address in the diode matrix by feeding the outputs of each NAND gate to a predetermined intersection of the coordinate lines of the matrix.
- Each output is thereby connected to the junction of a pair of forward biased diodes in the matrix so that an output is obtained on each of the respective coordinate lines.
- the coordinate address of each store element is selected to correspond to the number of the input on which the appearance or disappearance of a signal has been detected. For example, the coordinates (3, 4) will correspond to line No. 34.
- NAND gates G1, G2 from the outputs of NOR gates 12a 12d and NAND gates 13a, 131) such that pulses from an oscillator S1 are gated to master electromagnetic decade counters El having decimal read-out wires connected to AND gates 16a, 16b. Only two of these gates 16a0 and 16219 (these connected to the 0 and read out wires) are shown in the figure for the sake of clarity.
- the second input of the gates 16a, 16b is connected to the corresponding one of the 0-9 and 10-90 lines of the matrix. The counters then hunt sinchronously along the mutually perpendicular matrix lines until the two coordinates are found which give a coincidence output from the gates 16a, 16b.
- the presence of a l in the matrix also inhibits the shift register by triggering a control bistable B1 to close a gate G3 between a clock Cl and the shift register. This prevents any further signals being read into the matrix before the original signal has been read out.
- the resetting of the flip-flops is controlled by an input from the NOR gates 15a 15n.
- the gates [5a 1511 can only be enabled by the coincidence of an X input from a 20 micro-second delay circuit D10 responsive to the output of bistable B1 and a second input which is connected to the respective matrix store input.
- a particular flip-flop transfers data to the matrix store, only that flip-flop can be reset after the data has been read out. This ensures that if at any time two or more alarm inputs appear simultaneously, they will be read out serially.
- FIG. 2 A complete cycle of operation commencing with an alarm input is clearly illustrated in FIG. 2.
- the alarm input triggers one of the J-K flip-flops B/Sl B/Sn and when the output from the flip-flop next coincides with the output of the shift register a pulse is fed into the matrix.
- the presence of the pulse in the matrix triggers the control bistable Bl which in turn triggers a timer giving a pulse of between 5 and 10 seconds.
- the master decade counters hunt for the address of the stored signal and at the end of the timer period a reset pulse from the delay circuit D10 resets the J-K flipflop. This in turn cancels the data in the matrix store.
- the signal from the delay circuit D10 also triggers a second m5 delay circuit D20, and the output from D20 enables a gate G6 to permit the printing of the final count displayed by the slave counters of the printer.
- a monostable M3 is triggered which closes the gates G1, G2 and feeds a reset signal to the electromagnetic decade counters and to the slave counters of the printer.
- the trailing edge of the pulse from the monostable M3 triggers a 5 ,us monostable M4 and the output from M4'resets the control bistable Bl. This enables the gate G3 so that clock pulses are again fed to the shift register.
- the shift register also clears the dynamic *bit on every 99th pulse of the clock to avoid any trailing pulses.
- the outputs of the bistables B2, 82a are fed to an OR gate G8, and the output of G8 inhibits an AND gate G9 connected to a clear line indicator.
- the second input of the AND gate G9 receives a Z pulse output from the bistable Bl which occurs each time a number is loaded into the matrix and displayed by the counters; if a number is displayed in response to the disappearance of an alarm input the AND gate G9 will no longer be inhibited because there is no input to the gates G7, G711 and the clear line indicator will therefore be energized by the Z pulse.
- a change of state on any one input line is fed to an encoder which converts the single input into binary coded decimal (BCD) form representing the number of the input.
- BCD binary coded decimal
- the BCD outputs representing the most and least significant digits may then either be synchronously scanned to search for the marked lines (this requires a display device which is capable of decoding the detected BCD (information) or they may be first decoded back into decimal form and then fed to AND gates such as those shown as 16a 16b etc., in the drawing for comparison with the decimal outputs of the electro-mechanical decade counters.
- a receiver for use in a security alarm signalling system in which a predetermined number of remote stations are each connected to a central receiving station by respective pairs of wires. each remote station being identified by a different predetermined number. and the receiver including a multiple input encoder, each input of said encoder being connected. when in use. to a respective pair of wires from one of the numbered remote stations. and the receiver also including a multiple input binary store; gating means connected between the outputs of said binary store and corresponding inputs of said encoder; scanning means for periodically scanning the inputs of said encoder.
- said scanning means including enabling means for periodically en abling each of said gating means in turn;
- said encoder including means responsive to a change in the signal level on any one of its inputs for generating a coded output signal representative of the number of the remote station to which the input is connected, and a digital display device including means for converting the coded output into a digital read-out of said number; and means responsive to the presence of a signal in said encoder for inhibiting the enabling means until the signal has been encoded and read out on the display device.
- a receiver in which the encoder includes a diode matrix of perpendicular coordinate lines, the output of each gating circuit being connected to the junction of a respective pair of diodes in the matrix such that an output is obtained from the corresponding pair of coordinate lines which intersect at the junction, the two coordinates together representing the two digits of the numbered input line to be displayed.
- a receiver in which the counter includes means for hunting synchronously for each of the pair of coordinates.
- a receiver in which the counter comprises a pair of electromagnetic decade counters arranged to give a two digit decimal output display. a first of the decade counters hunting for the least significant coordinate and the second decade counter hunting for the most significant coordinate of the number to be displayed.
Abstract
In a security alarm signalling system in which a signal may be transmitted from any one of a number of remote stations to a central receiving station, the receiving station includes a multiple input encoder responsive to a change of state on any one of its inputs for presenting a coded output representative of the number of the input on which the change of state has occurred, and a digital display device including means for scanning the coded output to obtain a digital readout of the said number and thereby, in use, identifying the associated remote station.
Description
United States Patent 11 1 McSorley et a1. 1 1 May 6, 1975 [54] DATA SIGNALLING SYSTEMS 3,644,927 2/1972 Green 340/413 3,714,646 1 1973 N b l 4 4 [75] inventors: David J. McSorley, Tw1ckenham; um erg er 3 0/ Croos Banstead both of Primary Examiner.1ohn W. Caldwell ng an Assistant ExaminerRichard P. Lange [73] Assignee: Alarm Equipment Supplies Limited, 141mm? g fl, Palmer &
Twickenham, Middlesex, England Estabrook [22] F1led: Apr. 17, 1973 [57] ABSTRACT 1 1 Appl- N04 351,882 In a security alarm signalling system in which a signal may be transmitted from any one of a number of re 52 US. (:1. 340/413; 340/150 mote Stations to a central receiving Station the receiv- 51 1m. (:1. G08b 19/00; H04g 3/00 Station includes a multiple input encoder respon- [58] Field of Search 340/413, 412, 408, 213.1, Sive a change of State any one of its inputs for 340/150 151, I63 presenting a coded output representative of the number of the input on which the change of state has 00- [56] References Cited curred, and a digital display device including means UNITED STATES PATENTS for scanning the coded output to obtain a digital read- I out of the said number and thereby, in use, identifying 3,483,555 12/1969 1311310.... 340/2131 the associated remote Station 3,543,267 11/1970 Morrls 340/413 3,613,092 10/1971 Schumann et a1. 340/413 7 Claims, 2 Drawing Figures Motnx r0 Matrix PATENIEB-" 975 SHEET KE S m5 9 QQNQQE w k m R m KQE MXQ R ES DATA SIGNALLING SYSTEMS This invention relates to signalling systems, and has particular application to a multi-line security alarm system in which alarm signals from different remote stations are fed to a central receiving station.
At present the central receiving station normally includes one or more indicator panels having indicator lights to identify the different remote station. Such panels are generally bulky. Moreover, with systems handling a large number of input lines, more than one security officer is often required to maintain adequate supervision of the different panels.
In accordance with the present invention a receiver for use in a security alarm signalling system in which a signal may be transmitted from any one of a number of remote stations to a central receiving station, includes: a multiple input encoder responsive to a change of state on any one of its inputs for presenting a coded output representative of the number of the input on which the change of state has occurred, and a digital display device including means for scanning the coded output to obtain a digital read-out of the said number and thereby, in use, identifying the associated remote station.
In one embodiment of the invention the appearance or disappearance of input signals from the remote stations trigger respective bistable devices, and a gating circuit is connected between each of the bistable devices and respective inputs of the encoder. The system then includes a shift register for enabling each of the gating circuits in turn and means for inhibiting the shift register whenever a signal is transferred into the encoder. This prevents further signals being transferred into the encoder before the original signal has been encoded and read out on the display device. The encoder may comprise, for example, amatrix, each input being connected to a pair of mutually perpendicular coordinate lines, and the scanning means then includes a pair of counters arranged to hunt synchronously along the coordinate lines until a coincidence is obtained for each counter. The two counters then give a combined read out in which the two digits represent the least significant digit and the most significant digit of the line number on which a change of state has occured.
One example of the invention is shown in the accompanying drawings in which:
FIG. 1 is a block circuit diagram of a multiple line alarm security system which presents a visual digital read-out and prints information relating to the date, time and place at which an alarm signal was generated.
FIG. 2 is a waveform diagram illustrating the operation of the circuit in FIG. 1.
Referring to these figures, the appearance or disappearance of an alarm input A,A,, triggers a corresponding pulse stretching circuit Dl-Dn which in turn transfers the J-K flip-flops B/Sl B/Sn to a 1.
The flip-flops acts as a binary store and a l in the store is transferred to a preselected address in a matrix through NAND gates I la, 1 lb, etc., by the appearance of enabling shift register signalsfl,j2, etc., on the second NAND gate input. A signal is transferred to a particular address in the diode matrix by feeding the outputs of each NAND gate to a predetermined intersection of the coordinate lines of the matrix. Each output is thereby connected to the junction of a pair of forward biased diodes in the matrix so that an output is obtained on each of the respective coordinate lines. The coordinate address of each store element is selected to correspond to the number of the input on which the appearance or disappearance of a signal has been detected. For example, the coordinates (3, 4) will correspond to line No. 34.
The presence of a 1 in the matrix enables NAND gates G1, G2 from the outputs of NOR gates 12a 12d and NAND gates 13a, 131) such that pulses from an oscillator S1 are gated to master electromagnetic decade counters El having decimal read-out wires connected to AND gates 16a, 16b. Only two of these gates 16a0 and 16219 (these connected to the 0 and read out wires) are shown in the figure for the sake of clarity. The second input of the gates 16a, 16b is connected to the corresponding one of the 0-9 and 10-90 lines of the matrix. The counters then hunt sinchronously along the mutually perpendicular matrix lines until the two coordinates are found which give a coincidence output from the gates 16a, 16b. The coincidence outputs are fed to OR gates 14a, 1412 which inhibit the gates G1, G2 respectively to stop the counters. The number indicated on the counters then corresponds to the number of the input on which a change of state has been detected. Ancillary slave counters controlling the print wheels of a printer (not shown) are wired in parallel to the master counters so that a visible read out of the final number displayed by the counters can be supplemented by printing the number with the time and date at which it occured.
The presence of a l in the matrix also inhibits the shift register by triggering a control bistable B1 to close a gate G3 between a clock Cl and the shift register. This prevents any further signals being read into the matrix before the original signal has been read out.
The resetting of the flip-flops is controlled by an input from the NOR gates 15a 15n. The gates [5a 1511 can only be enabled by the coincidence of an X input from a 20 micro-second delay circuit D10 responsive to the output of bistable B1 and a second input which is connected to the respective matrix store input. In other words, when a particular flip-flop transfers data to the matrix store, only that flip-flop can be reset after the data has been read out. This ensures that if at any time two or more alarm inputs appear simultaneously, they will be read out serially.
A complete cycle of operation commencing with an alarm input is clearly illustrated in FIG. 2. The alarm input triggers one of the J-K flip-flops B/Sl B/Sn and when the output from the flip-flop next coincides with the output of the shift register a pulse is fed into the matrix. The presence of the pulse in the matrix triggers the control bistable Bl which in turn triggers a timer giving a pulse of between 5 and 10 seconds. During this time the master decade counters hunt for the address of the stored signal and at the end of the timer period a reset pulse from the delay circuit D10 resets the J-K flipflop. This in turn cancels the data in the matrix store.
The signal from the delay circuit D10 also triggers a second m5 delay circuit D20, and the output from D20 enables a gate G6 to permit the printing of the final count displayed by the slave counters of the printer. At the end of the print time a monostable M3 is triggered which closes the gates G1, G2 and feeds a reset signal to the electromagnetic decade counters and to the slave counters of the printer. The trailing edge of the pulse from the monostable M3 triggers a 5 ,us monostable M4 and the output from M4'resets the control bistable Bl. This enables the gate G3 so that clock pulses are again fed to the shift register.
The shift register also clears the dynamic *bit on every 99th pulse of the clock to avoid any trailing pulses.
The appearance or disappearance of line fault inputs LFl LFI trigger pulse stretching circuits DlA-DnA corresponding to the pulse stretching circuits D1- Dn so that line fault inputs are displayed in the same way as the alarm inputs. In order to distinguish between line fault and alarm conditions separate indicators are provided for each condition. Thus during an alarm display. an output from the pulse stretching circuits Dl- Dn enables OR gates G7 which triggers bistable B2 to energize the alarm indicator. During a line fault condition, on the other hand, an output from the pulse stretching circuits D/A-DnA enables OR gate G7a which triggers bistable 82a to energize the line fault indicator. Further, in order to distinguish between the appearance and disappearance of an alarm or line fault input the outputs of the bistables B2, 82a are fed to an OR gate G8, and the output of G8 inhibits an AND gate G9 connected to a clear line indicator. The second input of the AND gate G9 receives a Z pulse output from the bistable Bl which occurs each time a number is loaded into the matrix and displayed by the counters; if a number is displayed in response to the disappearance of an alarm input the AND gate G9 will no longer be inhibited because there is no input to the gates G7, G711 and the clear line indicator will therefore be energized by the Z pulse.
In one alternative system (not illustrated) for handling up to 1000 input lines. a change of state on any one input line is fed to an encoder which converts the single input into binary coded decimal (BCD) form representing the number of the input. This has the advantage of requiring not more than 12 output wires for each input. The BCD outputs representing the most and least significant digits may then either be synchronously scanned to search for the marked lines (this requires a display device which is capable of decoding the detected BCD (information) or they may be first decoded back into decimal form and then fed to AND gates such as those shown as 16a 16b etc., in the drawing for comparison with the decimal outputs of the electro-mechanical decade counters.
We claim:
1. A receiver for use in a security alarm signalling system in which a predetermined number of remote stations are each connected to a central receiving station by respective pairs of wires. each remote station being identified by a different predetermined number. and the receiver including a multiple input encoder, each input of said encoder being connected. when in use. to a respective pair of wires from one of the numbered remote stations. and the receiver also including a multiple input binary store; gating means connected between the outputs of said binary store and corresponding inputs of said encoder; scanning means for periodically scanning the inputs of said encoder. said scanning means including enabling means for periodically en abling each of said gating means in turn; said encoder including means responsive to a change in the signal level on any one of its inputs for generating a coded output signal representative of the number of the remote station to which the input is connected, and a digital display device including means for converting the coded output into a digital read-out of said number; and means responsive to the presence of a signal in said encoder for inhibiting the enabling means until the signal has been encoded and read out on the display device.
2. A receiver according to claim 1 in which the digital display device includes a counter. and the receiver further includes an oscillator for feeding pulses to the counter in response to a detected change of signal level on one of the inputs to the encoder, a coincidence detector connected to compare the output of the encoder representing the number of the remote station associated with the change of signal level with the number present in the counter. and inhibiting means connected to receive an output from the coincidence detector when the two numbers being compared are equal for inhibiting the supply of pulses to the counter such that the final number displayed by the counter represents the number of the remote station.
3. A receiver according to claim 1, further including a clear line indicator connected to receive an energising signal from a control circuit whenever a change in signal level has been detected at one of the encoder inputs, and means for inhibiting operation of the indicator whenever an alarm signal is present at one of the inputs to the encoder whereby the indicator distinguishes between the display of a number in response to the appearance of an input signal and the display of a number in response to the disappearance of an input signal.
4. A receiver according to claim 2, in which the digital display device further includes a printer for printing the said input number displayed by the counter.
5. A receiver according to claim 2 in which the encoder includes a diode matrix of perpendicular coordinate lines, the output of each gating circuit being connected to the junction of a respective pair of diodes in the matrix such that an output is obtained from the corresponding pair of coordinate lines which intersect at the junction, the two coordinates together representing the two digits of the numbered input line to be displayed.
6. A receiver according to claim 2 in which the counter includes means for hunting synchronously for each of the pair of coordinates.
7. A receiver according to claim 2 in which the counter comprises a pair of electromagnetic decade counters arranged to give a two digit decimal output display. a first of the decade counters hunting for the least significant coordinate and the second decade counter hunting for the most significant coordinate of the number to be displayed.
Claims (7)
1. A receiver for use in a security alarm signalling system in which a predetermined number of remote stations are each connected to a central receiving station by respective pairs of wires, each remote station being identified by a different predetermined number, and the receiver including a multiple input encoder, each input of said encoder being connected, when in use, to a respective pair of wires from one of the numbered remote stations, and the receiver also including a multiple input binary store; gating means connected between the outputs of said binary store and corresponding inputs of said encoder; scanning means for periodically scanning the inputs of said encoder, said scanning means including enabling means for periodically enabling each of said gating means in turn; said encoder including means responsive to a change in the signal level on any one of its inputs for generating a cOded output signal representative of the number of the remote station to which the input is connected, and a digital display device including means for converting the coded output into a digital read-out of said number; and means responsive to the presence of a signal in said encoder for inhibiting the enabling means until the signal has been encoded and read out on the display device.
2. A receiver according to claim 1 in which the digital display device includes a counter, and the receiver further includes an oscillator for feeding pulses to the counter in response to a detected change of signal level on one of the inputs to the encoder, a coincidence detector connected to compare the output of the encoder representing the number of the remote station associated with the change of signal level with the number present in the counter, and inhibiting means connected to receive an output from the coincidence detector when the two numbers being compared are equal for inhibiting the supply of pulses to the counter such that the final number displayed by the counter represents the number of the remote station.
3. A receiver according to claim 1, further including a clear line indicator connected to receive an energising signal from a control circuit whenever a change in signal level has been detected at one of the encoder inputs, and means for inhibiting operation of the indicator whenever an alarm signal is present at one of the inputs to the encoder whereby the indicator distinguishes between the display of a number in response to the appearance of an input signal and the display of a number in response to the disappearance of an input signal.
4. A receiver according to claim 2, in which the digital display device further includes a printer for printing the said input number displayed by the counter.
5. A receiver according to claim 2 in which the encoder includes a diode matrix of perpendicular coordinate lines, the output of each gating circuit being connected to the junction of a respective pair of diodes in the matrix such that an output is obtained from the corresponding pair of coordinate lines which intersect at the junction, the two coordinates together representing the two digits of the numbered input line to be displayed.
6. A receiver according to claim 2 in which the counter includes means for hunting synchronously for each of the pair of coordinates.
7. A receiver according to claim 2 in which the counter comprises a pair of electromagnetic decade counters arranged to give a two digit decimal output display, a first of the decade counters hunting for the least significant coordinate and the second decade counter hunting for the most significant coordinate of the number to be displayed.
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US351882A US3882492A (en) | 1973-04-17 | 1973-04-17 | Data signalling systems |
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US351882A US3882492A (en) | 1973-04-17 | 1973-04-17 | Data signalling systems |
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US3882492A true US3882492A (en) | 1975-05-06 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4148007A (en) * | 1977-01-13 | 1979-04-03 | Nissan Motor Company, Limited | Serial-indication fault display system for vehicles |
US4223302A (en) * | 1979-03-05 | 1980-09-16 | Marvel Engineering Company | Conditions monitoring device |
US4358755A (en) * | 1981-03-09 | 1982-11-09 | Simmonds Precision Products, Inc. | Signal selection circuit |
US20030046627A1 (en) * | 2001-08-22 | 2003-03-06 | Ku Joseph Weiyeh | Digital event sampling circuit and method |
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US3483555A (en) * | 1965-05-06 | 1969-12-09 | Telemecanique Electrique | Multiple monitoring system |
US3543267A (en) * | 1969-04-07 | 1970-11-24 | Transmation Inc | Scanning monitor system |
US3613092A (en) * | 1969-04-23 | 1971-10-12 | Robertshaw Controls Co | Sequence counting encoder monitor |
US3644927A (en) * | 1969-05-27 | 1972-02-22 | Gulton Ind | Event monitor system |
US3714646A (en) * | 1970-08-21 | 1973-01-30 | Robertshaw Controls Co | Multiple point alarm system with two state alarm switches |
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1973
- 1973-04-17 US US351882A patent/US3882492A/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US3483555A (en) * | 1965-05-06 | 1969-12-09 | Telemecanique Electrique | Multiple monitoring system |
US3543267A (en) * | 1969-04-07 | 1970-11-24 | Transmation Inc | Scanning monitor system |
US3613092A (en) * | 1969-04-23 | 1971-10-12 | Robertshaw Controls Co | Sequence counting encoder monitor |
US3644927A (en) * | 1969-05-27 | 1972-02-22 | Gulton Ind | Event monitor system |
US3714646A (en) * | 1970-08-21 | 1973-01-30 | Robertshaw Controls Co | Multiple point alarm system with two state alarm switches |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4148007A (en) * | 1977-01-13 | 1979-04-03 | Nissan Motor Company, Limited | Serial-indication fault display system for vehicles |
US4223302A (en) * | 1979-03-05 | 1980-09-16 | Marvel Engineering Company | Conditions monitoring device |
US4358755A (en) * | 1981-03-09 | 1982-11-09 | Simmonds Precision Products, Inc. | Signal selection circuit |
US20030046627A1 (en) * | 2001-08-22 | 2003-03-06 | Ku Joseph Weiyeh | Digital event sampling circuit and method |
US6889349B2 (en) * | 2001-08-22 | 2005-05-03 | Hewlett-Packard Development Company, L.P. | Digital event sampling circuit and method |
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