US3900597A - System and process for deposition of polycrystalline silicon with silane in vacuum - Google Patents

System and process for deposition of polycrystalline silicon with silane in vacuum Download PDF

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US3900597A
US3900597A US426396A US42639673A US3900597A US 3900597 A US3900597 A US 3900597A US 426396 A US426396 A US 426396A US 42639673 A US42639673 A US 42639673A US 3900597 A US3900597 A US 3900597A
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wafers
tube
silicon
silane
furnace
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US426396A
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Jerry L Chruma
Paul G Hilton
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Motorola Solutions Inc
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Motorola Inc
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Priority to GB5447774A priority patent/GB1470614A/en
Priority to JP49145507A priority patent/JPS5095185A/ja
Priority to DE2460211A priority patent/DE2460211B2/en
Priority to CA216,252A priority patent/CA1047850A/en
Priority to FR7500576A priority patent/FR2255707B1/fr
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Priority to HK683/80A priority patent/HK68380A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/006—Apparatus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Definitions

  • the present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum.
  • This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber.
  • the deposition chamber is a hot wall furnace.
  • the deposition zone is kept at as uniform a temperature as possible.
  • the preferred temperature is 600C with a workable range extending from 600C to 700C.
  • the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the dep0Sition rates are different from that rate in the central flattened portion.
  • the boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 21) mils thick.
  • the wafers are placed in the tube from the source input end. At the gas exhaust end. intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon lay-products which pass through the tube.
  • the undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.
  • the prior art method for forming polycrystalline silicon on wafers is run in a hot-wall furnace using nitrogen gas as the carrier gas and silicon tetrahydride as the source of silicon.
  • the furnace is given a heat profile which resembles a ramp beginning at the source end and increasing towards the exhaust end of the tube.
  • Each furnace is independently profiled such that there is a rain-out profile giving the most uniform front-toback. and sideto-side poly deposition as is possible within the system.
  • the quartz boat is placed in the rain-out area of the furnace and wafers are placed side-by-side with one broad surface on the boat such that the deposition of the polycrystalline silicon occurs over the opposing and upturned second major surface. Because of the placement of the wafers on their flat surfaces, approximately l2 to wafers fit within the deposition zone of the furnace at any one time. Normally, two lines of wafers are placed on the boat. The deposition profile of the polycrystalline material on the wafer appears bell-shaped when taken on a straight line across the wafer and perpendicular to the flow of gas. This means that in the center of the wafer, the polycrystalline material is thickest and at the edge of the wafer. it is thinnest. Normally.
  • an average thickness of 4,500 A. is chosen with the thickest material in the center at 6.000 A. and the edge thickness of the material at 3,000 A.
  • the center portion of 6.000 A. thick material can be too thick for the manufacture of devices on that wafer while the 3.000 thick A. of polycrystalline silicon can be too thin for the successful fabrication of devices. Accordingly. some workable devices are fabricated in the intermediate area where the polycrystalline thickness is typically 4.500 A.
  • a third drawback in this system is the wafers are placed into the furnace from the exit end. the brown, powdered silicon material oftentimes drops off the walls onto the wafer as they are being pulled out of or put into the furnace.
  • the prior art process for deposit polycrystalline on wafers has the problems of low throughut; i.c.. l2 to 20 wafers at a time. non-uniformity of deposition of material $1,500 A. across the surface of the wafers. and the wafers are put in from the exit end of the tube subjecting them to the flaking off of powdered silicon material which then falls onto the wafers either prior to polycrystalline silicon deposition or after such polycrystalline silicon deposition.
  • Such deposition of granular silicon renders the adjacent area unfit for the fabrication of devices.
  • the present invention relates generally to a process and product for the deposition of polycrystalline silicon on a substrate in a heated tube, using a gaseous source and a vacuum and. more particularly, the present invention relates to a process and product for depositing polycrystalline silicon on a substrate in a heated tube using silicon tetrahydride as the source gas. and using a vacuum.
  • substrates used in the manufacture of semiconductor devices at temperatures over 600C such as silicon. germanium, sapphire, spine], ceramic. silicon dioxide, and refractory metals such as tungston. molybdenum.
  • FIG. I shows a schematic view of a standard polycrystalline silicon deposition apparatus
  • FIG. 2 shows the temperature profile used in the apparatus shown in FIG. 1;
  • FIG. 3 shows a deposition curve normally associated with the apparatus shown in FIG. 1;
  • FIG. 4 shows the top view of a typical two-inch wafer shaded to show its non-uniform coating of polycrystalline silicon in a system as shown in FIG. 1;
  • FIG. 5 shows a thickness profile taken along the line 5-5 of the wafer shown in FIG. 4 which is perpendicular to the path of the gas flow;
  • FIG. 6 shows a plurality of thickness profiles taken along the line 6-6 of the wafer shown in FIG. 4 which profiles are along the path of the gas flow at different positions in the tube;
  • FIG. 7 shows the schematic view of the apparatus of the present invention
  • FIG. 8 shows the temperature profile of the apparatus shown in FIG. 7;
  • FIG. 9 shows the deposition profile at a selected temperature
  • FIG. 10 identifies a plurality of locations on a wafer which is coated with different thicknesses of polycrystalline silicon when the wafers are closely spaced on the boat;
  • FIG. 1 1 shows the cross sectional profile of the polycrystalline film along the lines RR', 5-8, and T-T' identified in FIG. 10, and the films are formed in the apparatus shown in FIG. 7, wherein the wafers were spaced approximately 3,000 mils apart;
  • FIG. I2 identifies a plurality of locations on a wafer which is coated with a substantially uniform thickness of polycrystalline silicon material over substantially all of the area of the wafer, when the wafer is spaced from the next adjacent wafer approximately 50 mils on centers using mil thick wafers;
  • FIG. 13 shows the cross sectional profile of the thickness of polycrystalline film above the lines XX' and Y-Y' shown in FIG. 12 of a wafer placed in a furnace of FIG. 7 wherein the spacing between adjacent wafers is on 50 mil centers and the wafers are 20 mils thick;
  • FIG. 14 shows the maximum variations of deposited polycrystalline silicon over the wafer surface as a function of the spacing of the wafers.
  • FIG. I there is shown a source I of nitrogen gas which is the carrier gas for the system and a source of 3 of silicon tetrahydride which is a source of silicon.
  • the furnace tube 5 can be heated by resistance heater coils 7 adjusted to give a temperature profile as shown in FIG. 2.
  • This temperature profile has been chosen in combination with the deposition profile as shown in FIG. 3 such that the highest degree of uniformity of polycrystalline deposition is achieved on the wafers 9 which are placed within the fallout range of the tube as indicated by the line 11 shown in FIG. 1.
  • the fallout range is that area of the tube 5 at which the polycrystalline silicon deposits out of the gas flow through the tube.
  • the temperature within the furnace is such as to decompose the silicon tetrahydride causing the silicon to rainout from the gas stream onto the wafers positioned below.
  • the top view of the wafer having polycrystalline silicon deposited thereon shown in FIG. 4 while a cross section through the wafer taken on the lines 5-5 perpendicular to the gas flow is shown in FIG. 5 and shows the variation in thickness across a single representative wafer. The coverage of the wafers is greatest at the center of the wafer and tapers off to a thinnest portion on the edge of the wafers.
  • FIG. 6 shows the variation in thickness of polycrystalline silicon depending on the location of the wafer within the fallout zone 11.
  • this view shows the temperature profile of the prior art deposition tube.
  • the temperature is established as a ramp beginning at 625C at the source end of the fallout zone identified as A.
  • the central portion B of the fallout zone is set at 650C, while the exhaust end C of the fallout zone is held at 675C.
  • this view shows the deposition thickness profile as a measure of the position of the wafer surface in the fallout zone.
  • This figure shows a variation of first a plus 3,000 A. and then a minus 3,000 A. along the fallout zone.
  • the source end of the fallout zone A shows a thickness of 3,000 A
  • the central point B shows a thickness of 6,000 A.
  • the exhaust end shows a thickness of 3,000 A.
  • the profile is a typical profile for a fixed run of 30 minutes. Larger or shorter runs would give different numbers. Also other factors such as flow rates and temperatures would give different numbers from run to run if minute differences in such run parameters occurred.
  • FIG. 4 shows the top view of a typical 2-inch wafer. Larger or smaller size wafers would have similar shaped profiles in all the views, both in the prior art and in the new system.
  • the source gas is flowing from left to right in FIG. 4.
  • FIG. 5 shows the variation of the polycrystalline deposition across a single wafer along a line perpendicular to the source gas flow. This figure shows that the target thickness is identified as X A. This target thickness is exceeded by a figure of approximately 500 A. in the center Q of the wafer, and the actual thickness falls short by about L000 A. at both edges P and R of the wafer.
  • FIG. 6 shows the variation of polycrystalline silicon thickness across the wafer taken along the direction of gas flow at the center N of a wafer and at both the first edge M and trailing edge 0 depending upon the place rnent of the wafer in the fallout zone 1 1.
  • Curve C shows a generally decreasing thickness for a wafer placed at the exhaust end.
  • Curve B shows a concave variation for the center of the fallout zone.
  • Curve A shows a generally increasing thickness for wafers placed at the source end of the tube.
  • a medium thickness of 4,500 A. is selected such that the thickest portion of the wafer along the line 6-6 of FIG. 4 is approximately 6,000 A. thick, FIG. 3, while the thinnest part of the wafer along the line 55 is at 3,000 A. thick, FIG. 3.
  • This variation in thickness guarantees that certain regions of the wafer have an optimum thickness of the polycrystalline mate rial at 4,500 A. With the optimum thickness, certain usable devices can be made on the wafer. However, it has been found that 3,000 A. can be too thin and 6,000 A. can be too thick for usable device performance.
  • FIG. 7 there is shown a schematic view of the present system wherein the preferred source 20 of semiconductor material is silane in a gaseous form.
  • Other sources can be used as SiC1 H SiClH or SiCl...
  • a flowmeter 22 is provided for metering the correct amount of silane gas flow into the tube and over the wafers.
  • a first source 24 of nitrogen is provided along with a nitrogen flowmeter 26. This flow is normally used at a low flow level to backflush any residual silane remaining within the plumbing lines outside of the furnace since silane is explosive when above a certain temperature and exposed to air.
  • a second source 28 of nitrogen is provided along with a flowmeter 30 for measuring the flow of nitrogen from the source 30 into a tube 32.
  • This source of nitrogen is used for rapidly bringing the evacuated tube 32 up to atmospheric pressure as well as aiding in the initial heating of the wafers. While nitrogen is shown, any inert gas normally used in the processing of semiconductor wafers can be used; i.e., argon, etc. Best results are achieved when the source gas 20 is used along during the deposition of the polycrystalline material. All gases flow in the direction of the arrow 34. An end cap 36 is in engagement with the tube to provide a vacuum seal with the tube. The N and SiH, flows enter the tube 32 at the point where the line 38 pases through an appropriate fitting in the end cap 36. A pressure sensor and vacuum gauge 40 is also attached to the input line 38 for reading the pressure and vacuum at this point.
  • the furnace tube 32 is profiled to exhibit a flat temperature profile as shown in FIG. 8 while the deposition profile is shown with reference to FIG. 9.
  • the usable range of the furnace provides a thickness variation of only 500 A. from the front to the back of the furnace. Referring to FIG. 13 briefly, this figure shows that for any one wafer the thickness is substantially constant over the entire wafer surface when the wafers are stood on edge perpendicular to the gas flow.
  • the embodiment shown with reference to FIG. 7 provides this improved thickness control.
  • the profiling temperature for the furnace shown in FIG. 7 can lie within a tmeperature range anywhere from 600-700 for giving practical results. At temperatures lower than 600, the rate of deposition slows to the point where the run takes too long. However, in those instances where a slow deposition rate can be tolerated, temperatures can be lowered to the minimum temperature at which the silane decomposes. At the upper end of the temperature spectrum; i.e.. above 700C, crystalline imperfections are formed on the surface of the wafers. Such imperfections or outgrowths are formed in a deposition atmosphere in the absence of hydrogen.
  • FIG. 8 shows the preferred temperature profile of the furnace 32 wherein the temperature of 600C is established at the source end A, the center B and the exhaust end C of the deposition zone indicated in FIG. 7 by a line 41.
  • FIG. 9 shows the deposition profile of the system shown in FIG. 7 when the tube is heated to 600C and the deposition run lasts for thirty minutes.
  • the variation from the source end A to the exhaust end B of the deposition zone is 500 A. as indicated by a line 42.
  • the deposition profile within the preferred deposition zone of the tube plus a leading and trailing edge is shown by the curve 43. It has been found that the best results are achieved when the maximum deposition thickness is set at the target thickness and the variations occur on the downward side as shown in FIG. 9. Similar deposition curves are achieved using a target thickness other than 4,500 A.
  • optical baffles 45 are attached at the exhaust end 46 of the quartz tube 32 to trap out the powdered silicon at this point.
  • Wafers 47 are placed into a quartz boat 49 and the loaded boat is loaded into the tube through the source end 51 of the quartz tube 32. In this way contact with the deposited powdered silicon material at the exhaust end 45 of the quartz tube is avoided.
  • the silicon boat carrying the wafers is placed within the preferred portion of the deposition curve, as discussed with reference to FIG. 9.
  • the wafers are placed on end and are placed with their broad surface perpendicular to the gas flow.
  • FIG. 14 shows the maximum variation across the wafer as a function of wafer spacing.
  • a preferable open space distance of 30 mils between adjacent surfaces of adjacent wafers has been selected as the preferable distance.
  • a polycrystalline silicon layer is formed on a wafer shown in H0. 12 having a deposition profile as shown in FIG. 13.
  • a line 55 shows the thickness variation in both the X-X' and Y-Y' directions as shown-in FIG. 12. This shows an essentially uniform thickness of polycrystalline silicon material deposited across the major portion of the wafer. It is only at the edge points 61a and 61b of the curve 55 shown in FIG.
  • the thickness of the polycrystalline material across the major surface between the lines is essentially uniform while the difference in thickness from wafer to wafer from the source end of the deposition zone to the exhaust end of the deposition zone differs by a total of 500 A. as shown with reference to FIG. 9.
  • the operation of the system shown in FIG. 7 has the following special steps.
  • the vacuum identified as the preferred vacuum level lies within the range of 600 to 1,600 millitorr.
  • Nitrogen from source 24 is always used to purge any residual SiH, left in the system once the Sil-l is turned off.
  • Nitrogen from the source 28 is used to break the vacuum and establish atmospheric pressure within the tube 32.
  • gaseous silicon source is selected from SiH SiCl H SiCl and SiCl.,.
  • the wafer to be covered with polycrystalline silicon is selected from silcion, germanium, sapphire, spinel, ceramic, silicon dioxide, tungsten and molybdenum.
  • a method of forming a polycrystalline silicon layer upon a plurality of silicon wafers comprising the steps of:
  • l0. ln a method for depositing polycrystalline silicon material onto a wafer which has a layer of silicon dioxide formed on a first major surface of the wafer, and the silicon is obtained from a gaseous silane source flowing through a heated furnace tube, and the tube has a first end into which the gaseous silicon is added to the tube,
  • the tube is further equipped with a second end from which the residual gaseous silane is exhausted.

Abstract

The present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum. This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber. The deposition chamber is a hot wall furnace. The deposition zone is kept at as uniform a temperature as possible. The preferred temperature is 600*C with a workable range extending from 600*C to 700*C. While the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the deposition rates are different from that rate in the central flattened portion. The boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 20 mils thick. The wafers are placed in the tube from the source input end. At the gas exhaust end, intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon by-products which pass through the tube. The undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.

Description

United States Patent 11 1 Chruma et al.
1 Aug. 19, 1975 1 SYSTEM AND PROCESS FOR DEPOSITION OF POLYCRYSTALLINE SILICON WITH SILANE IN VACUUM [75] Inventors: Jerry L. Chruma; Paul G. Hilton.
both of Phoenix, Ariz.
173] Assignee: Motorola, Inc., Chicago. Ill.
[22] Filed: Dec. 19, 1973 [21] Appl. No.: 426,396
OTHER PUBLICATIONS Perrault et a1, IBM Technical Disclosure Bulletin, Vol. 16, No. 3, Aug. 1973, 726.
Primary Examiner-Ralph S. Kendall Axsislam firmniner-Harris A. Pitlick Armrm'y, Age/i1, m Firm-Vincent .1. Rauner; Ellen P.
Trevors PRIOR ART [57] ABSTRACT The present invention is directed to the method and means for depositing polycrystalline silicon from silane in a vacuum. This process contemplates the use of a gas source and a means for assuring a uniform flow of gas into the deposition chamber. The deposition chamber is a hot wall furnace. The deposition zone is kept at as uniform a temperature as possible. The preferred temperature is 600C with a workable range extending from 600C to 700C. While the deposition zone is profiled flat from a temperature point of view, the deposition rate over the length of the tube appears as a flattened curve. This means that at the source and exhaust portions of the tube, the dep0Sition rates are different from that rate in the central flattened portion. The boat upon which the wafers are placed is centered within the center portion of the curve along its flattest portion. Wafers are placed perpendicular to the gas flow with a preferred spacing approximately 50 mils on center when using wafers 21) mils thick. The wafers are placed in the tube from the source input end. At the gas exhaust end. intermediate the tube and the vacuum pump, is an optical baffle. The function of the optical baffle is to collect the undeposited silane material and silicon lay-products which pass through the tube. The undeposited silane material appears in the form of a brown dust which is granular silicon and silicon monoxide. This granular material forms around the exit end of the tube and in the baffle.
13 Claims, 14 Drawing Figures PATENTEBAUGISISTB 3,900,597
SJLZI 1 [1F 4 II A a PM.
/oo%-o/ ooooooo FM- !3 7 5 PRIORART F/g. M4
650C-- GAS FLOW saws-- 6 I I I I I I I I 1* A B C PRIORART Fla 2 PRIOR ART Fig.4 600021 I'I'I'I'I'I'F A B C PRIOR ART PATENTED AUG 1 91975 S. QT 2 SF *2 loooli 4- x+ x0003 xfi x3 H0003 X-IOOOK L I l l I [M IN IO 1P o R J PRIOR ART 2" WAFER PRIOR ART 2 WAFER Fig.6 Fig.5
GAUGE as 34 47 32 45 4 LA LJ llllllllli I I SIJ 49 4s l VACUUM F 26 PUMP M f 22 24 44 M Hg. 7
PATENTEDAUG 1 9:975 900 597 600C Hg. 8
I I I I l l I I I I 1 I A B c JIHHIIIIIIIIIIIIIL I L J 1 Fig.9
SR IL'VT 4000 A R 3000& V 2000K I000 13 I I I k; Y J
2" WAFER PATENTEDAUGISIQYS 3,900,597
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x-sooii l L l I I I I I M l LS WAFER SPACI NG Fig. /4
SYSTEM AND PROCESS FOR DEPOSITION OF POLYCRYSTALLINE SILICON WITH SILANE IN VACUUM BACKGROUND OF THE INVENTION The prior art method for forming polycrystalline silicon on wafers is run in a hot-wall furnace using nitrogen gas as the carrier gas and silicon tetrahydride as the source of silicon. The furnace is given a heat profile which resembles a ramp beginning at the source end and increasing towards the exhaust end of the tube. Each furnace is independently profiled such that there is a rain-out profile giving the most uniform front-toback. and sideto-side poly deposition as is possible within the system.
According to the prior art practice, the quartz boat is placed in the rain-out area of the furnace and wafers are placed side-by-side with one broad surface on the boat such that the deposition of the polycrystalline silicon occurs over the opposing and upturned second major surface. Because of the placement of the wafers on their flat surfaces, approximately l2 to wafers fit within the deposition zone of the furnace at any one time. Normally, two lines of wafers are placed on the boat. The deposition profile of the polycrystalline material on the wafer appears bell-shaped when taken on a straight line across the wafer and perpendicular to the flow of gas. This means that in the center of the wafer, the polycrystalline material is thickest and at the edge of the wafer. it is thinnest. Normally. an average thickness of 4,500 A. is chosen with the thickest material in the center at 6.000 A. and the edge thickness of the material at 3,000 A. In practice. the center portion of 6.000 A. thick material can be too thick for the manufacture of devices on that wafer while the 3.000 thick A. of polycrystalline silicon can be too thin for the successful fabrication of devices. Accordingly. some workable devices are fabricated in the intermediate area where the polycrystalline thickness is typically 4.500 A. A third drawback in this system is the wafers are placed into the furnace from the exit end. the brown, powdered silicon material oftentimes drops off the walls onto the wafer as they are being pulled out of or put into the furnace. The buildup of such powdered silicon material on the quartz tube is so rapid that normally a maximum of ten to twenty runs can be made using the same quartz tubev When the quartz tube is pulled from the furnace to be cleaned, the coefficient of expansion between the quartz and the silicon is so great that the quartz tube breaks and a new center section must be fused with the unbroken end sections as to reuse these two end portions of the tube.
In summary. the prior art process for deposit polycrystalline on wafers has the problems of low throughut; i.c.. l2 to 20 wafers at a time. non-uniformity of deposition of material $1,500 A. across the surface of the wafers. and the wafers are put in from the exit end of the tube subjecting them to the flaking off of powdered silicon material which then falls onto the wafers either prior to polycrystalline silicon deposition or after such polycrystalline silicon deposition. Such deposition of granular silicon renders the adjacent area unfit for the fabrication of devices.
SUMMARY OF THF. INVENTION The present invention relates generally to a process and product for the deposition of polycrystalline silicon on a substrate in a heated tube, using a gaseous source and a vacuum and. more particularly, the present invention relates to a process and product for depositing polycrystalline silicon on a substrate in a heated tube using silicon tetrahydride as the source gas. and using a vacuum.
It is an object of the present invention to provide a new improved method for depositing polycrystalline silicon on a substrate using a heated tube and a vacuum.
It is an additional object of the present invention to provide a hot-wall furnace tube having a flat temperature profile in the hot zone of the tube which results in the deposition of a uniform thickness of polycrystalline silicon over the major portion of the surface of the wafer.
It is still a further object of the present invention to provide a method for depositing polycrystalline silicon from silane in a hot-wall furnace tube with improved uniformity as compared to that presently possible.
It is another object of the present invention to pro vide a means and a method for depositing polycrystalline silicon from silane at a uniform rate over the wafer with a tolerance of better than 500 A. from edge to edge of a single wafer.
It is still a further object of the present invention to provide a method for depositing polycrystalline silicon on wafers within a hot-wall furnace tube for increasing the throughput capacity of the furnace.
It is a further object of the present inventon to provide a method for depositing polycrystalline silicon on wafers in a hot-wall tube such that the major surface of the wafers contain a uniform thickness of the polycrystalline silicon over as great a region as possible.
It is another object of the present invention to provide a method for depositing polycrystalline silicon on wafers in a furnace wherein the wafers are placed on edge and their broad major surfaces are then placed perpendicular to the flow of the source gas and the wafers are placed closer together than previously thought possible.
It is an additional object of the present invention to provide a method for depositing polycrystalline silicon on many different substrates used in the manufacture of semiconductor devices at temperatures over 600C. such as silicon. germanium, sapphire, spine], ceramic. silicon dioxide, and refractory metals such as tungston. molybdenum.
It is a still further object of the present invention to provide a method of depositing polycrystalline silicon in a heated tube, which method is independent of the means for heating the tube and heating means such as RF, resistance or radiant heat can be used.
It is another object of the present invention to provide a method for depositing polycrystalline silicon on a substrate using several gas sources such as silane. SiCl H SiClH and SiCh.
It is a further object of the present invention to provide a method for depositing polycrystalline silicon in a heated evacuated tube under a vacuum on a substrate and using a gaseous source, wherein teh spacing of the wafers is minimized for increasing the throughput of the method.
DESCRIPTION OF THE FIGURES FIG. I shows a schematic view of a standard polycrystalline silicon deposition apparatus;
FIG. 2 shows the temperature profile used in the apparatus shown in FIG. 1;
FIG. 3 shows a deposition curve normally associated with the apparatus shown in FIG. 1;
FIG. 4 shows the top view of a typical two-inch wafer shaded to show its non-uniform coating of polycrystalline silicon in a system as shown in FIG. 1;
FIG. 5 shows a thickness profile taken along the line 5-5 of the wafer shown in FIG. 4 which is perpendicular to the path of the gas flow;
FIG. 6 shows a plurality of thickness profiles taken along the line 6-6 of the wafer shown in FIG. 4 which profiles are along the path of the gas flow at different positions in the tube;
FIG. 7 shows the schematic view of the apparatus of the present invention;
FIG. 8 shows the temperature profile of the apparatus shown in FIG. 7;
FIG. 9 shows the deposition profile at a selected temperature;
FIG. 10 identifies a plurality of locations on a wafer which is coated with different thicknesses of polycrystalline silicon when the wafers are closely spaced on the boat;
FIG. 1 1 shows the cross sectional profile of the polycrystalline film along the lines RR', 5-8, and T-T' identified in FIG. 10, and the films are formed in the apparatus shown in FIG. 7, wherein the wafers were spaced approximately 3,000 mils apart;
FIG. I2 identifies a plurality of locations on a wafer which is coated with a substantially uniform thickness of polycrystalline silicon material over substantially all of the area of the wafer, when the wafer is spaced from the next adjacent wafer approximately 50 mils on centers using mil thick wafers;
FIG. 13 shows the cross sectional profile of the thickness of polycrystalline film above the lines XX' and Y-Y' shown in FIG. 12 of a wafer placed in a furnace of FIG. 7 wherein the spacing between adjacent wafers is on 50 mil centers and the wafers are 20 mils thick;
FIG. 14 shows the maximum variations of deposited polycrystalline silicon over the wafer surface as a function of the spacing of the wafers.
BRIEF DESCRIPTION OF THE INVENTION In the prior art system of depositing polycrystalline silicon, as shown with reference to FIG. I, there is shown a source I of nitrogen gas which is the carrier gas for the system and a source of 3 of silicon tetrahydride which is a source of silicon. The furnace tube 5 can be heated by resistance heater coils 7 adjusted to give a temperature profile as shown in FIG. 2. This temperature profile has been chosen in combination with the deposition profile as shown in FIG. 3 such that the highest degree of uniformity of polycrystalline deposition is achieved on the wafers 9 which are placed within the fallout range of the tube as indicated by the line 11 shown in FIG. 1. The fallout range is that area of the tube 5 at which the polycrystalline silicon deposits out of the gas flow through the tube. The temperature within the furnace is such as to decompose the silicon tetrahydride causing the silicon to rainout from the gas stream onto the wafers positioned below. The top view of the wafer having polycrystalline silicon deposited thereon shown in FIG. 4 while a cross section through the wafer taken on the lines 5-5 perpendicular to the gas flow is shown in FIG. 5 and shows the variation in thickness across a single representative wafer. The coverage of the wafers is greatest at the center of the wafer and tapers off to a thinnest portion on the edge of the wafers. FIG. 6 shows the variation in thickness of polycrystalline silicon depending on the location of the wafer within the fallout zone 11.
Referring again to FIG. 2, this view shows the temperature profile of the prior art deposition tube. The temperature is established as a ramp beginning at 625C at the source end of the fallout zone identified as A. The central portion B of the fallout zone is set at 650C, while the exhaust end C of the fallout zone is held at 675C.
Referring again to FIG. 3, this view shows the deposition thickness profile as a measure of the position of the wafer surface in the fallout zone. This figure shows a variation of first a plus 3,000 A. and then a minus 3,000 A. along the fallout zone. The source end of the fallout zone A shows a thickness of 3,000 A, while the central point B shows a thickness of 6,000 A. and the exhaust end shows a thickness of 3,000 A. While it is possible to build devices with the thickness of polycrystalline silicon over the entire range as shown in FIG. 3, it is impractical from a commercial viewpoint to identify and sort the individual die according to thickness. It is not uncommon to have several hundred die to a wafer. The actual identification and sorting of these die is too costly. Again the profile is a typical profile for a fixed run of 30 minutes. Larger or shorter runs would give different numbers. Also other factors such as flow rates and temperatures would give different numbers from run to run if minute differences in such run parameters occurred.
FIG. 4 shows the top view of a typical 2-inch wafer. Larger or smaller size wafers would have similar shaped profiles in all the views, both in the prior art and in the new system. The source gas is flowing from left to right in FIG. 4.
FIG. 5 shows the variation of the polycrystalline deposition across a single wafer along a line perpendicular to the source gas flow. This figure shows that the target thickness is identified as X A. This target thickness is exceeded by a figure of approximately 500 A. in the center Q of the wafer, and the actual thickness falls short by about L000 A. at both edges P and R of the wafer.
FIG. 6 shows the variation of polycrystalline silicon thickness across the wafer taken along the direction of gas flow at the center N of a wafer and at both the first edge M and trailing edge 0 depending upon the place rnent of the wafer in the fallout zone 1 1. Curve C shows a generally decreasing thickness for a wafer placed at the exhaust end. Curve B shows a concave variation for the center of the fallout zone. Curve A shows a generally increasing thickness for wafers placed at the source end of the tube.
In operation, a medium thickness of 4,500 A. is selected such that the thickest portion of the wafer along the line 6-6 of FIG. 4 is approximately 6,000 A. thick, FIG. 3, while the thinnest part of the wafer along the line 55 is at 3,000 A. thick, FIG. 3. This variation in thickness guarantees that certain regions of the wafer have an optimum thickness of the polycrystalline mate rial at 4,500 A. With the optimum thickness, certain usable devices can be made on the wafer. However, it has been found that 3,000 A. can be too thin and 6,000 A. can be too thick for usable device performance.
Accordingly, it is desirable to form a polycrystalline layer with a more optimum thickness over a greater portion of the wafer. In the system shown in FIG. I only l2 to wafers can be passed through the system at one time because of the size of the tube and the size of the fallout zone. Since the wafers must lie on a major surface with the polycrystalline material raining out from the gas stream upon the upper or opposite major surface of a substrate, the physical limitation of the system is l2 to 20 wafers.
Another drawback on the system shown with reference to FIG. 1 is the fact that the wafers are put in through the exhaust end 13 of the tube. When the wafers are being put in, as well as when the wafers are taken out, some of the powdered silicon material flecks off of the walls of the tube at the end 13 and become deposited on the wafers. This means that any polycrystalline material grown over that powdered piece of silicon would be unsuitable for the formation of semiconductor devices. Also, any flecks of powdered silicon falling on a newly grown polycrystalline layer adversely affects the use of that area for an active device.
Referring to FIG. 7 there is shown a schematic view of the present system wherein the preferred source 20 of semiconductor material is silane in a gaseous form. Other sources can be used as SiC1 H SiClH or SiCl... A flowmeter 22 is provided for metering the correct amount of silane gas flow into the tube and over the wafers. A first source 24 of nitrogen is provided along with a nitrogen flowmeter 26. This flow is normally used at a low flow level to backflush any residual silane remaining within the plumbing lines outside of the furnace since silane is explosive when above a certain temperature and exposed to air. A second source 28 of nitrogen is provided along with a flowmeter 30 for measuring the flow of nitrogen from the source 30 into a tube 32. This source of nitrogen is used for rapidly bringing the evacuated tube 32 up to atmospheric pressure as well as aiding in the initial heating of the wafers. While nitrogen is shown, any inert gas normally used in the processing of semiconductor wafers can be used; i.e., argon, etc. Best results are achieved when the source gas 20 is used along during the deposition of the polycrystalline material. All gases flow in the direction of the arrow 34. An end cap 36 is in engagement with the tube to provide a vacuum seal with the tube. The N and SiH, flows enter the tube 32 at the point where the line 38 pases through an appropriate fitting in the end cap 36. A pressure sensor and vacuum gauge 40 is also attached to the input line 38 for reading the pressure and vacuum at this point. The furnace tube 32 is profiled to exhibit a flat temperature profile as shown in FIG. 8 while the deposition profile is shown with reference to FIG. 9. This means that the flattened curve shown in FIG. 9 represents the variation in the thickness of polycrystalline silicon material deposited on a wafer when positioned at any location within the entire heated zone of the furnace. The usable range of the furnace provides a thickness variation of only 500 A. from the front to the back of the furnace. Referring to FIG. 13 briefly, this figure shows that for any one wafer the thickness is substantially constant over the entire wafer surface when the wafers are stood on edge perpendicular to the gas flow. The embodiment shown with reference to FIG. 7 provides this improved thickness control.
The profiling temperature for the furnace shown in FIG. 7 can lie within a tmeperature range anywhere from 600-700 for giving practical results. At temperatures lower than 600, the rate of deposition slows to the point where the run takes too long. However, in those instances where a slow deposition rate can be tolerated, temperatures can be lowered to the minimum temperature at which the silane decomposes. At the upper end of the temperature spectrum; i.e.. above 700C, crystalline imperfections are formed on the surface of the wafers. Such imperfections or outgrowths are formed in a deposition atmosphere in the absence of hydrogen. FIG. 8 shows the preferred temperature profile of the furnace 32 wherein the temperature of 600C is established at the source end A, the center B and the exhaust end C of the deposition zone indicated in FIG. 7 by a line 41.
FIG. 9 shows the deposition profile of the system shown in FIG. 7 when the tube is heated to 600C and the deposition run lasts for thirty minutes. The variation from the source end A to the exhaust end B of the deposition zone is 500 A. as indicated by a line 42. The deposition profile within the preferred deposition zone of the tube plus a leading and trailing edge is shown by the curve 43. It has been found that the best results are achieved when the maximum deposition thickness is set at the target thickness and the variations occur on the downward side as shown in FIG. 9. Similar deposition curves are achieved using a target thickness other than 4,500 A.
In some early experiments a cold trap cooled by liquid nitrogen was used to remove the silane before it was vented into the vacuum pump 44 shown in FIG. 7. This was to prevent damage to the vacuum apparatus. However, the cold trap was allowed to wann after the deposition run was completed; it was damaged by the spontaneous burning of the silane as it warmed and became exposed to air.
Accordingly, optical baffles 45 are attached at the exhaust end 46 of the quartz tube 32 to trap out the powdered silicon at this point. Wafers 47 are placed into a quartz boat 49 and the loaded boat is loaded into the tube through the source end 51 of the quartz tube 32. In this way contact with the deposited powdered silicon material at the exhaust end 45 of the quartz tube is avoided. The silicon boat carrying the wafers is placed within the preferred portion of the deposition curve, as discussed with reference to FIG. 9. The wafers are placed on end and are placed with their broad surface perpendicular to the gas flow.
In earlier experiments, wafers were placed at greater distances and wafers were manufactured having the top view as shown in FIG. 10. The upper portion of the wafer indicated by the line S-S has a uniform amount of material deposited thereon, as shown by a comparison curve 8-8 in FIG. 11, but the lower portion indicated by the line RR was substantially non-uniform and unusable as shown by the comparison curve RR in FIG. 11. Additionally, a thickness variation also oc curred from the top to the bottom of the wafer as indicated by the line TT in FIGS. 10 and II. The spacing which gave the results illustrated in FIG. I] was 3,000 mils. It should be kept in mind that the length of the spacing between wafers is that distances between midpoints of the thickness of adjacent wafers. When two wafers are 20 mils thick and the spacing is given as 50 mils, there is actually a 30 mil open area between the rear surface of the first wafer and the front surface of the next wafer. Accordingly, if thicker wafers are used, the spacings would change also. This change would only be significant at the upper and lower limits as in between it does not matter. It is recommended that the actual spacing of 30 mils from surface to surface should not be made smaller. At the upper limit, minimum acceptable depositions on the top half of wafers were achieved at actual back surface to front surface spacing of 2,980 mils.
Accordingly, many experiments were run to ascertain the optimum spacing of the wafers side-by-side. This information is shown in FIG. 14 by the line 53. This curve shows the maximum variation across the wafer as a function of wafer spacing. A preferable open space distance of 30 mils between adjacent surfaces of adjacent wafers has been selected as the preferable distance. A polycrystalline silicon layer is formed on a wafer shown in H0. 12 having a deposition profile as shown in FIG. 13. A line 55 shows the thickness variation in both the X-X' and Y-Y' directions as shown-in FIG. 12. This shows an essentially uniform thickness of polycrystalline silicon material deposited across the major portion of the wafer. It is only at the edge points 61a and 61b of the curve 55 shown in FIG. 13 that a slight increase in thickness is found. It should be emphasized that the thickness of the polycrystalline material across the major surface between the lines is essentially uniform while the difference in thickness from wafer to wafer from the source end of the deposition zone to the exhaust end of the deposition zone differs by a total of 500 A. as shown with reference to FIG. 9.
In the improved system as shown with reference to H0. 7, approximately 250 wafers can be placed on a 12-inch boat. This is a throughput greater than ID to 1 as compared with the prior art method of forming polycrystalline silicon material.
The operation of the system shown in FIG. 7 has the following special steps. The vacuum identified as the preferred vacuum level lies within the range of 600 to 1,600 millitorr. Nitrogen from source 24 is always used to purge any residual SiH, left in the system once the Sil-l is turned off. Nitrogen from the source 28 is used to break the vacuum and establish atmospheric pressure within the tube 32.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
1. In a method for depositing polycrystalline silicon material onto a wafer from a gaseous silicon source flowing through a furnace tube, and the furnace is provided with heating means, and is further provided with a first end through which the gaseous silicon source is admitted into the tube, and is further provided with a second end from which the residual gaseous silicon is exhausted, the improvement comprising the steps of:
introducing a plurality of wafers into the furnace through the first end;
placing said plurality of wafers into the stream of gaseous silicon such that the broad surface of each of said wafers upon which the polycrystalline material is to deposit is placed perpendicular to the direction of the gas flow;
spacing the wafers a minimum of 30 mils between adjacent surfaces;
heating the wafers to a temperature under 700C for a time sufficient to grow the desired thickness of polycrystalline silicon material; establishing a vacuum at the exhaust end of the tube for drawing the gaseous silicon over the wafers;
continuing the flow of the gaseous silicon for a predetermined period and then closing off the flow of said gaseous silicon; and
withdrawing said wafers from the furnace by said first end.
2. The method recited in claim 1 wherein the furnace tube and wafers are heated to the predetermined operating temperature before the gaseous silicon is passed into the furnace under the influence of the vacuum.
3. The method recited in claim 1, wherein the spacing of the wafers lies between 50 to 3,000 mils on center.
4. The method recited in claim 1 wherein the gaseous silicon source is selected from SiH SiCl H SiCl and SiCl.,.
5. The method recited in claim 1 wherein the wafer to be covered with polycrystalline silicon is selected from silcion, germanium, sapphire, spinel, ceramic, silicon dioxide, tungsten and molybdenum.
6. The method recited in claim I, and further includes the step of:
providing a baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
7. The method for depositing polycrystalline silicon as recited in claim 1, whrein after the step of closing off the flow of silane, the method further includes the step of:
flushing with an inert gas any residual gaseous silane which remains between the silicon source and the vacuum source.
8. The method for depositing polycrystalline silicon as recited in claim 1, wherein after the step of closing off the flow of gaseous silicon, the method further includes the step of:
establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the tube.
9. A method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprising the steps of:
placing a plurality of silicon wafers in a closed container;
establishing a uniform temperature throughout a portion of the closed container, said temperature being less than 700C, and said wafers being placed within the uniform temperature portion of the container;
placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils; and
passing a gas stream of silane over the heated Wafers under the motivation of a vacuum established between the range of 600 to 1,600 millitorr.
l0. ln a method for depositing polycrystalline silicon material onto a wafer which has a layer of silicon dioxide formed on a first major surface of the wafer, and the silicon is obtained from a gaseous silane source flowing through a heated furnace tube, and the tube has a first end into which the gaseous silicon is added to the tube,
and the tube is further equipped with a second end from which the residual gaseous silane is exhausted. the improvement comprising the steps of:
introducing a plurality of wafers into the furnace through the first end of the furnace, and said wafers being oriented such that the first major surface of each wafer faces the first end of the furnace tube and is perpendicular to the direction of gas flow through the furnace tube, and said wafers are spaced more than 30 mils between adjacent surfaces; establishing a vacuum at the exhaust end of the tube to a level within the range of 600 to 1,600 millitorr for drawing gases through the furnace; introducing a flow of an inert gas into the tube while heating the wafers to a predetermined temperature under 700C; upon reaching the predetermined temperature, shutting off the flow of nitrogen and exposing the silane to the efi'ects of the vacuum; continuing the flow of silane for a predetermined period and then closing off the flow of silane; and
withdrawing the wafers from the furnace by said first end.
1 l. The method for depositing polycrystalline silicon as recited in claim 10, wherein after the step of closing off the flow of silane, the method further includes the step of:
flushing with an inert gas any residual silane which remains between the silane source and the source of vacuum.
12. The method for depositing polycrystalline silicon as recited in claim 10, wherein after the step of closing off the flow of silane, the method further includes the step of:
establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the furnace tube.
13. The method for depositing polycrystalline silicon as recited in claim 10, and further includes the step of:
providing a baffie at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.

Claims (13)

1. IN A METHOD FOR DEPOSITING POLYCRYSTALLINE SILICON MATERIAL ONTO A WAFER FROM A GASEOUS SILICON SOURCE FLOWING THROUGH A FURNACE TUBE, AND THE FURANCE IS PROVIDED WITH HEATING MEANS, AND IS FURTHER PROVIDED WITH A FIRST END THROUGH WHICH THE GASEOUS SILICON SOURCE IS ADMITTED INTO THE TUBE, AND IS FURTHER PROVIDED WITH A SECOND END FROM WHICH THE RESIDUAL GASEOUS SILICON IS EXHAUSTED, THE IMPROVEMENT COMPRISING THE STEPS OF: INTRODUCING A PLURALITY OF WAFERS INTO THE FURNACE THROUGH THE FIRST END, PLACING SAID PLURALITY OF WAFERS INTO THE STREAM OF GASEOUS SILICON SUCH THAT THE BROAD SURFACE OF EACH OF SAID WAFERS UPON WHICH THE POLYCRYSTALLINE MATERIAL IS TO DEPOSIT IS PLACED PERPENDICULAR TO THE DIRECTION OF THE GAS FLOW, SPACING THE WAFERS A MINIMUM OF 30 MILS BETWEEN ADJACENT SURFACE, HEATING THE WAFERS TO A TEMPERATURE UNDER 700*C FOR A TIME SUFFICIENT TO GROW THE DESIRED THICKNESS OF POLYCRYSTALLINE SILICON MATERIAL, ESTABLISHING A VACUUM AT THE EXHAUST END OF THE TUBE FOR DRAWING THE GASEOUS SILICON OVER THE WAFERS, CONTINUING THE FLOW OF THE GASEOUS SILICON FOR A PREDETERMINED PERIOD AND THEN CLOSING OFF THE FLOW OF SAID GASEOUS SILICON, AND WITHDRAWING SAID WAFERS FROM THE FURNACE BY SAID FIRST END.
2. The method recited in claim 1 wherein the furnace tube and wafers are heated to the predetermined operating temperature before the gaseous silicon is passed into the furnace under the influence of the vacuum.
3. The method recited in claim 1, wherein the spacing of the wafers lies between 50 to 3,000 mils on center.
4. The method recited in claim 1 wherein the gaseous silicon source is selected from SiH4, SiCl2H2, SiCl3 and SiCl4.
5. The method recited in claim 1 wherein the wafer to be covered with polycrystalline silicon Is selected from silcion, germanium, sapphire, spinel, ceramic, silicon dioxide, tungsten and molybdenum.
6. The method recited in claim 1, and further includes the step of: providing a baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
7. The method for depositing polycrystalline silicon as recited in claim 1, whrein after the step of closing off the flow of silane, the method further includes the step of: flushing with an inert gas any residual gaseous silane which remains between the silicon source and the vacuum source.
8. The method for depositing polycrystalline silicon as recited in claim 1, wherein after the step of closing off the flow of gaseous silicon, the method further includes the step of: establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the tube.
9. A method of forming a polycrystalline silicon layer upon a plurality of silicon wafers, comprising the steps of: placing a plurality of silicon wafers in a closed container; establishing a uniform temperature throughout a portion of the closed container, said temperature being less than 700*C, and said wafers being placed within the uniform temperature portion of the container; placing the wafers on end perpendicular to the flow of gas and spaced one from the other by a distance greater than 30 mils; and passing a gas stream of silane over the heated wafers under the motivation of a vacuum established between the range of 600 to 1,600 millitorr.
10. In a method for depositing polycrystalline silicon material onto a wafer which has a layer of silicon dioxide formed on a first major surface of the wafer, and the silicon is obtained from a gaseous silane source flowing through a heated furnace tube, and the tube has a first end into which the gaseous silicon is added to the tube, and the tube is further equipped with a second end from which the residual gaseous silane is exhausted, the improvement comprising the steps of: introducing a plurality of wafers into the furnace through the first end of the furnace, and said wafers being oriented such that the first major surface of each wafer faces the first end of the furnace tube and is perpendicular to the direction of gas flow through the furnace tube, and said wafers are spaced more than 30 mils between adjacent surfaces; establishing a vacuum at the exhaust end of the tube to a level within the range of 600 to 1,600 millitorr for drawing gases through the furnace; introducing a flow of an inert gas into the tube while heating the wafers to a predetermined temperature under 700*C; upon reaching the predetermined temperature, shutting off the flow of nitrogen and exposing the silane to the effects of the vacuum; continuing the flow of silane for a predetermined period and then closing off the flow of silane; and withdrawing the wafers from the furnace by said first end.
11. The method for depositing polycrystalline silicon as recited in claim 10, wherein after the step of closing off the flow of silane, the method further includes the step of: flushing with an inert gas any residual silane which remains between the silane source and the source of vacuum.
12. The method for depositing polycrystalline silicon as recited in claim 10, wherein after the step of closing off the flow of silane, the method further includes the step of: establishing atmospheric pressure within the furnace tube by deactivating the vacuum source and introducing an inert gas into the furnace tube.
13. The method for depositing polycrystalline silicon as recited in claim 10, and further includes the step of: providing a baffle at the exhaust end of the furnace tube for removing residual silane prior to entering the vacuum pump.
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DE2460211A DE2460211B2 (en) 1973-12-19 1974-12-19 Process for the chemical deposition of polycrystalline silicon from the gas phase
CA216,252A CA1047850A (en) 1973-12-19 1974-12-19 System and process for deposition of polycrystalline silicon with silane in vacuum
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US20080038936A1 (en) * 2002-07-19 2008-02-14 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US20080047877A1 (en) * 2001-08-07 2008-02-28 Freissle Manfred Franz A Screening Arrangement
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films
US9443730B2 (en) 2014-07-18 2016-09-13 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US9837271B2 (en) 2014-07-18 2017-12-05 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US10460932B2 (en) 2017-03-31 2019-10-29 Asm Ip Holding B.V. Semiconductor device with amorphous silicon filled gaps and methods for forming

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US4082865A (en) * 1976-11-19 1978-04-04 Rca Corporation Method for chemical vapor deposition
US4164436A (en) * 1977-07-22 1979-08-14 Hitachi, Ltd. Process for preparation of semiconductor devices utilizing a two-step polycrystalline deposition technique to form a diffusion source
US4449037A (en) * 1978-10-31 1984-05-15 Fujitsu Limited Method and apparatus for heating semiconductor wafers
US4203387A (en) * 1978-12-28 1980-05-20 General Signal Corporation Cage for low pressure silicon dioxide deposition reactors
US4263087A (en) * 1979-02-19 1981-04-21 Fujitsu Limited Process for producing epitaxial layers
US4367768A (en) * 1979-02-24 1983-01-11 Heraeus Quarzschmelze Gmbh Refractory protective tube for the heat treatment of semiconductor components
US4228004A (en) * 1979-04-12 1980-10-14 Thermco Products Corporation Method and apparatus for removal of by-products of chemical vapor deposition from oil for vacuum pump
US4388342A (en) * 1979-05-29 1983-06-14 Hitachi, Ltd. Method for chemical vapor deposition
US4263336A (en) * 1979-11-23 1981-04-21 Motorola, Inc. Reduced pressure induction heated reactor and method
US4315968A (en) * 1980-02-06 1982-02-16 Avco Corporation Silicon coated silicon carbide filaments and method
US4444812A (en) * 1980-07-28 1984-04-24 Monsanto Company Combination gas curtains for continuous chemical vapor deposition production of silicon bodies
US4509456A (en) * 1981-07-28 1985-04-09 Veb Zentrum Fur Forschung Und Technologie Mikroelektronik Apparatus for guiding gas for LP CVD processes in a tube reactor
DE3235503A1 (en) * 1981-11-12 1983-05-19 Advanced Semiconductor Materials America, Inc., 85040 Phoenix, Ariz. IMPROVED DEPOSIT OF SILICON FROM A PLASMA
US4547404A (en) * 1982-08-27 1985-10-15 Anicon, Inc. Chemical vapor deposition process
US4489103A (en) * 1983-09-16 1984-12-18 Rca Corporation SIPOS Deposition method
US4556584A (en) * 1984-05-03 1985-12-03 Btu Engineering Corporation Method for providing substantially waste-free chemical vapor deposition of thin-film on semiconductor substrates
US4734297A (en) * 1984-10-30 1988-03-29 Rhone-Poulenc Specialites Chimiques Production of shaped articles of ultra-pure silicon
US4744863A (en) * 1985-04-26 1988-05-17 Wisconsin Alumni Research Foundation Sealed cavity semiconductor pressure transducers and method of producing the same
US4853669A (en) * 1985-04-26 1989-08-01 Wisconsin Alumni Research Foundation Sealed cavity semiconductor pressure transducers and method of producing the same
US4597160A (en) * 1985-08-09 1986-07-01 Rca Corporation Method of fabricating a polysilicon transistor with a high carrier mobility
US5026574A (en) * 1986-03-19 1991-06-25 The General Electric Company, P.L.C. Chemical vapor deposition process for depositing large-grain polysilicon films
US5298452A (en) * 1986-09-12 1994-03-29 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US5906680A (en) * 1986-09-12 1999-05-25 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US4897360A (en) * 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
US5181964A (en) * 1990-06-13 1993-01-26 International Business Machines Corporation Single ended ultra-high vacuum chemical vapor deposition (uhv/cvd) reactor
US5112773A (en) * 1991-04-10 1992-05-12 Micron Technology, Inc. Methods for texturizing polysilicon utilizing gas phase nucleation
US5874129A (en) * 1991-08-09 1999-02-23 Applied Materials, Inc. Low temperature, high pressure silicon deposition method
US5614257A (en) * 1991-08-09 1997-03-25 Applied Materials, Inc Low temperature, high pressure silicon deposition method
US5607724A (en) * 1991-08-09 1997-03-04 Applied Materials, Inc. Low temperature high pressure silicon deposition method
US5695819A (en) * 1991-08-09 1997-12-09 Applied Materials, Inc. Method of enhancing step coverage of polysilicon deposits
US5753559A (en) * 1996-01-16 1998-05-19 United Microelectronics Corporation Method for growing hemispherical grain silicon
US20080003763A1 (en) * 1998-03-06 2008-01-03 Asm America, Inc. Method of depositing silicon with high step coverage
US20030129811A1 (en) * 1998-03-06 2003-07-10 Ivo Raaijmakers Method of depositing silicon with high step coverage
US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
US6465045B1 (en) 1998-10-06 2002-10-15 Case Western Reserve University Low stress polysilicon film and method for producing same
US6610361B1 (en) 1998-10-06 2003-08-26 Case Western Reserve University Multi-layer assemblies with predetermined stress profile and method for producing same
US6268068B1 (en) 1998-10-06 2001-07-31 Case Western Reserve University Low stress polysilicon film and method for producing same
US6564810B1 (en) 2000-03-28 2003-05-20 Asm America Cleaning of semiconductor processing chambers
US6666924B1 (en) 2000-03-28 2003-12-23 Asm America Reaction chamber with decreased wall deposition
US6708700B2 (en) 2000-03-28 2004-03-23 Asm America Cleaning of semiconductor processing chambers
US8360001B2 (en) 2001-02-12 2013-01-29 Asm America, Inc. Process for deposition of semiconductor films
US20050250302A1 (en) * 2001-02-12 2005-11-10 Todd Michael A Thin films and methods of making them
US7026219B2 (en) 2001-02-12 2006-04-11 Asm America, Inc. Integration of high k gate dielectric
US8067297B2 (en) 2001-02-12 2011-11-29 Asm America, Inc. Process for deposition of semiconductor films
US20070102790A1 (en) * 2001-02-12 2007-05-10 Todd Michael A Process for deposition of semiconductor films
US7285500B2 (en) * 2001-02-12 2007-10-23 Asm America, Inc. Thin films and methods of making them
US20050233529A1 (en) * 2001-02-12 2005-10-20 Pomarede Christophe F Integration of high k gate dielectric
US7893433B2 (en) 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US7547615B2 (en) 2001-02-12 2009-06-16 Asm America, Inc. Deposition over mixed substrates using trisilane
US7790556B2 (en) 2001-02-12 2010-09-07 Asm America, Inc. Integration of high k gate dielectric
US20080047877A1 (en) * 2001-08-07 2008-02-28 Freissle Manfred Franz A Screening Arrangement
US7651953B2 (en) 2002-07-19 2010-01-26 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US20090311857A1 (en) * 2002-07-19 2009-12-17 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US20080038936A1 (en) * 2002-07-19 2008-02-14 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US7964513B2 (en) 2002-07-19 2011-06-21 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films
US7141095B2 (en) 2002-09-11 2006-11-28 Planar Systems, Inc. Precursor material delivery system for atomic layer deposition
US20040124131A1 (en) * 2002-09-11 2004-07-01 Aitchison Bradley J. Precursor material delivery system for atomic layer deposition
US9443730B2 (en) 2014-07-18 2016-09-13 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US9837271B2 (en) 2014-07-18 2017-12-05 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
US10460932B2 (en) 2017-03-31 2019-10-29 Asm Ip Holding B.V. Semiconductor device with amorphous silicon filled gaps and methods for forming

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CA1047850A (en) 1979-02-06
JPS5095185A (en) 1975-07-29
GB1470614A (en) 1977-04-14
DE2460211B2 (en) 1979-05-23
DE2460211A1 (en) 1975-11-06
FR2255707A1 (en) 1975-07-18
FR2255707B1 (en) 1978-06-23
HK68380A (en) 1980-12-12

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