US3918041A

US3918041A - Multiplex display system

Info

Publication number: US3918041A
Application number: US495026A
Authority: US
Inventors: Roger A Mao
Original assignee: Individual
Current assignee: Individual
Priority date: 1974-08-05
Filing date: 1974-08-05
Publication date: 1975-11-04
Anticipated expiration: 1992-11-04

Abstract

A multiplex system is disclosed for storageless displays which utilize a plurality of illuminating devices for displaying large numbers of characters. The display system uses a plurality of circuits for memorizing digital coded signals representing numerical of alphanumerical characters supplied thereto where the number of such memory circuits correspond to that of the illuminating devices. Included is a circuit common to the memory circuits for simultaneously selecting for display identical numerical or alphanumerical characters or symbols. The display system may incorporate either a seven segment display or a 16 segment display for visually exhibiting the numerical or alphanumerical characters.

Description

Mao

MULTIPLEX DISPLAY SYSTEM Nov. 4, 1975 Primary ExaminerDavid L, Trafton [76] Inventor: Roger A. Mao, 5603C S. Doubloon Court, Tempe, An'z. 85283 ABSTRACT [22] Filed: Aug 5 1974 A multiplex system is disclosed for s toragel ess displays which utilize a plurality of illuminating devices for dis- [21] Appl. No.: 495,026 playing large numbers of characters, The display system uses a plurality of circuits for memorizing digital {52] CL 340/336; 340/324 R; 350/160 LC coded signals representing numerical of alphanumer- [511 In. CLZ G08B 5/36 ical characters supplied thereto where the number of 58 Field of s 'r'ciiiijjllIiiIIIIIIIIlIiiI67336, 178/30 l F Circuits coriesponfl 1 of mumi' natmg devices. Included 18 a circuit common to the [561 CM 31minstir"2,2152?zLzizzszkm slfs ."aim;

a 1 n '1' UNITED STATES PATENTS or symbols. The display system may incorporate either 3,299,418 Treseder 4 i r v i v l78/30 X a even egment or a segment for 3715744 2/1973 i 340/336 visually exhibiting the numerical or alphanumerica] 1789388 1/1974 Medwm H 340/336 characmrq 3,815,]20 6/1974 Kanda 340/336 20 Claims, 7 Drawing Figures 12 BINARY CODE DATA lNPUT REGISTER Q /2O 4 22 58 r r 62 q;72l iiIfis I 60 l l 28 l A l l g 30 Q] MEMORY REGlSTER l l4 I BlNARY I AND I 32 CODE l BACKPL l I ANE DRIVE T GENERATOR l I 34 IA l l I g l I l 5CD sswsm f I DECOCER/ l I DRIVER U.S. Patent Nov. 4, 1975 Sheet 3 Of3 3,918,041

Fig. 5A

ZIG 222 230 l 220 ZIB Fig. 3B

MULTIPLEX DISPLAY SYSTEM BACKGROUND OF THE INVENTION I. Field of the Invention The invention relates generally to display systems and, more particularly, to multiplex techniques for such systems comprising a plurality of separately energizable illuminating display devices, such as segments comprising liquid crystal materials where the segments are so positioned with respect to each other, that when selectively illuminated, they form numerical or alphanumerical characters or symbols.

2. Description of the Prior Art In prior art circuits numerical or alphanumerical characters to be displayed are addressed one character at a time. As the number of characters to be displayed increases, the scan frequency required to address the digits increases, thereby decreasing the duty cycle.

In a display system employing liquid crystal displays, a problem arises as to the number of characters that may be displayed by prior art multiplex circuits. Liquid crystal materials have an inherent problem in that the molecules have a certain amount of inertia that has to be overcome. This limits the operating speed. Therefore, if there were, for instance, digits or 100 digits to be displayed, and each individual digit would have to be strobed one at a time, then the frequencies necessary in order to operate such a liquid crystal display would be of such large magnitude that the display itself cannot respond.

Other prior art circuits employ a "parallel" scheme for displaying characters in which each individual character to be displayed is controlled by a separate decoder. In this scheme the number of leads required to energize the display system is dependent upon the number of characters to be displayed and upon the number of segments to be energized. The parallel" scheme requires Sn I leads (where S =the number of segments, n the number of characters to be displayed and l is the lead common to a back plane drive). Hence, the number of leads required in this type of scheme is directly proportional to the number of characters to be displayed. For displays having a large number of digits, for instance, in excess of ten, because of the number of leads required, the cost of production may be prohibitive.

A need exists to develop a multiplex technique for reducing the number of required leads for energizing the display.

A need also exists to develop a multiplex technique as a solution to the problems caused by frequency limitations due to the use of liquid crytal materials.

SUMMARY OF THE INVENTION It is an object of this invention to provide an improved multiplex system for visually displaying numerical or alphanumerical characters in response to a binary code data input signal.

Another object of this invention is to provide a multiplex circuit which is suitable for manufacture in integrated circuit form.

Still another object of this invention is to provide a multiplex system which is capable of simultaneously selecting for display identical numerical or alphanumerical symbols.

2 A still further object is to provide a multiplex system which is adaptable to the use of field effect liquid crystal devices using a one-third select or four-level driving mechanism.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT The system for displaying numerical or alphanumerical symbols is disclosed which is suitable for providing multiplexing of large numbers of numerical or alphanumerical characters to be displayed in a display system. The duty cycle of the multiplex circuit is held constant and is not a function of the number of characters displayed. The multiplex system or circuit includes a storage means and a selection means for simultaneously selecting for display identical numerical or alphanumerical symbols. The storage means has input terminals for receiving digital coded signals representing the numerical or alphanumerical symbols for storing the coded signals during a writing cycle. The selection means includes generator means for cyclically providing binary coded signals to the storage means during a display cycle for simultaneously selecting for display identical characters that are stored during the write cycle. The selection circuit also provides means for energizing storageless display materials for exhibiting the numerical or alphanumerical symbol on a visual display means. Various modifications of the multiplex circuit render it suitable for simultaneously selecting for display either identical characters or identical segments with the segments being correlated with respect to each other for forming numerical or alphanumerical symbols.

Other objects, features and advantages of the invention will be apparent from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. la is a block diagram of a multiplex circuit illustrating one embodiment of the invention.

FIG. lb is a block diagram of one component of FIG. la.

FIG. 1c is a partial block diagram and partial schematic diagram of one component of FIG. Ib.

FIG. 2a is a partial block and partial schematic diagram of a second form of embodiment of the invention.

FIG. 2b is a partial block and partial schematic diagram of one component of FIG. 2a.

FIG. 3a is an illustration of a seven segment numerical symbol display of FIG. la.

FIG. 3b is an illustration of a I6 segment alphanumerical symbol display.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to provide a clear explanation, the invention is described hereinafter with reference to embodiments using a plurality of liquid crystal display devices. However, other display devices can also be used such as light-emitting diodes (LEDs) and incandescent and fluorescent readouts.

Referring to FIGS. la and lb there is shown a multiplex system according to one embodiment of the invention. A visual display system is illustrated comprising visual dispaly unit 18. Visual display unit 18 is shown to have a plurality of digit or characters for display in response to a predetermined control signal being applied from a system source, not shown.

In a preferred form of the invention, the characters to be displayed consists of seven segments, and is illustrated in FIG. 3a. The segments are correlated with respect to each other to form arabic numbers. The seven segments, 200, 202, 204, 206, 208, 210 and 212 are illuminated to form particular arabic numerals in response to control signals generated by the multiplex circuit to be explained later.

As is well known in the art, binary coded signals of four-bit lengths are applied to the multiplex circuit over leads 20, 22, 24 and 26. These coded signals are applied to memory system 10 to be multiplexed for visual display in arabic form. A shift register 12 is connected to memory register 10 for supplying timing pulses in synchronism with the applied binary coded signals for storing the single bits of coded signals in memory circuits comprising a plurality of four-bit latch circuits 8], corresponding to the number of characters to be displayed on visual display unit 18. Shift register 12 has a plurality of output terminals, as illustrated by leads S8 64, corresponding to the number of memory circuits, for strobing the binary coded signals into the memory units in a sequential order.

The memory register 10 is adapted to provide a plurality of output terminals, as illustrated by leads 66 72 for supplying turn-on signals to back plane drive 74, as will be explained later. Back plane drive 74 being well known in the art, receives the turn-on signals to energize the individual liquid crystal digits.

The binary code generater 14 provides repititious binary coded signals of four-bit length to memory register 10 and to decoder 16, respectively. The generated four-bit binary coded signals represent the numeral characters 9 and are applied to memory register and decoder 16 over leads 28 34 and 36- 42, respectively.

Decoder 16 comprises a BCD to seven segment decoder, well known in the art, and a segment driver for energizing the seven segment characters to be displayed on visual display unit 18.

The multiplex technique and circuit, as illustrated in FIGS. la, lb and 1c eliminates or minimizes problems associated with multiplex techniques in which the display operation employs a serial or time share process. Instead of addressing the characters to be displayed one at a time, identical numerical characters can be strobed simultaneously for displaying these characters at the same instant of time as will hereinafter be explained.

As illustrated in FIG. lb, memory register 10 is comprised of a plurality of storage registers, connected in parallel to the data input terminals of the multiplex circuit. Each storage register comprised of four-bit latch and comparator circuit 81. Each individual four-bit latch and comparator circuit 81, as shown in FIG. lc, includes a single bit latch flip-flop 82 which has two input terminals and a single output terminal. The output terminal thereof is connected to one input terminal of an Exclusive OR circuit 84. The other input terminal of Exclusive OR circuit 84 is connected to binary code generator 14. The output terminal of Exclusive OR circuit 84 is connected to one of four input terminals of an AND circuit 80. The remaining three input terminals of AND circuit 80 are connected to similar Exclusive OR circuits individual to each of the single bit latch flipflops 82 that comprise founbit latch comparator 81. The output terminal of AND circuit 86 is then con- 4 nected to one of a plurality of input terminals to back plane drive 74 over leads 66a 72a.

Shift register 12 is connected to each individual single bit latch 82 through a plurality of output terminals as illustrated by leads 58 64.

A description will be given to the operation of one embodiment of the invention, the construction of which is explained above.

In operation, during a write cycle, numerical data is supplied by a source (not shown) sequentially in the order in which the numeric characters ar to be visually displayed. The data applied is in a coded form, such as a binary coded, four-bit length, signal. The binary coded signal representing numeric characters are applied over leads 20 26, in parallel, to the input terminals of single bit latches 82 comprising a single four-bit latch and comparator circuit 81.

As the numeric data reaches its proper digit, it is strobed into four-bit latch and comparator circuit 81 by means of timing pulses being applied to the second input terminals of the singlebit latches 82. The timing pulses are supplied by shift register 12, as illustrated, over leads 58 64. The timing pulses are applied to the input of the four-bit latch and comparator circuit 81 in synchronism with the arrival of the sequential numerical data over leads 20 26. In this way, the binary coded signals that represent a numeric character to be displayed at a particular location is strobed into the correct four-bit latch and is stored at the correct spatial location to be displayed later. Each single data bit of a four-bit length binary coded signal is then stored in the correct latch flip-flop 82 and provides an input signal to one input terminal of Exclusive OR circuit 84 connected as described above.

The write cycle continues until all of the numerical data to be displayed is stored in corresponding four-bit latches and comparators. During the write cycle, binary code generator 14 is disabled and display unit 18 is in a non-display mode.

After the write cycle has been completed, a display cycle is inaugurated and binary code generator 14 is enabled. Binary code generator 14, well known in the art, cyclically generates binary coded signals of four-bit lengths representing the numeric characters 0 9. Binary generator 14 applies the coded signals over leads 28 34 to Exclusive OR circuit 84 that is individual to each of the single bit latches 82, at a second input terminal thereof. Exclusive OR circuit 84 compares the data stored in single bit latch 82 with the bit information from binary code generator 14 and, if identical, provides a signal at the output tenninal thereof.

In a like manner, all of the binary coded signals stored in a particular four-bit latch is compared with the generated binary code signal from binary code generator 14. If the binary code generated is identical to the binary code stored in the four-bit latch, four output signals are produced by the four Exclusive OR circuits 84, which are then applied over leads 96 to AND gate 86 at input terminals thereof. AND gate 86, as is known, provides a signal at an output terminal thereof to back plane drive 74 for turning on the numerical character to be displayed.

Assuming that there are identical binary coded signals stored in several of the plurality of four-bit latch and comparator circuits 8], each of the respective AND gates 86 will simultaneously provide turn-on signals in response to the generated binary code signals from binary code generator I4. Hence, identical numerical characters at displayed at the same time on visual display unit 18, as will be explained.

Other identical numerical characters will be displayed sequentially as binary code generator 14 produces a binary code signal identical to the stored numerical data in particular four-bit latch and comparator circuits 8] during the cyclically production of binary coded signals. The operation for displaying other identical numerical characters is the same as that described above.

To visually display the characters, the cyclically produced binary coded signals from binary code generator 14 are also applied, as illustrated, over leads 36, 38, 40 and 42 to a BCD to seven segment decoder/driver l6. Decoder/driver 16 being known to the art decodes the four-bit length coded signal from generator 14 to provide signals for energizing the seven segment character as shown in FIG. 3a, in response to a tum-on signal being applied at the correct time from AND gates 86.

The method for energizing segments uses a one-third select or four-level scheme. A detailed discussion of this scheme and the principle of operation appears in the article Matrix-addressed Liquid Crystal Display by C. H. Gooch and J. J. Low, J. Phys. D: Appl. Phys, Vol. 5, 1972.

As described above, the invention provides an advantage over prior art in that identical characters are simultaneously displayed. Prior art multiplex circuits address the characters to be displayed one at a time. Whereas prior art circuits for display of a large number of characters may be limited by the scan frequency being non-compatible with the response time of liquid crystals, the embodiment of the invention discloses a technique whereby identical characters are displayed simultaneously which, therefore, relaxes the scan frequency requirements. The duty cycle of the present invention is fixed, for any number (n) of characters to be displayed, at one-tenth for the number of numerical digits). Prior art circuits require a duty cycle for the scan frequency to be l/n.

A second embodiment of the invention is shown in FlGS. 2a and 2b in which either numerical or alphanumerical characters or symbols may be displayed using either seven segment or 16 segment characters, as illustrated in FIGS. 3a and 3b.

The operation of the embodiment as illustrated in FIG. 2 is quite similar to the multiplex circuit and technique of the first embodiment. Whereas in FIG. 1, identical numerical characters are displayed, FIG. 2 discloses a technique in which identical segments are to be displayed simultaneously.

During the write cycle, digital coded signals are supplied by a source (not shown) that consists of seven or 16 bits and each bit corresponds to a particular segment to be displayed. The digital signals are sequentially applied to the multiplex circuit in the order to which the numerical or alphanumerical characters are to be spatially displayed on visual display units 116. The seven-bit or 16-bit data information is applied in parallel to a plurality of n-bit latching comparators 101 over leads, as illustrated, 104 108.

The n-bit latch and comparator circuit 101 includes either seven or 16 individual single latch flipflops 160, corresponding to the supplied digital signals. Single bit latch 160 is adapted to receive a timing pulse from register 102 and a single bit of information from the digital signals applied from the source at input terminals thereof. FIG. 2b shows, for illustration, one of n (n equal to 7 or l6) latches 160 that comprise n-bit laltch and comparator circuit 101. The timing pulse and single bit signals are applied to single latch 160 over

leads

122 and 124, respectively. Single bit latch 160 is connected to one input terminal of AND gate 162 which is individual to each latch 160 comprising n-bit latch and comparator 101. A second input terminal of AND gate 162 is provided to receive a signal from one ofn generator 110.

The output of AND gate 162 is connected to one of a plurality of input terminals of OR gate 164. OR gate 164 is individual to n-bit latch circuit 101 having a total number of input terminals corresponding to the AND gates, 162, that comprise n-bit latch and comparator circuit 101. An output signal is produced by OR gate 164 in response to a signal from any of AND gate, 162, at an output terminal thereof for providing a tum-on" signal to back plane drive US which is similar to back plane drive 74 of FIG. 1. The tum-on" signal is used to energize particular segments of visual display unit 1 l6 which are correlated with respect to each other to display either a numerical or alphanumerical character in accordance with the digital signals received from the data information source. The output signals from oneof-n generator are also supplied to segment drive 114 for illuminating the segments that have received the turn-on" signal from back plane drive 118.

As described previously, for the embodiment of FIG. 1, shift register 102 provides timing pulses in synchronism with the digital signals applied over leads 104 108 for strobing individual bit information from the applied digital signals into the correct n-bit latch 10] in order that correct segments may be illuminated in the order that they are to be displayed.

In a like manner, as to the circuit described in FIG. 1, the write cycle continues until all of the n-bit latch and comparator circuits 10], contain the information, either numerical or alphanumerical, to be displayed in visual form on visual display unit 116.

As the write cycle concludes, a display cycle is inaugurated and one-of n generator 110 is enabled for pro viding cyclically a one-of-seven or one-of-l6 code. In way of an example, for the case in which the 1 of 7 code is used, generator 110 has seven output terminals corresponding to the seven AND gates, 136, included in 11-bit latch and comparator 101. The seven single data bits generated by the l of 7 code are applied to the plurality of n-bit latch and comparators, 101, in parallel, over lead 136, shown for illustration. When the logical l stored in a single bit latch agrees with a logical l" appearing on AND gate 162 provided by one-of-n generator 110 the output of OR gate 164 goes to a logical l The logical l from the output of OR gate 164 activates the back plane of the particular character to be displayed.

To visually display the segments, the cyclically produced l of 7 code from one-of-n generator 110 is applied as illustrated over leads I40 144 to segment drive 114. Segment driver 114, being well known to the art, provides the necessary energizing signals for illuminating the segments of the visual display unit. The individual characters are displayed and the segments that comprise them are shown in FIGS. 3a and 3b, respectively. Hence, in response to identical signals being supplied to n-bit latch and comparator l0], all identical segments will be simultaneously displayed.

Thus, for a seven segment display the duty cycle of the scan frequency is now 1/7, and for a 16 segment 7 display the duty cycle is H16.

in summary, a technique has been disclosed whereby identical characters or segments, correlated to form numeric or alphanumeric characters, are simultaneously strobed for being visually displayed.

A distinct advantage over prior art multiplex circuits is provided by the embodiments of the invention. In prior art circuits in which the characters to be displayed are addressed one at a time, the number of characters is limited due to the scan frequency required. That is, as the number of characters increases, the scan frequency must increase and, therefore, the duty cycle must decrease. Therefore, the maximum number of characters that may be displayed is limited by the response time of the liquid crystal display. However, as disclosed in the preferred embodiments of the invention, the duty cycle of the scan frequency is held constant, its value depending upon if identical characters or identical segments are simultaneously displayed, and is not a function of the number of characters to be displayed.

Another advantage of the invention over prior art circuits is the reduction of leads required to energize the display. In the present form, the selected segments are energized in parallel"from a single decoder. The number of leads required to activate the display system is now S n in general (where S the number of segments comprising the numerical or alphanumerical character and n the number of characters to be displayed). As described earlier the number of leads required in prior art circuits are proportional to the formula Sn l. In way of a numerical example, assuming seven segment digits are to be illuminated, S 7 for l such digits (n prior art circuits would require at least 71 leads to provide the means for energizing all ten digits; the embodiments of the invention require only 17 leads. Hence, multiplex circuits of the invention can realize a severe savings in production cost.

While the above detailed description has shown, described and pointed out the fundamental novel features of the invention as applied to various embodiments, it will be understood that various substitutions and changes in the form and details of the circuits and methods may be made by those skilled in the art without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the following claims.

I claim:

1. A system for displaying numerical or alphanumerical symbols comprising in combination:

means for applying predetermined binary coded signals representing numerical or alphanumerical symbols;

storage means connected to said means for applying predetermined binary coded signals to receive said predetermined binary coded signals for storing each of said numerical or alphanumerical symbols to be displayed;

selection means connected to said storage means for simultaneously selecting for display identical numerical or alphanumerical symbols; and

display means for visually exhibiting identical numerical or alphanumerical symbols stored in said storage means.

2. The system according to claim 1 wherein said selection means further includes means for selecting for display other unlike numerical or alphanumerical symbols to be displayed by said display means.

3. A multiplex circuit suitable for decoding binary coded signals for providing a display of a plurality of numerical or alphanumerical symbols comprising, in combination:

means for applying first predetermined binary coded signals representing numerical or alphanumerical symbols;

storage means connected to said means for applying said predetermined binary coded signals to receive said predetermined binary coded signals for storing each of said binary coded signals representing numerical or alphanumerical symbols;

generator means for repeatedly providing a sequential set of binary coded signals representing numerical or alphanumerical symbols;

selection means connected to said storage means and to said generator means to receive said first predetermined binary coded signals and said sequential set of binary coded signals for simultaneously displaying identical numerical or alphanumerical symbols;

said selection means further including means for selectin g for display other numerical or alphanumerical symbols; and

display means for visually displaying said numerical or alphanumerical symbols.

4. The multiplex circuit according to claim 3 wherein said first predetermined binary coded and siad second predetermined binary coded signals comprise a sequence of four digital signals representing numerical symbols.

5. The multiplex circuit according to claim 4 wherein said storage means includes in combination:

a plurality of memory circuits corresponding to said plurality of numerical symbols to be displayed for receiving said first predetermined binary coded signals comprising said sequence of four digital signals;

timing means connected to said plurality of memory circuits for generating timing pulse signals and sequentially supplying said timing pulse signals to said memory circuits for rendering said memory circuits in a state for receiving saim first predetermined binary coded signals sequentially.

6. The multiplex circuit according to claim 5 wherein each of said memory circuits include in combination four single-bit latch flip-flops.

7. The multiplex circuit according to claim 6 wherein said selection means further includes in combination:

comparator means individual of each of said singlebit latch flipflops of said each memory circuit for comparing said first predetermined binary coded signal and said second predetermined binary coded signal and providing a control signal at an output terminal thereof in response to said first and said second predetermined binary coded signals being identical; and

gating means individual to each of said memory circuits connected to each of said comparator means comprising each of said memory circuits to receive said control signal from each of said comparator means for supplying a tum-on signal to said display means in response to each of said comparator means supplying a control signal to said gating means.

8. The multiplex circuit according to claim 7 wherein said display means includes in combination:

9 a back plane drive means connected to each of said gating means to receive said control signals; decoder means connected to said generating means to receive said sequential set of binary coded signals for providing an illuminating control signal; a plurality of segments connected to said decoder means and illuminated when energized and correlated with respect to each other to display said plurality of numerical symbols;

said segments being illuminated in response to receiving said gating control signal and said illuminating control signal for visually exhibiting said numerical symbols.

9. The multiplex circuit according to claim 8 wherein said plurality of segments corresponding to an individual numerical symbol includes seven segments arranged in the form of an arabic FIG. 8.

10. A multiplex circuit suitable for decoding binary coded signals for providing a display of a plurality of numerical or alphanumerical symbols comprising, in combination:

storage means connected to said means for applying said predetermined binary coded signals for storing each of said binary coded signals representing numerical or alphanumerical symbols;

generation means for repeatedly providing a sequential set of binary coded signals;

selection means connected to said storage means and to said generator means to receive said first predetermined binary coded signals and said sequential set of binary coded signals for simultaneously displaying identical segments corresponding to each of said plurality of numerical or alphanumerical symbols to be displayed;

said selector means further including means for selecting for display other segments corresonding to numerical or alphanumerical symbols to be displayed; and

display means for visually displaying said numerical or alphanumerical symbols.

1]. The multiplex circuit according to claim 3 wherein said first predetermined binary coded signals and said second predetermined and repeating binary coded signals comprise a sequence of seven digital signals representing numerical symbols.

12. The multiplex circuit according to claim wherein said storage means includes in combination:

a plurality of memory circuits corresponding to said plurality of numerical symbols to be displayed to receive said first predetermined binary coded signals comprising said sequence of seven digital signals; and

timing means connected to said plurality of memory circuits for generating timing pulse signals and sequentially supplying said timing pulse signals to said memory circuits for rendering said memory circuits in a state for receiving said first predetermined binary coded signals sequentially 13. The multiplex circuit according to claim 1] wherein each of said memory circuits include in combination seven single-bit latch flip-flops, each of said sin gle-bit latch flip-flops receiving one digital signal of said sequence of seven digital signals for providing a segment control signal at an output terminal thereof.

14. The multiplex circuit according to claim 12 wherein said selection means further includes in combination:

first gating means individual to each of said single-bit latches and connected to said generating means to receive said segment control signal and said se quential set of binary coded signal for gating said segment control signal to an output terminal thereof in response to said segment control signal 10 and said sequential set of binary coded signal being identical;

second gating means individual to each of said memory circuits connected to said output terminal of each of said gating means to receive said segment control signal for providing a turn-on signal to said display means for illuminating said predetermined numerical symbol.

15. The multiplex circuit of claim 13 wherein said display means includes in combination:

a back plane drive means connected to each of said second gating means to receive said turn-on sig' nals;

driver means connected to said generating means to receive said sequential set of binary coded signals for providing an illuminating control signal;

a plurality of segments connected to said driver means being illuminated when energized and said segments being correlated with respect to each other to display said numerical symbols; and

said segments being illuminated in response to receiving said turn-on signal and said illuminating control signal for viaually displaying said numerical symbols.

16. The multiplex circuit according to claim 10 wherein said first predetermined binary coded signals and said sequential set of binary coded signals comprise a sequence of 16 digital signals representing numerical and alphanumerical symbols.

17. The multiplex circuit according to claim 15 wherein said storage means includes in combination:

a plurality of memory circuits corresponding to said plurality of numerical or alphanumerical symbols to be displayed to receive said first predetermined binary coded signals comprising said sequence of 16 digital signals; and

timing means connected to said plurality of memory circuits for generating timing pulse signals and sequentially supplying said timing pulse signals to said memory circuits for rendering said memory circuits in a state for receiving said first predetermined binary coded signals sequentially.

18. The multiplex circuit according to claim 16 wherein each of said plurality of memory circuits include in combination l6 single-bit latches, each of said latches receiving one of said digital signals of said sequence of said 16 digital signals for providing a segment control signal at an output tenninal thereof.

19. The multiplex circuit of claim 17 wherein said selection means further includes in combination:

first gating means individual to each of said single-bit latches and connected to said generating means to receive said segment control signal and said sequential set of binary coded signals for gating said segment control signal to an output terminal thereof in response to said segment control signal and said sequential set of coded signals being identical;

1 1 12 second gating means individual to each of said memdriver I cflnnected to Said gfmcrating to or circuits Connect d t t t t l f receive said sequential set of binary co ed signals y e P Frmma 0 for providing an illuminating control signal;

the said first gating means to receive said segment a plurality of segments connected to said driver control signal for providing a turn-on signal to said 5 mcans "P when Fnerglzed and 531d 8' display means for illuminating said predetermined bemg F with respect to i ether to dlsplay said numerical or alphanumerical symnumerlcal or alphanumerical symbol. b l d 20. The multiplex circuit of claim 18 wherein said saidsegments being illuminated in responseto redisplay means includes in combination: m ceivmg said turn-on signal and said lllumlnatlng control signal for visually displaying said numerical or alphanumerical symbols. second gating means to receive said turn-on signal;

a back plane drive means connected to each of said

Claims

1. A system for displaying numerical or alphanumerical symbols comprising in combination: means for applying predetermined binary coded signals representing numerical or alphanumerical symbols; storage means connected to said means for applying predetermined binary coded signals to receive said predetermined binary coded signals for storing each of said numerical or alphanumerical symbols to be displayed; selection means connected to said storage means for simultaneously selecting for display identical numerical or alphanumerical symbols; and display means for visually exhibiting identical numerical or alphanumerical symbols stored in said storage means.

3. A multiplex circuit suitable for decoding binary coded signals for providing a display of a plurality of numerical or alphanumerical symbols comprising, in combination: means for applying first predetermined binary coded signals representing numerical or alphanumerical symbols; storage means connected to said means for applying said predetermined binary coded signals to receive said predetermined binary coded signals for storing each of said binary coded signals representing numerical or alphanumerical symbols; generator means for repeatedly providing a sequential set of binary coded signals representing numerical or alphanumerical symbols; selection means connected to said storage means and to said generator means to receive said first predetermined binary coded signals and said sequential set of binary coded signals for simultaneously displaying identical numerical or alphanumerical symbols; said selection means further including means for selecting for display other numerical or alphanumerical symbols; and display means for visually displaying said numerical or alphanumerical symbols.

5. The multiplex circuit according to claim 4 wherein said storage means includes in combination: a plurality of memory circuits corresponding to said plurality of numerical symbols to be displayed for receiving said first predetermined binary coded signals comprising said sequence of four digital signals; timing means connected to said plurality of memory circuits for generating timing pulse signals and sequentially supplying said timing pulse signals to said memory circuits for rendering said memory circuits in a state for receiving saim first predetermined binary coded signals sequentially.

7. The multiplex circuit according to claim 6 wherein said selection means further includes in combination: comparator means individual of each of said single-bit latch flip-flops of said each memory circuit for comparing said first predetermined binary coded signal and said second predetermined binary coded signal and providing a control signal at an output terminal thereof in respOnse to said first and said second predetermined binary coded signals being identical; and gating means individual to each of said memory circuits connected to each of said comparator means comprising each of said memory circuits to receive said control signal from each of said comparator means for supplying a turn-on signal to said display means in response to each of said comparator means supplying a control signal to said gating means.

8. The multiplex circuit according to claim 7 wherein said display means includes in combination: a back plane drive means connected to each of said gating means to receive said control signals; decoder means connected to said generating means to receive said sequential set of binary coded signals for providing an illuminating control signal; a plurality of segments connected to said decoder means and illuminated when energized and correlated with respect to each other to display said plurality of numerical symbols; said segments being illuminated in response to receiving said gating control signal and said illuminating control signal for visually exhibiting said numerical symbols.

10. A multiplex circuit suitable for decoding binary coded signals for providing a display of a plurality of numerical or alphanumerical symbols comprising, in combination: means for applying first predetermined binary coded signals representing numerical or alphanumerical symbols; storage means connected to said means for applying said predetermined binary coded signals for storing each of said binary coded signals representing numerical or alphanumerical symbols; generation means for repeatedly providing a sequential set of binary coded signals; selection means connected to said storage means and to said generator means to receive said first predetermined binary coded signals and said sequential set of binary coded signals for simultaneously displaying identical segments corresponding to each of said plurality of numerical or alphanumerical symbols to be displayed; said selector means further including means for selecting for display other segments corresonding to numerical or alphanumerical symbols to be displayed; and display means for visually displaying said numerical or alphanumerical symbols.

11. The multiplex circuit according to claim 3 wherein said first predetermined binary coded signals and said second predetermined and repeating binary coded signals comprise a sequence of seven digital signals representing numerical symbols.

12. The multiplex circuit according to claim 10 wherein said storage means includes in combination: a plurality of memory circuits corresponding to said plurality of numerical symbols to be displayed to receive said first predetermined binary coded signals comprising said sequence of seven digital signals; and timing means connected to said plurality of memory circuits for generating timing pulse signals and sequentially supplying said timing pulse signals to said memory circuits for rendering said memory circuits in a state for receiving said first predetermined binary coded signals sequentially.

13. The multiplex circuit according to claim 11 wherein each of said memory circuits include in combination seven single-bit latch flip-flops, each of said single-bit latch flip-flops receiving one digital signal of said sequence of seven digital signals for providing a segment control signal at an output terminal thereof.

14. The multiplex circuit according to claim 12 wherein said selection means further includes in combination: first gating means individual to each of said single-bit latches and connected to said generating means to receive said segment control signal and said sequential set of binary coded signal for gating said segment control signal to an output terminal thereof in response to said segment control signal and said sequential set of binary coded signal being identical; second gating means individual to each of said memory circuits connected to said output terminal of each of said gating means to receive said segment control signal for providing a turn-on signal to said display means for illuminating said predetermined numerical symbol.

15. The multiplex circuit of claim 13 wherein said display means includes in combination: a back plane drive means connected to each of said second gating means to receive said turn-on signals; driver means connected to said generating means to receive said sequential set of binary coded signals for providing an illuminating control signal; a plurality of segments connected to said driver means being illuminated when energized and said segments being correlated with respect to each other to display said numerical symbols; and said segments being illuminated in response to receiving said turn-on signal and said illuminating control signal for viaually displaying said numerical symbols.

17. The multiplex circuit according to claim 15 wherein said storage means includes in combination: a plurality of memory circuits corresponding to said plurality of numerical or alphanumerical symbols to be displayed to receive said first predetermined binary coded signals comprising said sequence of 16 digital signals; and timing means connected to said plurality of memory circuits for generating timing pulse signals and sequentially supplying said timing pulse signals to said memory circuits for rendering said memory circuits in a state for receiving said first predetermined binary coded signals sequentially.

18. The multiplex circuit according to claim 16 wherein each of said plurality of memory circuits include in combination 16 single-bit latches, each of said latches receiving one of said digital signals of said sequence of said 16 digital signals for providing a segment control signal at an output terminal thereof.

19. The multiplex circuit of claim 17 wherein said selection means further includes in combination: first gating means individual to each of said single-bit latches and connected to said generating means to receive said segment control signal and said sequential set of binary coded signals for gating said segment control signal to an output terminal thereof in response to said segment control signal and said sequential set of coded signals being identical; second gating means individual to each of said memory circuits connected to said output terminal of the said first gating means to receive said segment control signal for providing a turn-on signal to said display means for illuminating said predetermined numerical or alphanumerical symbol.

20. The multiplex circuit of claim 18 wherein said display means includes in combination: a back plane drive means connected to each of said second gating means to receive said turn-on signal; driver means connected to said generating means to receive said sequential set of binary coded signals for providing an illuminating control signal; a plurality of segments connected to said driver means illuminated when energized and said segments being correlated with respect to each other to display said numerical or alphanumerical symbols; and said segments being illuminated in response to receiving said turn-on signal and said illuminating control signal for visually displaying said numerical or alphanumerical symbols.