|Numéro de publication||US4339285 A|
|Type de publication||Octroi|
|Numéro de demande||US 06/172,757|
|Date de publication||13 juil. 1982|
|Date de dépôt||28 juil. 1980|
|Date de priorité||28 juil. 1980|
|Numéro de publication||06172757, 172757, US 4339285 A, US 4339285A, US-A-4339285, US4339285 A, US4339285A|
|Inventeurs||Jacques I. Pankove|
|Cessionnaire d'origine||Rca Corporation|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (17), Citations hors brevets (10), Référencé par (74), Classifications (27), Événements juridiques (2)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
The present invention relates to laser irradiation of silicon films. More particularly, it relates to the laser irradiation of an oxygenated, doped, non-single crystalline silicon film.
Silicon films can be characterized by their crystallographic structure and by the type and concentration of impurity atoms they contain. The structures can be classified as crystalline, polycrystalline and amorphous, and the silicon films can be doped with oxygen, hydrogen or typical N or P type conductivity modifiers. A large number of combinations of crystal structure, impurity type and impurity concentration are therefore possible. By manipulating these combinations, it is possible to create a silicon film having electrical properties within a wide range of values. Generally, the conductivity of a silicon film increases as the degree of its crystallinity increases and as the doping concentration of N or P type conductivity modifiers increases. Compared to polycrystalline silicon films, amorphous silicon films tend to be more insulating and single crystalline films tend to be more conducting. As described herein, materials having resistivities greater than approximately 108 ohm-centimeters will be characterized as insulating and materials having resistivities less than about 102 ohm-centimeters will be characterized as conducting.
Polycrystalline silicon films doped with N or P type conductivity modifiers are electrically conductive and are conventionally used as gates, contacts and interconnections in integrated circuit devices. In U.S. Pat. No. 4,198,246, PULSED LASER IRRADIATION FOR REDUCING RESISTIVITY OF A DOPED POLYCRYSTALLINE SILICON FILM, issued Apr. 15, 1980 to C. P. Wu, and in copending U.S. patent application Ser. No. 065,437, LOW RESISTIVITY POLYCRYSTALLINE SILICON FILM, filed Aug. 10, 1979 by C. P. Wu et al now U.S. Pat. No. 4,229,502, it is disclosed that the conductivity of N or P type polycrystalline silicon films can be further increased by subjecting them to thermal annealing or laser irradiation.
In contrast, oxygenated, polycrystalline silicon films are typically highly resistive and are conventionally used as insulating and passivating layers. Oxygenated polycrystalline silicon, hereinafter referred to as SIPOS, is an insulating material, although its conductivity can be increased if it is doped with an N or P type conductivity modifier. The resistivity of doped or undoped SIPOS can be further manipulated by varying its oxygen concentration, as is described in U.S. Pat. No. 4,014,037, SEMICONDUCTOR DEVICE, issued Mar. 22, 1977 to T. Matsushita and in U.S. Pat. No. 4,086,613, SEMICONDUCTOR DEVICE HAVING A PASSIVATED SURFACE AND METHOD OF MANUFACTURING THE DEVICE, issued Apr. 25, 1978 to J. P. H. Biet et al. The resistivity of pure (nonoxygenated) polycrystalline silicon is approximately 3×106 ohm-centimeters, whereas SIPOS containing approximately 20 atomic percent oxygen has a resistivity of approximately 1011 ohm-centimeters. Oxygenated, amorphous silicon is also substantially insulating, typically having a resistivity greater than 108 ohm-centimeters.
A method is disclosed for fabricating adjacent electrically conducting and insulating regions in a silicon film. Initially, a substantially insulating layer of oxygenated, N or P doped, non-single crystalline silicon film is formed. This film is then selectively laser irradiated so as to form an irradiated portion which is substantially conducting.
FIGS. 1 and 2 illustrated the process steps in a preferred embodiment of the present invention.
FIG. 3 illustrates an electrode/passivation layer structure fabricated by the present invention.
FIG. 4 illustrates an electrode/gate oxide structure fabricated by the present invention.
FIG. 5 illustrates an interconnection structure fabricated by the present invention.
In the preferred embodiment, as illustrated in FIG. 1, a layer of oxygenated, N or P doped, non-single crystalline silicon film 12 is formed on a substrate 10. The substrate 10 is not essential to the invention, although it provides a carrier on which to form the silicon film 12 and it may be used in conjunction with the silicon film 12 to create, for example, a semiconductor device. The substrate 10 can be a conductor, semiconductor, semiinsulator or insulator, and it can be of any crystalline or non-crystalline structure. In one example, the substrate 10 is single crystalline silicon, appropriately doped to create a diode, transistor or thyristor.
The material of the silicon film 12 is oxygenated, N or P type non-single crystalline silicon. It can be either N or P type SIPOS, or oxygenated, N or P type amorphous silicon. It is essential to the invention that the film 12 be doped with both oxygen and an N or P type conductivity modifier. A film so described will be substantially insulating; it will have a resistivity greater than 108 ohm-centimeters. This insulating silicon film 12 can be formed by conventional methods, such as by the thermal decomposition of silane in an atmosphere containing both a source of oxygen and the appropriate N or P type dopant. An appropriate thickness for the film 12 would be about 0.1-10μ.
The silicon film layer 12 is then selectively irradiated by laser irradiation 14. A laser pulse from a Nd-YAG laser operated at a level of 0.45 joules/cm2 has produced the results described herein. The wavelength of the radiation was 0.53 micrometers and the pulse duration was 90 nanoseconds. Although these parameters have been experimentally verified, it should be recognized that the invention is not limited to a Nd-YAG laser or these operating parameters. Other lasers, such as Nd-glass, as well as other wavelengths and combinations of power level and pulse duration should be expected to yield similar results. Additionally, multiple laser pulses can be used. For example, a multiple laser pulse might be used if one desires to monitor film resistivity changes between pulses.
The selectivity of the radiation 14 can be regulated, for example, by optically focusing the radiation 14, or by using an apertured mask 16 disposed on the silicon film 12. The mask 16 is made of a material which is opaque to the radiation 14 and it includes an aperture 18 corresponding to that portion of the insulating film 12 which will be made conductive. Any metal, for example, is a suitable mask 16 material.
Following the irradiation, the mask 16 is removed, as illustrated in FIG. 2. That portion of the film 12 which was irradiated 20 has now been rendered substantially conductive. In the cited example, the original oxygenated, doped, non-single crystalline silicon film 12 had a resistivity on the order of approximately 1011 ohm-centimeters. As a result of the described laser pulse, the irradiated portion had a resistivity of 2.4 ohm-centimeters, a drop in resistivity of approximately 11 orders of magnitude. The result is an electrically conducting film 20 adjacent to an electrically insulating film 22; a structure which can serve a variety of functions in electronic devices.
FIGS. 3, 4 and 5 illustrate three embodiments of the present invention in semiconductor devices. FIG. 3 illustrates the invention being used as an electrode/passivating layer. In this embodiment, a semiconductor substrate 110 is provided, the substrate including regions of first and second conductivity type, 24 and 26 respectively. A PN junction 28 separates the first and second semiconductor regions 24 and 26, the PN junction 28 terminating at a substrate surface 30. A silicon film 112, similar to the previously described silicon film 12, is disposed on the substrate surface 30. A conducting portion 120 of the film 112 overlies the first semiconductor region 24 and a non-irradiated portion 122 overlies the PN junction 28 at the surface 30. This embodiment is particularly suitable for use in a semiconductor power device in which the PN junction 28 supports a relatively high voltage.
In FIG. 4, the present invention is embodied in the gate structure of an insulated gate field effect transistor (IGFET). In this exemplary embodiment, a semiconductor substrate 210, of first conductivity type, is provided. The substrate 210 includes a surface 230, and source and drain regions, 31 and 32 respectively, of second conductivity type, extend into the substrate from the surface 230. A silicon film 212 similar to the previously described silicon film 12 is disposed on the semiconductor surface 230. The film 212 is selectively irradiated such that conducting portions 220 are formed over the source and drain regions 31 and 32. That portion of the film 212 between the conducting portions 220 and overlying the substrate between the source and drain regions 31 and 32 is deliberately not irradiated, so that it remains an insulating portion 222.
Electrical contacts, which may be of conventional metallization, are disposed on the silicon film 212. A source electrode 36 overlies the conducting portion 220 overlying the source region 31, a drain electrode 38 overlies the conducting portion 220 which overlies the drain region 32 and a gate electrode 40 overlies the insulating portion 222 which overlies that portion of the substrate 210 between the source and drain regions. In this embodiment, the silicon film 212 simultaneously insulates the gate electrode 40 from the substrate and connects the source and drain electrodes 36 and 38 to the respective semiconductor regions 31 and 32. Furthermore, it should be recognized that this embodiment, described with reference to a planar FET is also applicable to nonplanar field effect devices such as vertical, double-diffused MOSFETS (VDMOS) and vertical, grooved MOSFETS (VMOS).
In FIG. 5, the present invention is embodied as an interconnection. In this embodiment, a substrate 310 is provided having a surface 330 and including first and second regions 41 and 42 spaced at surface 330 by a third region 43. The substrate 310 might be, for example, a semiconductor, and the first, second and third regions, 41, 42 and 43, might be internal semiconductor regions doped with N or P type conductivity modifiers. A silicon film 312, similar to the previous described film 12, is disposed on the surface 330 and is irradiated so as to form conducting portions 320 over the first and second regions 41 and 42. That portion of the film 312 disposed over the third region 43 remains an insulating portion 322. An electrically conducting film 44 of any electrically conductive material overlies the silicon film 312 so as to electrically connect the conducting portions 320 which overlie the first and second regions 41 and 42. The conducting film 44 is insulated from the third region 43 by the insulating portion 322 of the silicon film 312 between the conducting portions 320.
It should be recognized that the illustration in FIG. 5 represents an exemplary configuration and that other interconnection embodiments of the present invention are also possible. In FIG. 5, the first, second and third regions 41, 42 and 43 are illustrated as internal to the substrate 310, however, they may be external as well. For example, spaced first and second regions might be disposed on the external surface 330 and the described interconnection structure might be disposed on the surface 330 to bridge these external first and second regions. In this example, the first and second regions might be thin conductor film lines on the surface 330 of an insulating substrate 310. This is commonly referred to as a crossover structure in the thin film and semiconductor art.
Furthermore, it should be recognized that additional interconnection structures, as well as alternative electrode/passivation and insulated gate structures are possible within the scope of the present invention. The invention is generally applicable to structures in which it is desired to generate a film which incorporates selective conducting and insulating areas.
|Brevet cité||Date de dépôt||Date de publication||Déposant||Titre|
|US3771026 *||25 mars 1971||6 nov. 1973||Hitachi Ltd||Conductive region for semiconductor device and method for making the same|
|US4014037 *||24 mars 1975||22 mars 1977||Sony Corporation||Semiconductor device|
|US4059461 *||10 déc. 1975||22 nov. 1977||Massachusetts Institute Of Technology||Method for improving the crystallinity of semiconductor films by laser beam scanning and the products thereof|
|US4063967 *||9 oct. 1975||20 déc. 1977||Siemens Aktiengesellschaft||Method of producing a doped zone of one conductivity type in a semiconductor body utilizing an ion-implanted polycrystalline dopant source|
|US4084986 *||19 avr. 1976||18 avr. 1978||Sony Corporation||Method of manufacturing a semi-insulating silicon layer|
|US4086613 *||8 déc. 1976||25 avr. 1978||U.S. Philips Corporation||Semiconductor device having a passivated surface and method of manufacturing the device|
|US4151008 *||23 mars 1977||24 avr. 1979||Spire Corporation||Method involving pulsed light processing of semiconductor devices|
|US4154625 *||16 nov. 1977||15 mai 1979||Bell Telephone Laboratories, Incorporated||Annealing of uncapped compound semiconductor materials by pulsed energy deposition|
|US4193183 *||26 juin 1978||18 mars 1980||National Semiconductor Corporation||Infrared photolithographic process for constructing self-aligned electrodes|
|US4198246 *||27 nov. 1978||15 avr. 1980||Rca Corporation||Pulsed laser irradiation for reducing resistivity of a doped polycrystalline silicon film|
|US4214918 *||12 oct. 1978||29 juil. 1980||Stanford University||Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam|
|US4229502 *||10 août 1979||21 oct. 1980||Rca Corporation||Low-resistivity polycrystalline silicon film|
|US4234358 *||5 avr. 1979||18 nov. 1980||Western Electric Company, Inc.||Patterned epitaxial regrowth using overlapping pulsed irradiation|
|US4240843 *||23 mai 1978||23 déc. 1980||Western Electric Company, Inc.||Forming self-guarded p-n junctions by epitaxial regrowth of amorphous regions using selective radiation annealing|
|US4243433 *||18 janv. 1978||6 janv. 1981||Gibbons James F||Forming controlled inset regions by ion implantation and laser bombardment|
|US4267011 *||20 sept. 1979||12 mai 1981||Tokyo Shibaura Denki Kabushiki Kaisha||Method for manufacturing a semiconductor device|
|US4272880 *||20 avr. 1979||16 juin 1981||Intel Corporation||MOS/SOS Process|
|1||*||Aggarwal, IBM-TDB, 21 (1979) 3271.|
|2||*||Beyer et al., IBM-TDB, 20 (1978) 3122.|
|3||*||Celler et al., Appl. Phys. Letts. 32 (1978) 464.|
|4||*||Chang, C. A. IBM-TDB, 20 (1977) 2459.|
|5||*||Foti et al., Appl. Phys. 15 (1978) pp. 365-369.|
|6||*||Kaplan et al., Electronics, Feb. 1980, pp. 137-142.|
|7||*||Krynicki et al., Phys. Letts., 6IA (1977) 181.|
|8||*||Lau, S.S., J. Vac. Sci. Technol. 15 (1978) 1656.|
|9||*||Narayan et al., J.Appl. Phys. 49 (1978) 3912.|
|10||*||Yaron in Digest of IEEE-Int. Electron Device Meeting, Washington, D.C., 1979, pp. 220-223.|
|Brevet citant||Date de dépôt||Date de publication||Déposant||Titre|
|US4460417 *||22 oct. 1982||17 juil. 1984||Nippon Telegraph & Telephone Public Corporation||Method of manufacturing insulating film and electric device utilizing the same|
|US4462150 *||16 sept. 1982||31 juil. 1984||Tokyo Shibaura Denki Kabushiki Kaisha||Method of forming energy beam activated conductive regions between circuit elements|
|US4545111 *||14 juil. 1983||8 oct. 1985||Energy Conversion Devices, Inc.||Method for making, parallel preprogramming or field programming of electronic matrix arrays|
|US4581620 *||29 juin 1981||8 avr. 1986||Shunpei Yamazaki||Semiconductor device of non-single crystal structure|
|US4584028 *||24 sept. 1984||22 avr. 1986||Rca Corporation||Neutralization of acceptor levels in silicon by atomic hydrogen|
|US4630355 *||8 mars 1985||23 déc. 1986||Energy Conversion Devices, Inc.||Electric circuits having repairable circuit lines and method of making the same|
|US4677742 *||5 déc. 1983||7 juil. 1987||Energy Conversion Devices, Inc.||Electronic matrix arrays and method for making the same|
|US4695479 *||12 mars 1986||22 sept. 1987||Sharp Kabushiki Kaisha||MOSFET semiconductor device and manufacturing method thereof|
|US4752118 *||14 oct. 1986||21 juin 1988||Energy Conversion Devices, Inc.||Electric circuits having repairable circuit lines and method of making the same|
|US4764432 *||1 juil. 1986||16 août 1988||Max Planck-Gesellschaft Zur Forderung Der Wissenschaften E.V.||Photo-mask with regions having a differing optical transmissivities|
|US4780428 *||10 juin 1987||25 oct. 1988||Sharp Kabushiki Kaisha||Mosfet semiconductor device and manufacturing method thereof|
|US4783424 *||21 févr. 1986||8 nov. 1988||Tokyo Shibaura Denki Kabushiki Kaisha||Method of making a semiconductor device involving simultaneous connection and disconnection|
|US5029324 *||16 avr. 1990||2 juil. 1991||Kabushiki Kaisha Toshiba||Semiconductor device having a semiconductive protection layer|
|US5047355 *||12 sept. 1989||10 sept. 1991||Siemens Aktiengesellschaft||Semiconductor diode and method for making it|
|US5145741 *||28 févr. 1991||8 sept. 1992||Quick Nathaniel R||Converting ceramic materials to electrical conductors and semiconductors|
|US5262350 *||1 juil. 1992||16 nov. 1993||Semiconductor Energy Laboratory Co., Ltd.||Forming a non single crystal semiconductor layer by using an electric current|
|US5459098 *||19 oct. 1992||17 oct. 1995||Marietta Energy Systems, Inc.||Maskless laser writing of microscopic metallic interconnects|
|US5859443 *||6 juin 1995||12 janv. 1999||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US5930658 *||26 nov. 1996||27 juil. 1999||Advanced Micro Devices, Inc.||Oxidized oxygen-doped amorphous silicon ultrathin gate oxide structures|
|US6271576 *||1 juin 1998||7 août 2001||Nathaniel R. Quick||Laser synthesized ceramic sensors and method for making|
|US6303499 *||7 juin 1995||16 oct. 2001||Canon Kabushiki Kaisha||Process for preparing semiconductor device|
|US6355941||11 janv. 1995||12 mars 2002||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US6670693||3 août 2001||30 déc. 2003||Nathaniel R. Quick||Laser synthesized wide-bandgap semiconductor electronic devices and circuits|
|US6900463||8 sept. 1992||31 mai 2005||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US6939748||13 oct. 2003||6 sept. 2005||Nathaniel R. Quick||Nano-size semiconductor component and method of making|
|US7052944 *||25 mai 2001||30 mai 2006||Nec Corporation||Thin-film transistor and method of manufacture thereof|
|US7237422||1 nov. 2005||3 juil. 2007||University Of Central Florida||Method of drawing a composite wire|
|US7262470||6 févr. 2004||28 août 2007||Sanyo Electric Co., Ltd.||Semiconductor device|
|US7268063||1 juin 2005||11 sept. 2007||University Of Central Florida||Process for fabricating semiconductor component|
|US7419887||26 juil. 2005||2 sept. 2008||Quick Nathaniel R||Laser assisted nano deposition|
|US7538394||22 déc. 2005||26 mai 2009||Sanyo Electric Co., Ltd.||Compound semiconductor switch circuit device|
|US7603883||25 juin 2007||20 oct. 2009||University Of Central Florida||Method of drawing a ceramic|
|US7645690||15 févr. 2007||12 janv. 2010||Infineon Technologies Austria Ag||Method for producing an integrated circuit having semiconductor zones with a steep doping profile|
|US7732321 *||4 mai 2005||8 juin 2010||Nds Limited||Method for shielding integrated circuits|
|US7732868||28 nov. 2002||8 juin 2010||Sanyo Electric Co., Ltd.||Semiconductor device|
|US7811914||20 avr. 2006||12 oct. 2010||Quick Nathaniel R||Apparatus and method for increasing thermal conductivity of a substrate|
|US7897492||6 oct. 2009||1 mars 2011||Quick Nathaniel R||Apparatus and method for transformation of substrate|
|US7951632||26 janv. 2006||31 mai 2011||University Of Central Florida||Optical device and method of making|
|US8067303||12 sept. 2007||29 nov. 2011||Partial Assignment University of Central Florida||Solid state energy conversion device|
|US8080836||9 juil. 2007||20 déc. 2011||University Of Central Florida||Embedded semiconductor component|
|US8393289||29 août 2008||12 mars 2013||University Of Central Florida||Laser assisted nano deposition|
|US8450805||22 déc. 2005||28 mai 2013||Semiconductor Components Industries, Llc||Compound semiconductor switch circuit device|
|US8617669||7 déc. 2010||31 déc. 2013||Partial Assignment to University of Central Florida||Laser formation of graphene|
|US8617965||25 avr. 2006||31 déc. 2013||Partial Assignment to University of Central Florida||Apparatus and method of forming high crystalline quality layer|
|US8674373||10 févr. 2012||18 mars 2014||University Of Central Florida||Solid state gas dissociating device, solid state sensor, and solid state transformer|
|US8722451||14 juil. 2011||13 mai 2014||University Of Central Florida||Solid state energy photovoltaic device|
|US8742506||18 mai 2012||3 juin 2014||Semiconductor Components Industries, Llc||Protecting element having first and second high concentration impurity regions separated by insulating region|
|US8772061||14 juil. 2011||8 juil. 2014||University Of Central Florida||Process of making a solid state energy conversion device|
|US8828769||1 déc. 2009||9 sept. 2014||University Of Central Florida||Energy conversion device|
|US8912549||3 mai 2011||16 déc. 2014||University Of Central Florida||Optical device and method of making|
|US9059079||25 sept. 2013||16 juin 2015||Ut-Battelle, Llc||Processing of insulators and semiconductors|
|US9064798||27 mai 2011||23 juin 2015||University Of Central Florida||Optical device and method of making|
|US9601641||8 déc. 2014||21 mars 2017||AppliCote Associates, LLC||Ultra-high pressure doping of materials|
|US9620667||18 nov. 2015||11 avr. 2017||AppliCote Associates LLC||Thermal doping of materials|
|US9735142||15 avr. 2014||15 août 2017||Semiconductor Components Industries, Llc||Method of forming a protecting element comprising a first high concentration impurity region separated by an insulating region of a substrate|
|US20030096462 *||25 mai 2001||22 mai 2003||Hiroshi Tanabe||Thin-film transistor and method of manufacture thereof|
|US20040222469 *||6 févr. 2004||11 nov. 2004||Sanyo Electric Co., Ltd.||Semiconductor device|
|US20050121730 *||8 sept. 2003||9 juin 2005||Tetsuro Asano||Protective device|
|US20060070420 *||1 nov. 2005||6 avr. 2006||University Of Central Florida||Method of drawing a composite wire|
|US20060151816 *||28 nov. 2002||13 juil. 2006||Sanyo Electric Co., Ltd.||Semiconductor device|
|US20060163659 *||22 déc. 2005||27 juil. 2006||Sanyo Electric Co., Ltd.||Compound semiconductor switch circuit device|
|US20060164150 *||22 déc. 2005||27 juil. 2006||Sanyo Electric Co., Ltd.||Compound semiconductor switch circuit device|
|US20070164388 *||30 mars 2007||19 juil. 2007||Sandisk 3D Llc||Memory cell comprising a diode fabricated in a low resistivity, programmed state|
|US20080017896 *||9 juil. 2007||24 janv. 2008||Quick Nathaniel R||Embedded semiconductor component|
|US20080044988 *||15 févr. 2007||21 févr. 2008||Infineon Technologies Austria Ag||Method for producing an integrated circuit having semiconductor zones with a steep doping profile|
|US20080093742 *||4 mai 2005||24 avr. 2008||Nds Limited||System For Shielding Integrated Circuits|
|US20090126627 *||29 août 2008||21 mai 2009||University Of Central Florida||Laser assisted nano deposition|
|US20100025694 *||6 oct. 2009||4 févr. 2010||Quick Nathaniel R||Apparatus and method for transformation of substrate|
|US20110031504 *||8 oct. 2010||10 févr. 2011||Quick Nathaniel R||Apparatus and method for increasing thermal conductivity of a substrate|
|US20110056542 *||1 déc. 2009||10 mars 2011||University of Central Florida, State University of the State of Florida||Energy conversion device|
|US20110211249 *||3 mai 2011||1 sept. 2011||University Of Central Florida||Optical device and method of making|
|USRE34658 *||27 janv. 1992||12 juil. 1994||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device of non-single crystal-structure|
|DE102006007052B3 *||15 févr. 2006||27 sept. 2007||Infineon Technologies Austria Ag||Semiconductor region e.g. ditch contact connection region, manufacturing method, involves maintaining topology stage in structural composition of semiconductor substrate during irradiation of semiconductor body|
|WO1998024120A1 *||20 juin 1997||4 juin 1998||Advanced Micro Devices, Inc.||Oxidized oxygen-doped amorphous silicon ultrathin gate oxide structures|
|Classification aux États-Unis||438/663, 148/DIG.3, 427/555, 257/E21.432, 148/DIG.117, 438/934, 438/618, 257/E21.347, 148/DIG.122, 148/DIG.22, 257/E21.266, 438/684, 438/799|
|Classification internationale||H01L21/314, H01L21/336, H01L21/268|
|Classification coopérative||H01L21/314, Y10S148/022, Y10S438/934, H01L21/268, H01L29/66606, Y10S148/117, Y10S148/003, Y10S148/122|
|Classification européenne||H01L29/66M6T6F11C, H01L21/314, H01L21/268|
|28 sept. 1999||AS||Assignment|
Owner name: INTERSIL CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARRIS SEMICONDUCTOR PATENTS, INC.;REEL/FRAME:010247/0161
Effective date: 19990813
|8 nov. 1999||AS||Assignment|
Owner name: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT, N
Free format text: SECURITY INTEREST;ASSIGNOR:INTERSIL CORPORATION;REEL/FRAME:010351/0410
Effective date: 19990813