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Numéro de publicationUS4464212 A
Type de publicationOctroi
Numéro de demandeUS 06/449,122
Date de publication7 août 1984
Date de dépôt13 déc. 1982
Date de priorité13 déc. 1982
État de paiement des fraisPayé
Autre référence de publicationDE3380613D1, EP0113405A2, EP0113405A3, EP0113405B1
Numéro de publication06449122, 449122, US 4464212 A, US 4464212A, US-A-4464212, US4464212 A, US4464212A
InventeursHarsaran S. Bhatia, Jacob Riseman
Cessionnaire d'origineInternational Business Machines Corporation
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Method for making high sheet resistivity resistors
US 4464212 A
A high sheet resistivity, doped semiconductor resistor is made by a process which produces a resistor diffusion or ion implantation mask having a narrow dimension determined by a "sidewall" technique. The sidewall technique defines the narrow dimension by the thickness of a doped or undoped layer deposited on a different underlying layer having horizontal and vertical surfaces. The horizontal portion of the deposited layer is removed by anistropic etching to leave only the vertical portion. The vertical portion, if undoped, is removed to define a diffused or ion-implanted resistor. The vertical portion, if doped, optionally may be removed, after heating to form a diffused resistor, or may be left in place to form a resistor in shunt with the diffused resistor.
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We claim:
1. The method of fabricating a first doped polycrystalline silicon resistor comprising:
providing a monocrystalline silicon semiconductor body;
forming a first insulator material layer upon a major surface of said body;
anisotropically etching said first layer, leaving a substantially vertical edge of said first layer where said resistor is to be formed;
forming a second layer of doped polycrystalline silicon material, having a different anisotropic etching characteristic as compared to said first layer, over said first layer;
anisotropically etching said second layer to substantially remove the horizontal portions of said second layer and leave the substantially vertical portion of said second layer on said edge of said first layer, thereby forming the body of said first resistor;
forming a third layer of said first insulator material over the resulting structure, said third layer being substantially coplanar with said vertical portion of said second layer; and
making electrical contact to the terminal portions of said first resistor body.
2. The method of claim 1 wherein said monocrystalline semiconductor body is of a first conductivity type and said doped polycrystalline silicon material is of the opposite conductivity type, and further including:
heating said resulting structure so as to diffuse the dopant from said resistor body into said semiconductor body to form a second resistor body in shunt with said first resistor body.

1. Field of the Invention

The present invention generally relates to a process for making high sheet resistivity doped semiconductor resistors and, more particularly, to a process for making such resistors characterized by very narrow and controllable width dimensions.

2. Description of the Prior Art

There is an increasing need for doped semiconductor resistors of high sheet resistivity and small dimensions for use in very large scale integrated (VLSI) circuits. One way to achieve high sheet resistivity is to reduce the width dimension of the resistor to less than a micron, e.g., of the order of 200 to 500 nanometers. This approach is preferred where total resistor size is to be kept at a minimum. The major problem to be solved is how such narrow dimensions are to be achieved for a resistor in a controllable and reproducible manner.

Conventional processes for making doped semiconductor resistors employ lithographic masking techniques for delineating the area of the resistor for diffusion or ion implantation. Light, electron beam and X-ray lithography have been used, in turn, as shorter wavelength radiation was resorted to in an effort to increase resolution to achieve the narrow dimensions desired. For reasons of insufficient resolution or undue expense and complexity or unacceptable reproducibility, each of the foreging approaches has been found to be inadequate to meet the VLSI need for high sheet resistivity doped semiconductor resistors.

So called "sidewall" processes for fabricating narrow dimensioned base, emitter and collector reach-through regions of bipolar transistors or source, drain and channel regions of field effect transistors are taught in U.S. Pat. Nos. 4,209,349 and 4,209,350, filed in the names of Irving T. Ho and Jacob Riseman on Nov. 3, 1978 and for making narrow dimensioned vertical insulating regions between conductive layers is disclosed in U.S. Pat. No. 4,234,362 filed in the name of Jacob Riseman on Nov. 3, 1978 and assigned to the present assignee. Briefly, the narrow dimension is determined by the thickness of a layer deposited upon a different underlying layer having horizontal and vertical surfaces. The horizontal portion of the deposited layer is removed by anistropic etching to leave only the vertical portion which then serves either as a mask for diffusion or ion implantation or as a shaped source of impurity in the event that the deposited layer was doped.


The present invention exploits the "sidewall" technology of the prior art to determine the narrow dimension of a diffused or ion implanted resistor of high sheet resistivity and small area. Sheet resistivity R is defined by the well-known expression R=ρ(l/w). The resistivity factor ρ can be controlled by diffusion time and temperature or by the implanted dose. The length l, normally being greater than 1 micrometer, can be established by ordinary lithographic techniques. The width w, when determined by the submicron sidewall technique in accordance with the present invention, can be made small enough and with sufficient control and reproducibility to yield the high value of sheet resistivity desired for the resistor.

In different species of the invention, the sidewall is undoped or doped and, if doped, it is either removed or left in place to become part of the final structure of the resistor.


FIGS. 1-5 are simplified cross-sectional views and FIG. 6 is a plan view of the structure resulting at respective points in the method sequence of a preferred embodiment of the present invention where the sidewall material is removed.


Only the process steps involved in making the high sheet resistivity resistor of the present invention will be described. Referring to FIG. 1, it is presumed that conventional process steps already have been exercised to form desired VLSI structures (not shown) such as, for example, subcollector, epitaxial layer and recessed oxide isolation such as shown, for example, in FIGS. 3A-3F of the aforementioned U.S. Pat. No. 4,209,350 and as described beginning on column 7, line 36. After such structures have been completed and it is desired to fabricate the resistors, a thin layer 1 of SiO2 is thermally grown on the substrate, which is epitaxial layer 2 in the example given. This is followed by the chemical vapor deposition of about 5000 Å of silicon dioxide 3.

The silicon dioxide layers 1 and 3 are selectively reactively ion etched away as shown in FIG. 2 to leave a substantially horizontal surface 4 and a substantially vertical surface 5, the latter surface defining one edge of the narrow dimension of the desired resistor. The reactive ion etching process, per se, is convenional and is described in the paper "A Survey of Plasma-Etching Processes" by Richard L. Bersin published in Solid State Technology, May 1976, pages 31 through 36 and in "Reactive Ion Etching of Silicon", J. N. Harvilchuck, et al., patent application Ser. No. 594,413 filed July 9, 1975, now abandoned, and continuation patent application Ser. No. 822,775 filed Aug. 8, 1977, now abandoned, and continuation patent application Ser. No. 960,322 filed Nov. 14, 1978, now abandoned, and continuation patent application Ser. No. 436,544 filed Oct. 25, 1982 and assigned to the assignee of the present patent application.

A blanket deposit of about 5000 Å of silicon next is placed over the structure of FIG. 2 and it is blanket reactively ion etched to remove the polycrystalline silicon from all horizontal surfaces, leaving only the vertical wall 6 of polycrystalline silicon of FIG. 3. It should be noted that any other material, such as silicon nitride, may be substituted for the polycrystalline silicon, provided that the substituted material is compatible with semiconductor device structure and processing and provided that it can be etched away without significant loss of silicon dioxide.

Approximately 5000 Å of silicon dioxide 7 is deposited over the device of FIG. 3 and, in turn, is covered by about one micrometer of resist (not shown). The composite layers are then etched away using O2 reactive ion etching for the organic resist layer and CF4 or CF4 +H2 for the SiO2 layer which removes the silicon dioxide at the same rate that is removes the resist to planarize the composite structure as shown in FIG. 4. The planarization etching is continued until the surface of vertical wall 6 is exposed as shown.

In the present embodiment, where the polysilicon is undoped, the polycrystalline silicon is removed by chemical etching in order to expose the underlying substrate (epitaxial layer 2). The exposed area is characterized by a width W separating oxides 4 and 7 which is determined with all of the precision and reproducibility with which the thickness of polycrystalline silicon 6 is controlled, whereby dimensions of the order of 200 to 500 nanometers are controllably realized. Dopant atoms are introduced into the exposed epitaxial layer by diffusion or by ion implantation to form the desired resistor 8. Contact areas 9 and 10 of FIG. 6 are delineated by conventional lithographic techniques and contacts are made thereto.

As an alternative to the deposition of 5000 Å of SiO2 to the structure of FIG. 3 as explained above, the preexisting oxide 4 can be removed (not shown) leaving a sidewall stud 6 of polycrystalline silicon. Oxide is deposited or grown over the entire article including the stud and then is covered by resist and planarized down to the polycrystalline silicon as described before.

In another embodiment of the invention, the polycrystalline silicon 6 is doped so that when the structure of FIG. 4 is reached, it is only necessary to apply heat to cause the diffusion of the dopant into the epitaxial layer beneath the polycrystalline silicon to produce the resistor 8 of FIG. 5. The doped polycrystalline silicon optionally may be left in place or removed by etching prior to the placement of contacts 9 and 10 of FIG. 6. If left in place in the final structure, the doped polycrystalline silicon itself becomes a resistor in shunt with the resistor 8 diffused into epitaxial layer 2.

Citations de brevets
Brevet cité Date de dépôt Date de publication Déposant Titre
US4209349 *3 nov. 197824 juin 1980International Business Machines CorporationMethod for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4209350 *3 nov. 197824 juin 1980International Business Machines CorporationMethod for forming diffusions having narrow dimensions utilizing reactive ion etching
US4234362 *3 nov. 197818 nov. 1980International Business Machines CorporationMethod for forming an insulator between layers of conductive material
US4298401 *19 nov. 19793 nov. 1981International Business Machines Corp.Breakdown voltage resistor obtained through a double ion-implantation into a semiconductor substrate, and manufacturing process of the same
US4332070 *15 déc. 19801 juin 1982Fairchild Camera & Instrument Corp.Method for forming a headless resistor utilizing selective diffusion and special contact formation
US4333227 *12 janv. 19818 juin 1982International Business Machines CorporationProcess for fabricating a self-aligned micrometer bipolar transistor device
Référencé par
Brevet citant Date de dépôt Date de publication Déposant Titre
US4722908 *28 août 19862 févr. 1988Fairchild Semiconductor CorporationFabrication of a bipolar transistor with a polysilicon ribbon
US4950619 *13 nov. 198921 août 1990Hyundai Electronics Industries Co., Ltd.Method for the fabrication of a high resistance load resistor utilizing side wall polysilicon spacers
US5013680 *18 juil. 19907 mai 1991Micron Technology, Inc.Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5122848 *8 avr. 199116 juin 1992Micron Technology, Inc.Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US5151376 *31 mai 199029 sept. 1992Sgs-Thomson Microelectronics, Inc.Method of making polycrystalline silicon resistors for integrated circuits
US5177027 *17 août 19905 janv. 1993Micron Technology, Inc.Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
US5250450 *12 févr. 19925 oct. 1993Micron Technology, Inc.Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
US7176553 *26 sept. 200313 févr. 2007Stmicroelectronics S.R.L.Integrated resistive elements with silicidation protection
US7566610 *30 janv. 200628 juil. 2009Alessandro GrossiProcess for manufacturing integrated resistive elements with silicidation protection
US20040119142 *26 sept. 200324 juin 2004Alessandro GrossiProcess for manufacturing integrated resistive elements with silicidation protection
US20060141730 *30 janv. 200629 juin 2006Stmicroelectronics S.R.I.Process for manufacturing integrated resistive elements with silicidation protection
Classification aux États-Unis438/384, 257/538, 257/E21.038, 438/684, 438/564, 257/E21.151, 257/E21.004
Classification internationaleH01L21/822, H01L21/3065, H01L21/02, H01L21/033, H01L27/04, H01L21/302, H01L21/225
Classification coopérativeH01L28/20, H01L21/0337, H01L21/2257
Classification européenneH01L28/20, H01L21/225A4F, H01L21/033F4
Événements juridiques
13 déc. 1982ASAssignment
Effective date: 19821209
5 nov. 1987FPAYFee payment
Year of fee payment: 4
23 oct. 1991FPAYFee payment
Year of fee payment: 8
2 janv. 1996FPAYFee payment
Year of fee payment: 12