US4513209A

US4513209A - Level detector

Info

Publication number: US4513209A
Application number: US06/348,311
Authority: US
Inventors: Kenzo Tanabe; Junji Suzuki
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1981-02-16
Filing date: 1982-02-11
Publication date: 1985-04-23
Anticipated expiration: 2002-04-23
Also published as: JPH0232585B2; GB2095937B; GB2095937A; DE3205286C2; JPS57135370A; DE3205286A1

Abstract

A level detector having good linearity and a high detection efficiency is arranged so as to be small in size and inexpensive to produce, thereby being well suited for use in a semiconductor integrated circuit. The detector employs a common emitter amplifier having two transistors connected in parallel so that odd order harmonic distortion components are mutually eliminated while DC and even order harmonic components appear at the collector thereof. The detector further includes a high impedance load for the two parallel connected transistors. The load is composed of a transistor normally biased in its active region so as to thereby raise the detection efficiency.

Description

BACKGROUND OF THE INVENTION

This invention relates to a level detector applicable to a radio receiver.

Generally, it is desirable for a level detector to have the following characteristics:

(i) good linearity (low distortion factor),

(ii) high detection efficiency,

(iii) good stability with respect to temperature variations, and

(iv) a low manufacturing cost and a small size.

A transistor detector is a well-known type of high-efficiency detector.

The conventional detector using transistors performs level detection at the base emitter junction of a transistor, so that an amplified and detected output signal is obtained at the collector thereof. This kind of detector, however, is difficult to use for realizing both a good linearity characteristic a high detection efficiency due to the following reasons:

Firstly, a heavy non-linear distortion is caused by using the non-linear characteristics of the base emitter junction of the transistor.

Secondly, it is difficult to provide a load resistor, having a high resistance value, in the monolithic semiconductor chip for realizing a high detection efficiency.

SUMMARY OF THE INVENTION

An object of the invention is to provide a level detector which can solve the above-noted problems and has a good linearity (low distortion factor) and a high detection efficiency and is small in size and inexpensive to produce, thereby being suited for a semiconductor integrated circuit.

In detail, a level detector of the invention firstly employs, emitter type amplifier comprising two transistors connected in parallel so that odd order harmonic distortion components are mutually eliminated, and DC and even order harmonic components only appear at the collector thereof, and secondly, is composed of a high impedance load realized by a transistor which is biased in its active region, thereby raising the detection efficiency.

BRIEF DESCRIPTION OF DRAWINGS

Other objects and aspects of the invention will become apparent from the following description of an embodiment with reference to the accompanying drawings in which:

FIG. 1 is a circuit diagram of a level detector of the present invention, formed in the integrated circuit, and

FIG. 2 is a graph of level detection output voltage from an output terminal with respect to an AC input signal.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, two AC signals, whose level is to be detected, and having the same signal level and having the opposite polarity are introduced to terminals 1 and 2, respectively. Reference numeral 3 designates an output terminal at the level detector of the invention, numeral 4 designates a power supply terminal for the DC power source, and numeral 5 designates a ground terminal.

Transistors Q₁, Q₂ and Q₃ are PNP type, their bases being connected altogether. The emitters of the transistors Q₁, Q₂ and Q₃ are connected to the power supply terminal 4 through bias resistors R₁, R₃ and R₄, respectively. The base and collector of transistor Q₁ are connected together the collector thereof being grounded through resistor R₂. The collectors of transistors Q₂ and Q₃ are respectively connected to the collector of transistor Q₄ and the collectors of NPN transistors Q₅ and Q₆ which are connected together. NPN transistors Q₄, Q₅ and Q₆ are grounded at the emitters thereof and connected at the bases to the collector of transistor Q₄ through base-bias resistors R₅, R₆ and R₇, respectively; the collector of transistor Q₄, as noted above, being connected to the collector of transistor Q₂. The bases of transistors Q₅ and Q₆ are connected to the input terminals 1 and 2 through AC signal coupling capacitors C₂ and C₃ respectively and the collectors of transistors Q₃, Q₅ and Q₆ are connected to the detector output terminal 3 and also grounded through a filtering capacitor C₁.

Next, the operation of the above mentioned circuit will be described.

Transistor Q₁ and resistors R₁ and R₂ construct a base-bias circuit with respect to transistors Q₂ and Q₃, the emitter currents of transistors Q₂ and Q₃ being determined by emitter resistors R₃ and R₄ thereof and the base-bias circuit. It is to be noted that the transistor Q₁ is used for compensating for the temperature dependant characteristics of the base emitter junctions of the transistors Q₂ and Q₃.

Transistors Q₄, Q₅ and Q₆ and resistors R₅, R₆ and R₇, constitute a current mirror circuit. Therefore, the collector bias currents of transistors Q₅ and Q₆ is determined by the collector current of transistor Q₄. On the other hand, since the collector of transistor Q₄ is connected to the collector of transistor Q₂, as mentioned before, the collector current in transistor Q₄ is nearly equal to that of transistor Q₂, whereby it is seen that the collector currents of transistors Q₅ and Q₆ are determined by transistor Q₂. To simplify the explanation, if it is assumed that transistors Q₄, Q₅, and Q₆ have the same characteristics, and it if is assumed that resistors R₅, R₆ and R₇ are equal in resistance, then the collector currents of transistors Q₄, Q₅ and Q₆ are nearly equal to that of transistor Q₂.

As seen from the circuit diagram in FIG. 1, the sum of the collector currents of transistors Q₅ and Q₆ is equal to the collector current of transistor Q₃.

Now, when the circuit is so designed so that the resistance value of resistor R₄ is made considerably smaller than that of resistor R₃, so that the emitter current of transistor Q₃ becomes larger than the sum of the collector currents of transistors Q₅ and Q₆ (the sum determined by the emitter current of transistor Q₂), transistor Q₃ has its operating point in its saturation region.

This invention is characterized firstly in that the operating point of the transistor Q₃, when an input signal is not present or too small, is set to be in its saturation region.

FIG. 2 shows the change of level detection output voltage V_out from an output terminal 3 in FIG. 1 with respect to an AC input signal voltage V_in applied between terminals 1 and 2 in FIG. 1. The level detection output voltage V_out is high when the AC input signal voltage V_in is smaller than V_x because the transistor Q₃ operates in its saturation region.

Next, the operation of the circuit shown in FIG. 1 will be described under the condition where two AC input signals having the same signal level and the opposite polarity are applied to terminals 1 and 2, respectively. The AC input signals are applied to the bases of transistors Q₅ and Q₆ through coupling capacitors C₂ and C₃, respectively.

It is well known that a rectified output signal is obtained at the collectors of transistors Q₅ and Q₆ when the applied AC input signals are so large that they overdrive the base to emitter junctions thereof.

The alternating current component included in the aforesaid rectified output signal is removed by the aforesaid filtering capacitor C₁, so that only a rectified DC component corresponding to the level of the input AC signals is applied to the collector of transistor Q₃. Hence, the collector current of transistor Q₃ increases as the AC input level increases, so that the operating point of transistor Q₃ is changed from its saturation region into its active region.

At this point, transistor Q₃ acts as a load resistor, having a large resistance value, for the transistors Q₅ and Q₆.

Referring to FIG. 2, the operating point of transistor Q₃, as shown, is driven into the active region in the vicinity of an input level V_x.

When the level of the input AC signal V_in applied between the input terminals 1 and 2 is large enough to overdrive the base-emitter junctions of the transistors Q₅ and Q₆, a rectified DC signal is produced at the collectors of the transistors Q₅ and Q₆. The rectified DC signal increases with the further increase of the input AC signal V_in, so that the operating point of the transistor Q₃ moves toward the active region of the transistor Q₃. And finally, when the level of the input AC signal V_in reaches the level equal to V_x, the operating point of the transistor Q₃ reaches the active region of the transistor Q₃. Accordingly, the collector of the transistor Q₃, or the output voltage V_out, decreases as shown in FIG. 2.

The level detector of the invention, which provides rectifying transistors Q₅ and Q₆ in parallel and which needs two AC input signals of opposite polarity with same signal level, may be simplified by omitting either transistor Q₅ or Q₆. However, in this instance, since the input signals to be rectified are usually intermediate frequency signals, in some cases, more than two signals close in frequency exist as said intermediate frequency signals according to a certain receiving condition.

In the above-noted case, a rectifier circuit which omits either transistor Q₅ and Q₆ generates high intermodulation products with a high input level due to the non-linearity of the base-emitter junction of transistor Q₆ and Q₅. Some of these intermodulation products are irregularly coupled to the input of the intermediate frequency amplifier and detector which causes a distorted sound.

This invention is characterized in that the transistors Q₅ and Q₆ are provided in parallel so as to eliminate the odd order intermodulation product, which is very harmful as mentioned above, by balancing out said odd order intermodulation products at their collectors.

The level detector of the invention is advantageous in:

(1) having a low distortion factor, because of a pair of ground emitter--amplifiers, having the collectors thereby connected together and which are the basic elements of the detector, are constructed essentially so as not to generate odd order harmonic distortion;

(2) having a high detection efficiency, because the active load transistor, used as the load resistor, has a high load impedance;

(3) having good stability with respect to the temperature variations, because the operating point of the detector is determined by the temperature compensated current mirror circuit; and

(4) being easy to realize in a monolithic integrated semiconductor chip.

In addition, although the collector currents of transistors Q₅ and Q₆ in FIG. 1 are determined by transistor Q₄ according to the principle of the current mirror for the convenience of explanation, other circuit configurations could of course be desirably adoptive within the scope of this invention.

Claims

What is claimed is:

1. A level detector comprising:

first and second transistors of a first conductivity type, said first and second transistors having their bases connected together;

a third transistor of a second conductivity type opposite to that of said first conductivity type;

a resistor connected between said third transistor's base and collector;

fourth and fifth transistors of said second conductivity type, said fourth and fifth transistors having their collectors connected together;

a DC bias circuit operatively connected to said bases of said first and second transistors for supplying a DC bias thereto;

wherein said first transistor's collector is connected to said third transistor's collector, said fourth and fifth transistors' bases are respectively connected to said third transistor's collector through separate resistors, said first and second transistors' emitters are respectively connected to a first terminal of a DC power supply through separate resistors, said third and fourth and fifth transistors' emitters are connected to a second terminal of said power supply, said second transistor's collector is connected to said fourth and said fifth transistors' collectors;

wherein AC signals having the same amplitude but of opposite polarities are respectively supplied to said fourth and fifth transistors' bases and a level detected output signal is provided at said common collectors of said second and fourth and fifth transistors, and wherein said second transistor is biased in its saturation region when said AC signals are of zero amplitude levels.

2. A level detector as recited in claim 1, wherein said DC bias circuit comprises an additional transistor having its base connected to its collector and having its collector connected to said second terminal of said DC power supply through a resistor and having its emitter connnected to said first terminal of said DC power supply through another resistor and having its collector supplying said DC bias to said bases of said first and second transistors.