US4723224A - Content addressable memory having field masking - Google Patents
Content addressable memory having field masking Download PDFInfo
- Publication number
- US4723224A US4723224A US06/815,610 US81561086A US4723224A US 4723224 A US4723224 A US 4723224A US 81561086 A US81561086 A US 81561086A US 4723224 A US4723224 A US 4723224A
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- cam
- selectively
- cam cells
- operand
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/903—Querying
- G06F16/90335—Query processing
- G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
Definitions
- CAM content addressable memory
- RWM read/write memory
- CAM content addressable memory
- Another object is to provide a CAM which requires minimal circuitry to provide field maskability.
- Yet another object of the present invention is to provide a field maskable CAM cell wherein all cells are identical in structure.
- a content addressable memory including a plurality of CAM cells, each of which comprises a memory cell for selectively storing a respective one of a plurality of bits comprising a first operand; and gating logic for selectively coupling a first line to a second line only if a respective one of the bits comprising a second operand does not match the bit stored in the respective memory cell; and control logic, generally responsive to a mask signal, for selectively preventing a predetermined subset of the CAM cells from coupling the first line to the second line.
- CAM content addressable memory
- the subset of the CAM cells is arranged so that the gating logic thereof selectively couples a first portion of the first line to the second line and the balance of the CAM cells is arranged so that the gating logic thereof selectively couples a second portion of the first line to the second line.
- the control logic comprises a coupler, responsive to the mask signal and interposed in the first line between the first and second portions thereof, for decoupling the first portion from the second portion in response to the mask signal.
- the mask signal comprises the bit stored in one of the CAM cells.
- FIG. 1 is a schematic diagram of a content addressable memory (CAM) cell suitable for use with the present invention.
- CAM content addressable memory
- FIG. 2 is a block diagram illustrating a content addressable memory comprising a plurality of the CAM cells of FIG. 1, wherein a field of the CAM cells are selectively masked by one of the CAM cells.
- FIG. 1 Shown in FIG. 1 is a content addressable memory (CAM) cell 10 comprised of a static read/write memory (RWM) cell 12 and an EXCLUSIVE OR (XOR) gate 14.
- RWM cell 12 is comprised of a pair of cross-coupled inverters 16-18 having respective inputs and outputs, and a pair of coupling transistors 20-22 which couple the inputs of the inverters 16-18 to respective complementary input (IN-IN*) lines 24-26 in response to a read/write (R/W) signal on line 28.
- XOR gate 14 is comprised of a pair of transistors 30-32, each of which is coupled in series between a respective one of the input lines 24-26 and an output node 34 with the gate thereof coupled to the output of an appropriate one of the inverters 16-18.
- transistors 30-32 are N-channel devices and thus have the gates thereof coupled to the outputs of the complementary inverters 16-18, respectively.
- transistors 30-32 may be P-channel devices if desired, and, if so, the gates thereof would then be coupled to the outputs of the corresponding inverters 18-16, respectively.
- RWM cell 12 operates as a conventional static memory to retain the logic state of an operand bit provided by suitable driver circuitry 36 as complementary logic states on the input lines 24-26 while the R/W signal is active.
- the operand bit is a logic ONE
- a high on the R/W line 28 will enable coupler 20/22 to couple the high/low on IN/IN* line 24/26 to the input of inverter 16/18, respectively.
- the output of inverter 16/18 will maintain the low/high on the input of inverter 18/16, respectively.
- R/W line 28 goes low, the operand bit stored in the RWM cell 12 will be a logic ONE.
- the operand bit is a logic ZERO
- the low/high on input lines 24/26 will result in the output of inverter 16/18 being high/low, respectively, and, after R/W goes low, the operand bit stored in the RWM cell 12 will be a logic ZERO.
- XOR gate 14 operates to provide a high on node 34 only if-the logic state of an operand bit presented on the input lines 24-26 differs from the logic state of the operand bit stored in the RWM cell 12.
- the operand bit stored in the RWM cell 12 and the operand bit on the input lines 24-26 are both logic ONE, the high on the output of inverter 18 will turn on transistor 32 and couple the node 34 to the low on IN* line 26.
- the high on the output of inverter 16 will turn on transistor 30 and couple the node 34 to the low on IN line 24.
- the output of the XOR 14 will be a low.
- the operand bit stored in the RWM cell 12 is a logic ONE and the operand bit on the input lines 24-26 is a logic ZERO
- the high on the output of inverter 18 will turn on transistor 32 and couple the node 34 to the high which is now on IN* line 26.
- the operand bit stored in the RWM cell 12 is a logic ZERO and the operand bit on the input lines 24-26 is a logic ONE
- the high on the output of inverter 16 will turn on transistor 30 and couple the node 34 to the high which is now on IN line 24.
- the output of the XOR 14 will be a high.
- the output of the XOR 14 on output node 34 may be utilized directly, the preferred form includes a buffer transistor 38 coupled between a sense line 40 and a ground line 42 with the gate thereof coupled to the output node 34.
- the sense line 40 will be coupled to the ground line 42 by the transistor 38 only if the output of the XOR 14 is a high, indicating that the input operand bit does not match the stored operand bit.
- the use of transistor 38 to buffer the output of XOR 14 allows different sensing schemes to be used.
- a conventional precharge-discharge virtual ground mechanism may be adequate to sense the outputs of a set of the CAM cells 12 which are coupled in parallel to form an individually addressable word.
- a transistor 44 might be used to precharge the sense line 40 during one phase of a CLOCK signal, while the ground line 42 is isolated from ground by a transistor 46.
- the driver circuitry 36 may be enabled so that each CAM cell 10 can be comparing a respective input operand bit to the operand bit stored therein. If there is a match in a particular CAM cell 12, the output of that cell's XOR 14 will be low and transistor 38 will be off; otherwise, the output of that XOR 14 will be high and transistor 38 will be on.
- transistor 44 will be off and transistor 46 will be on. If the transistor 38 of every CAM cell 10 is off, indicting a match of all input operand bits to all stored operand bits, sense line 40 will remain precharged and the output of a clocked buffer 48 will be high. However, if the transistor 38 of even one of the CAM cells 12 is on, indicating a mismatch in the corresponding bit position, sense line 40 will be discharged and the output of the buffer 48 will be low.
- a self-biased sense amplifier 50 is employed to continuously sense the state of the sense line 40.
- a current limiting transistor 52 is used to limit the rate of discharge of the sense line 40 via the ground line 42.
- the use of current limiting also allows the sense amplifier 50 to operate significantly faster and more reliably over process.
- a CAM array 54 can be easily formed by connecting a plurality of the CAM cells 10 in parallel to form each of a plurality of individually addressable "words".
- the CAM cells 10 in corresponding bit positions of all words can share the same pair of input lines 24-26.
- all of the CAM cells 10 in a particular word can share the same R/W line 28, sense line 40 and ground line 42. This form is particularly advantageous if certain subsets or fields of the bits of each word are to be selectively masked during the match operation in response to a mask signal.
- the CAM cells 10 which are to store this maskable field can be arranged so that the output transistors 38 thereof are all coupled to the same severable portions of the sense line 40 and ground line 42, while the balance of the CAM cells 10 are arranged so that the output transistors 38 thereof are all coupled to the main portions of lines 40-42.
- the coupler 54 is interposed in the ground line 42 rather than the sense line 40.
- the mask signal may even comprise the bit stored in one of the CAM cells 10.
- that CAM cell 10 be arranged so as to be adjacent to the coupler 54 to faciltate layout.
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US06/815,610 US4723224A (en) | 1986-01-02 | 1986-01-02 | Content addressable memory having field masking |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/815,610 US4723224A (en) | 1986-01-02 | 1986-01-02 | Content addressable memory having field masking |
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US4723224A true US4723224A (en) | 1988-02-02 |
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US06/815,610 Expired - Fee Related US4723224A (en) | 1986-01-02 | 1986-01-02 | Content addressable memory having field masking |
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Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989009966A2 (en) * | 1988-04-08 | 1989-10-19 | Allied-Signal Inc. | Computer system with distributed associative memory |
US4928260A (en) * | 1988-05-11 | 1990-05-22 | Advanced Micro Devices, Inc. | Content addressable memory array with priority encoder |
US4932053A (en) * | 1988-11-10 | 1990-06-05 | Sgs-Thomson Microelectronics, S.A. | Safety device against the unauthorized detection of protected data |
EP0507208A2 (en) * | 1991-04-02 | 1992-10-07 | Motorola, Inc. | A data processing system with combined static and dynamic masking of information in an operand |
EP0507209A2 (en) * | 1991-04-02 | 1992-10-07 | Motorola, Inc. | A data processor with concurrent independent static and dynamic masking of operand information |
US5301141A (en) * | 1992-05-01 | 1994-04-05 | Intel Corporation | Data flow computer with an articulated first-in-first-out content addressable memory |
US5333127A (en) * | 1991-06-17 | 1994-07-26 | Mitsubishi Denki Kabushiki Kaisha | Memory circuit with dual sense amplifier and amplifier control circuitry |
US5386413A (en) * | 1993-03-19 | 1995-01-31 | Bell Communications Research, Inc. | Fast multilevel hierarchical routing table lookup using content addressable memory |
US5444649A (en) * | 1993-06-10 | 1995-08-22 | Apple Computer, Inc. | Associative memory system having configurable means for comparing fields in an array of stored data words with corresponding one or more fields in a supplied argument word |
US5446685A (en) * | 1993-02-23 | 1995-08-29 | Intergraph Corporation | Pulsed ground circuit for CAM and PAL memories |
US5452355A (en) * | 1994-02-02 | 1995-09-19 | Vlsi Technology, Inc. | Tamper protection cell |
US5491806A (en) * | 1990-06-26 | 1996-02-13 | Lsi Logic Corporation | Optimized translation lookaside buffer slice having stored mask bits |
EP0858077A2 (en) * | 1997-02-06 | 1998-08-12 | Nortel Networks Corporation | Content addressable memory |
US6046923A (en) * | 1999-01-13 | 2000-04-04 | Lucent Technologies Inc. | Content-addressable memory architecture with column muxing |
US6101116A (en) * | 1999-06-30 | 2000-08-08 | Integrated Device Technology, Inc. | Six transistor content addressable memory cell |
US6128207A (en) * | 1998-11-02 | 2000-10-03 | Integrated Device Technology, Inc. | Low-power content addressable memory cell |
US6181591B1 (en) * | 1998-10-29 | 2001-01-30 | International Business Machines Corporation | High speed CAM cell |
US6275406B1 (en) | 1999-09-10 | 2001-08-14 | Sibercore Technologies, Inc. | Content address memory circuit with redundant array and method for implementing the same |
US6339539B1 (en) | 1999-09-10 | 2002-01-15 | Sibercore Technologies, Inc. | Content addressable memory having read/write capabilities that do not interrupt continuous search cycles |
US6362990B1 (en) | 1999-09-10 | 2002-03-26 | Sibercore Technologies | Three port content addressable memory device and methods for implementing the same |
US6392910B1 (en) | 1999-09-10 | 2002-05-21 | Sibercore Technologies, Inc. | Priority encoder with multiple match function for content addressable memories and methods for implementing the same |
US6418042B1 (en) * | 1997-10-30 | 2002-07-09 | Netlogic Microsystems, Inc. | Ternary content addressable memory with compare operand selected according to mask value |
US6502163B1 (en) | 1999-12-17 | 2002-12-31 | Lara Technology, Inc. | Method and apparatus for ordering entries in a ternary content addressable memory |
US6553453B1 (en) | 1999-09-10 | 2003-04-22 | Sibercore Technologies, Inc. | Variable width content addressable memory device for searching variable width data |
US6745280B2 (en) | 2002-03-28 | 2004-06-01 | Integrated Device Technology, Inc. | Content addressable memories having entries stored therein with independently searchable weight fields and methods of operating same |
US20050066115A1 (en) * | 2003-09-24 | 2005-03-24 | Kuldeep Simha | Content addressable memory |
US7050317B1 (en) * | 2002-03-15 | 2006-05-23 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices that support power saving longest prefix match operations and methods of operating same |
US20060181908A1 (en) * | 2005-02-11 | 2006-08-17 | International Business Machines Corporation | Method and apparatus for controlling the timing of precharge in a content addressable memory system |
US7116569B2 (en) | 2005-02-11 | 2006-10-03 | International Business Machines Corporation | Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask |
US20060279855A1 (en) * | 2005-06-08 | 2006-12-14 | Hon Hai Precision Industry Co., Ltd. | Lens system for digital camera |
US7187571B1 (en) | 2004-04-09 | 2007-03-06 | Integrated Device Technology, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
US7283404B2 (en) | 2005-02-11 | 2007-10-16 | International Business Machines Corporation | Content addressable memory including a dual mode cycle boundary latch |
US7570503B1 (en) | 2005-05-20 | 2009-08-04 | Netlogic Microsystems, Inc. | Ternary content addressable memory (TCAM) cells with low signal line numbers |
USRE41351E1 (en) | 2000-05-18 | 2010-05-25 | Netlogic Microsystems, Inc. | CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same |
GB2529221A (en) * | 2014-08-14 | 2016-02-17 | Ibm | Content addressable memory cell and array |
Citations (1)
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DE3105503A1 (en) * | 1981-02-14 | 1982-09-02 | Brown, Boveri & Cie Ag, 6800 Mannheim | ASSOCIATIVE ACCESS MEMORY |
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1986
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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DE3105503A1 (en) * | 1981-02-14 | 1982-09-02 | Brown, Boveri & Cie Ag, 6800 Mannheim | ASSOCIATIVE ACCESS MEMORY |
Non-Patent Citations (2)
Title |
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J. C. Hou, "CAM Cell for Use in Hybrid Memory Scheme", IBM Technical Disclosure Bulletin, vol. 26, No. 8, Jan. 1984, pp. 4331-4334. |
J. C. Hou, CAM Cell for Use in Hybrid Memory Scheme , IBM Technical Disclosure Bulletin, vol. 26, No. 8, Jan. 1984, pp. 4331 4334. * |
Cited By (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989009966A3 (en) * | 1988-04-08 | 1990-03-08 | Allied Signal Inc | Computer system with distributed associative memory |
WO1989009966A2 (en) * | 1988-04-08 | 1989-10-19 | Allied-Signal Inc. | Computer system with distributed associative memory |
US4928260A (en) * | 1988-05-11 | 1990-05-22 | Advanced Micro Devices, Inc. | Content addressable memory array with priority encoder |
US4932053A (en) * | 1988-11-10 | 1990-06-05 | Sgs-Thomson Microelectronics, S.A. | Safety device against the unauthorized detection of protected data |
US5546555A (en) * | 1990-06-26 | 1996-08-13 | Lsi Logic Corporation | Optimized translation lookaside buffer slice having stored mask bits |
US5491806A (en) * | 1990-06-26 | 1996-02-13 | Lsi Logic Corporation | Optimized translation lookaside buffer slice having stored mask bits |
US6125433A (en) * | 1990-06-26 | 2000-09-26 | Lsi Logic Corporation | Method of accomplishing a least-recently-used replacement scheme using ripple counters |
EP0507208A2 (en) * | 1991-04-02 | 1992-10-07 | Motorola, Inc. | A data processing system with combined static and dynamic masking of information in an operand |
EP0507209A2 (en) * | 1991-04-02 | 1992-10-07 | Motorola, Inc. | A data processor with concurrent independent static and dynamic masking of operand information |
EP0507209A3 (en) * | 1991-04-02 | 1994-04-20 | Motorola Inc | |
EP0507208A3 (en) * | 1991-04-02 | 1994-04-20 | Motorola Inc | |
US5333127A (en) * | 1991-06-17 | 1994-07-26 | Mitsubishi Denki Kabushiki Kaisha | Memory circuit with dual sense amplifier and amplifier control circuitry |
US5301141A (en) * | 1992-05-01 | 1994-04-05 | Intel Corporation | Data flow computer with an articulated first-in-first-out content addressable memory |
US5446685A (en) * | 1993-02-23 | 1995-08-29 | Intergraph Corporation | Pulsed ground circuit for CAM and PAL memories |
US5386413A (en) * | 1993-03-19 | 1995-01-31 | Bell Communications Research, Inc. | Fast multilevel hierarchical routing table lookup using content addressable memory |
US5444649A (en) * | 1993-06-10 | 1995-08-22 | Apple Computer, Inc. | Associative memory system having configurable means for comparing fields in an array of stored data words with corresponding one or more fields in a supplied argument word |
US5452355A (en) * | 1994-02-02 | 1995-09-19 | Vlsi Technology, Inc. | Tamper protection cell |
EP0858077A2 (en) * | 1997-02-06 | 1998-08-12 | Nortel Networks Corporation | Content addressable memory |
EP0858077A3 (en) * | 1997-02-06 | 1999-12-15 | Nortel Networks Corporation | Content addressable memory |
US6418042B1 (en) * | 1997-10-30 | 2002-07-09 | Netlogic Microsystems, Inc. | Ternary content addressable memory with compare operand selected according to mask value |
US6181591B1 (en) * | 1998-10-29 | 2001-01-30 | International Business Machines Corporation | High speed CAM cell |
US6128207A (en) * | 1998-11-02 | 2000-10-03 | Integrated Device Technology, Inc. | Low-power content addressable memory cell |
USRE39227E1 (en) * | 1998-11-02 | 2006-08-08 | Integrated Device Technology, Inc. | Content addressable memory (CAM) arrays and cells having low power requirements |
US6046923A (en) * | 1999-01-13 | 2000-04-04 | Lucent Technologies Inc. | Content-addressable memory architecture with column muxing |
US6101116A (en) * | 1999-06-30 | 2000-08-08 | Integrated Device Technology, Inc. | Six transistor content addressable memory cell |
US6362990B1 (en) | 1999-09-10 | 2002-03-26 | Sibercore Technologies | Three port content addressable memory device and methods for implementing the same |
US6275406B1 (en) | 1999-09-10 | 2001-08-14 | Sibercore Technologies, Inc. | Content address memory circuit with redundant array and method for implementing the same |
US6339539B1 (en) | 1999-09-10 | 2002-01-15 | Sibercore Technologies, Inc. | Content addressable memory having read/write capabilities that do not interrupt continuous search cycles |
US6553453B1 (en) | 1999-09-10 | 2003-04-22 | Sibercore Technologies, Inc. | Variable width content addressable memory device for searching variable width data |
US6609222B1 (en) | 1999-09-10 | 2003-08-19 | Sibercore Technologies, Inc. | Methods and circuitry for built-in self-testing of content addressable memories |
US6392910B1 (en) | 1999-09-10 | 2002-05-21 | Sibercore Technologies, Inc. | Priority encoder with multiple match function for content addressable memories and methods for implementing the same |
USRE41992E1 (en) | 1999-09-10 | 2010-12-07 | Sanjay Gupta | Methods and circuitry for built-in self-testing of content addressable memories |
USRE41659E1 (en) | 1999-09-10 | 2010-09-07 | Sanjay Gupta | Methods and circuitry for built-in self-testing of content addressable memories |
US6502163B1 (en) | 1999-12-17 | 2002-12-31 | Lara Technology, Inc. | Method and apparatus for ordering entries in a ternary content addressable memory |
USRE41351E1 (en) | 2000-05-18 | 2010-05-25 | Netlogic Microsystems, Inc. | CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same |
US7050317B1 (en) * | 2002-03-15 | 2006-05-23 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices that support power saving longest prefix match operations and methods of operating same |
US6745280B2 (en) | 2002-03-28 | 2004-06-01 | Integrated Device Technology, Inc. | Content addressable memories having entries stored therein with independently searchable weight fields and methods of operating same |
GB2406686B (en) * | 2003-09-24 | 2006-06-07 | Hewlett Packard Development Co | Content addressable memory |
GB2406686A (en) * | 2003-09-24 | 2005-04-06 | Hewlett Packard Development Co | Enabling access to a subset of content addressable memory fields |
US20050066115A1 (en) * | 2003-09-24 | 2005-03-24 | Kuldeep Simha | Content addressable memory |
US7146457B2 (en) | 2003-09-24 | 2006-12-05 | Hewlett-Packard Development Company, L.P. | Content addressable memory selectively addressable in a physical address mode and a virtual address mode |
US7859876B1 (en) | 2004-04-09 | 2010-12-28 | Netlogic Microsystems, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
US7545660B1 (en) | 2004-04-09 | 2009-06-09 | Integrated Device Technology, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
US7187571B1 (en) | 2004-04-09 | 2007-03-06 | Integrated Device Technology, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
US7248492B1 (en) | 2004-04-09 | 2007-07-24 | Integrated Device Technology, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
US7522438B1 (en) | 2004-04-09 | 2009-04-21 | Integrated Device Technology, Inc. | Method and apparatus for CAM with reduced cross-coupling interference |
US7116569B2 (en) | 2005-02-11 | 2006-10-03 | International Business Machines Corporation | Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask |
US7283404B2 (en) | 2005-02-11 | 2007-10-16 | International Business Machines Corporation | Content addressable memory including a dual mode cycle boundary latch |
US7167385B2 (en) | 2005-02-11 | 2007-01-23 | International Business Machines Corporation | Method and apparatus for controlling the timing of precharge in a content addressable memory system |
US20060181908A1 (en) * | 2005-02-11 | 2006-08-17 | International Business Machines Corporation | Method and apparatus for controlling the timing of precharge in a content addressable memory system |
US7570503B1 (en) | 2005-05-20 | 2009-08-04 | Netlogic Microsystems, Inc. | Ternary content addressable memory (TCAM) cells with low signal line numbers |
US20060279855A1 (en) * | 2005-06-08 | 2006-12-14 | Hon Hai Precision Industry Co., Ltd. | Lens system for digital camera |
GB2529221A (en) * | 2014-08-14 | 2016-02-17 | Ibm | Content addressable memory cell and array |
US20160049198A1 (en) * | 2014-08-14 | 2016-02-18 | International Business Machines Corporation | Content addressable memory cell and array |
US10553282B2 (en) * | 2014-08-14 | 2020-02-04 | International Business Machines Corporation | Content addressable memory cell and array |
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