US5028979A - Table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder - Google Patents

Table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder Download PDF

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Publication number
US5028979A
US5028979A US07/488,148 US48814890A US5028979A US 5028979 A US5028979 A US 5028979A US 48814890 A US48814890 A US 48814890A US 5028979 A US5028979 A US 5028979A
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lines
drain
field oxide
strips
source
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US07/488,148
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Stefano Mazzali
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STMicroelectronics SRL
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SGS Thomson Microelectronics SRL
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Assigned to SGS-THOMSON MICROELECTRONICS S.R.L. reassignment SGS-THOMSON MICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MAZZALI, STEFANO
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder.
  • Another problem of this structure is represented by the low capacitative coupling between the control gate and the floating gate of each cell, due to the fact that the coupling area between the two gates is practically equal to that between the floating gate and the substrate. This implies a value of the capacitative ratio which is too low to obtain good writing characteristics of the cell.
  • a cell matrix having a "table cloth” structure which comprises field oxide areas formed on the cell substrate perpendicularly to the source and drain lines and lateral fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.
  • a decoder typical of the "table cloth” structure, which is more complicated than the traditional one.
  • the object of the present invention is to accomplish a matrix with a "table cloth" structure with buried junctions which, in addition to improving the capacitative ratio, will also allow the use of a traditional-type decoder, with a consequent shorter access time, less circuit complexity and higher cell density.
  • a table cloth matrix of EPROM memory cells comprising source lines and drain lines parallel and alternated with one another, inserted in buried layers of a substrate under strips of field oxide, floating gate areas connecting said source lines and drain lines with lateral fins superimposed over said strips of field oxide, and control gate lines parallel to one another and perpendicular to said source lines and drain lines in a condition superimposed over said floating gate areas, so as to define a plurality of rows of memory cells parallel to one another, characterized in that each source line is alternated with a pair of drain lines separated by an insulation area obtained in the substrate, so that each drain line is associated with one and only one of said rows of cells.
  • each drain line is assigned to a single row of cells, and not to two rows as in the traditional technique, it is possible to access one individual cell with a traditional, faster and simpler decoder, and thus with a lower utilization of space.
  • FIG. 1 is a perspective cross-section of a portion of a matrix of EPROM memory cells according to the invention
  • FIG. 2 is a plan view from above of a part of said matrix of memory cells
  • FIGS. 3, 4, 5, 6 and 7 show enlarged details of said matrix in cross-section taken along the lines III--III, IV--IV, V--V-VI--VI and VII--VII of FIG. 2.
  • the matrix shown in the drawings comprises a silicon substrate 1, wherein there are obtained in buried layers parallel source lines 2, alternated with pairs of parallel drain lines 3.
  • the two drain lines 3 are separated by insulation strips 4, while insulation strips 6 are provided at the sides of the drain lines 2.
  • each source line 2 there is grown a thick strip of field oxide 5; similarly, on each pair of adjacent drain lines 3 there is grown a thick strip of field oxide 7, more extensive than the strips of field oxide 5 (FIG. 1).
  • Said strips of field oxide 5 and 7 are alternated with said insulation strips 4 and 6.
  • each source line 2 and drain line 3 there are defined gate oxide areas 8, partially superimposed over said field oxide strips 5 and 7 by means of asymmetrical fins 10 and 11 (FIG. 3), the larger fin 10 being superimposed over the corresponding oxide strip 7, the smaller fin 11 being superimposed over oxide strip 5.
  • the oxide areas 8 are each coated by a floating gate area 9, say of polysilicon, with asymmetrical fins 12 and 13 (FIG. 3) superimposed over fins 10 and 11, respectively, of the underlying gate oxide areas 8.
  • control gate lines 15 the so-called “word lines”
  • the matrix is thus constituted by a plurality of EPROM memory cells arranged in a table cloth pattern, each of which is conformed like the one indicated with 16 (FIGS. 2 and 3), that is, it has a floating gate area 9 interposed between a source line 2 and drain line 3, and a control gate line 15 perpendicular to the source lines 2 and the drain lines 3, the floating gate 9 having two asymmetrical lateral fins 12 and 13 partially superimposed over the underlying oxide strips 5 and 7 and being interposed between a gate oxide area 8 and a layer of dielectric 14.
  • the oxide strips 5 and 7 have the task of increasing the distance between drain lines 3 and source lines 4 and the floating gate areas 9. In combination with the large contact surface between floating gate areas 9 and the oxide 5 and 7, obtained thanks to fins 12 and 13, this allows the attainment of an excellent capacitative coupling.
  • each drain line 3 is common to only one row of cells 16, each of which is thus accessible through a traditional decoder, which is simpler and occupies a more limited space.

Abstract

The table cloth matrix comprises a semiconductor substrate, wherein there are contained in deep layers, under strips of field oxide, source lines and drain lines parallel to one another, areas of floating gate connecting said source lines and drain lines and control gate lines, parallel to one another and perpendicular to said source lines and drain lines, in a condition superimposed over said floating gate areas. Each source line is alternated with two drain lines separated by an insulation zone, so that each drain line is associated with a single row of matrix cells.

Description

DESCRIPTION
The present invention relates to a table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder.
In the manufacture of memory matrices one of the fundamental problems is to increase the density of the cells as much as possible, so as to improve performance and to exploit the available area better. This implies the search for and the use of increasingly advanced technolgies, particularly in the area of photolithography, wherein the definition of smaller and smaller structures is required, down to submicrometric dimensions. In spite of such technolgies it is more and more difficult to compact the devices, so that research is now oriented towards new structures with which to overcome these problems.
In the field of EPROM memory cells a step ahead in this sense has been made with the accomplishment of the so-called "table cloth" matrix wherein two groups of source lines and one group of drain lines parallel and alternated with one another are intersected perpendicularly by control gate lines parallel to one another, while floating gate areas are interposed between said source and drain lines beneath said control gate lines.
The new configuration, better described in the Italian patent application No. 23479 A/84 dated Nov. 7, 1984, which corresponds to U.S. Pat. No. 4,792,925 assigned to the assignee of the present application, has proved advantageous as regards dimensional problems, attaining levels of miniaturization, cell density and compactness of considerable interest. The decoder required to access the individual cells has, on the other hand, proved very complex, as it is necessary to distinguish one group of source lines from the other, as well as to address the appropriate drain and control gate lines.
Another problem of this structure is represented by the low capacitative coupling between the control gate and the floating gate of each cell, due to the fact that the coupling area between the two gates is practically equal to that between the floating gate and the substrate. This implies a value of the capacitative ratio which is too low to obtain good writing characteristics of the cell.
A solution for improving said capacitative ratio is proposed in the Italian patent application No. 22848 A/88 dated Dec. 5 1988, which corresponds to U.S. Pat. No. 444,796 filed Dec. 1, 1988 and assigned to the assignee of the present application.
In this patent application there is again provided a cell matrix having a "table cloth" structure which comprises field oxide areas formed on the cell substrate perpendicularly to the source and drain lines and lateral fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas. In this cell, however, it is necessary to have a decoder, typical of the "table cloth" structure, which is more complicated than the traditional one. In addition, it is not possible to compact this structure further, to keep the minimum distance between the control gate lines.
Some time ago a "table cloth" matrix was also accomplished based on drain and source lines alternated with one another, included in buried layers of the substrate, with superimposed field oxide, on which there rest lateral fins of the floating gate. In this way, through the field oxide, the floating gate is separated from the drain or the source lines, while thanks to the above mentioned lateral fins an extensive coupling area is ensured between the floating gate and the control gate and a consequent better capacitative ratio.
The performance of this latter structure is in practice fairly poor, particularly for the long time necessary to access the individual cell, due to the fact that a same drain line is common to two rows of cells, so that to address an individual cell it is necessary to suitably command not only a drain line and a control gate but also one of the two source lines on each side of the above drain line. This type of a more complicated decoder requires more intricate, and thus larger, circuitry, something which is clearly to be avoided.
The object of the present invention is to accomplish a matrix with a "table cloth" structure with buried junctions which, in addition to improving the capacitative ratio, will also allow the use of a traditional-type decoder, with a consequent shorter access time, less circuit complexity and higher cell density.
According to the invention such object is attained with a table cloth matrix of EPROM memory cells, comprising source lines and drain lines parallel and alternated with one another, inserted in buried layers of a substrate under strips of field oxide, floating gate areas connecting said source lines and drain lines with lateral fins superimposed over said strips of field oxide, and control gate lines parallel to one another and perpendicular to said source lines and drain lines in a condition superimposed over said floating gate areas, so as to define a plurality of rows of memory cells parallel to one another, characterized in that each source line is alternated with a pair of drain lines separated by an insulation area obtained in the substrate, so that each drain line is associated with one and only one of said rows of cells.
It appears evident that, since each drain line is assigned to a single row of cells, and not to two rows as in the traditional technique, it is possible to access one individual cell with a traditional, faster and simpler decoder, and thus with a lower utilization of space. In addition, the presence of field oxide superimposed over the source and drain lines, together with the extensive contact surface between floating gate and control gate, allows an excellent capacitative coupling.
The characteristics and the advantages of the present invention shall be made more evident by the following detailed description of one of its preferred embodiments, illustrated as a non-limiting example in the following drawings, wherein:
FIG. 1 is a perspective cross-section of a portion of a matrix of EPROM memory cells according to the invention;
FIG. 2 is a plan view from above of a part of said matrix of memory cells;
FIGS. 3, 4, 5, 6 and 7 show enlarged details of said matrix in cross-section taken along the lines III--III, IV--IV, V--V-VI--VI and VII--VII of FIG. 2.
The matrix shown in the drawings, of the so-called "table cloth" type, comprises a silicon substrate 1, wherein there are obtained in buried layers parallel source lines 2, alternated with pairs of parallel drain lines 3. The two drain lines 3 are separated by insulation strips 4, while insulation strips 6 are provided at the sides of the drain lines 2.
Above each source line 2 there is grown a thick strip of field oxide 5; similarly, on each pair of adjacent drain lines 3 there is grown a thick strip of field oxide 7, more extensive than the strips of field oxide 5 (FIG. 1).
Said strips of field oxide 5 and 7 are alternated with said insulation strips 4 and 6.
Between each source line 2 and drain line 3 (constituting the so-called "bit-lines") there are defined gate oxide areas 8, partially superimposed over said field oxide strips 5 and 7 by means of asymmetrical fins 10 and 11 (FIG. 3), the larger fin 10 being superimposed over the corresponding oxide strip 7, the smaller fin 11 being superimposed over oxide strip 5.
The oxide areas 8 are each coated by a floating gate area 9, say of polysilicon, with asymmetrical fins 12 and 13 (FIG. 3) superimposed over fins 10 and 11, respectively, of the underlying gate oxide areas 8.
Above each group formed by the superimposed areas of gate oxide 8 and floating gate 9 there is deposited a layer of dielectric oxide 14.
Lastly over each "sandwich" formed by oxide area 8, floating gate 9, dielectric 9 there are deposited, aligned with this "sandwich", control gate lines 15 (the so-called "word lines"), perpendicular to source lines 2 and drain lines 3.
The matrix is thus constituted by a plurality of EPROM memory cells arranged in a table cloth pattern, each of which is conformed like the one indicated with 16 (FIGS. 2 and 3), that is, it has a floating gate area 9 interposed between a source line 2 and drain line 3, and a control gate line 15 perpendicular to the source lines 2 and the drain lines 3, the floating gate 9 having two asymmetrical lateral fins 12 and 13 partially superimposed over the underlying oxide strips 5 and 7 and being interposed between a gate oxide area 8 and a layer of dielectric 14.
The oxide strips 5 and 7 have the task of increasing the distance between drain lines 3 and source lines 4 and the floating gate areas 9. In combination with the large contact surface between floating gate areas 9 and the oxide 5 and 7, obtained thanks to fins 12 and 13, this allows the attainment of an excellent capacitative coupling.
At the same time, since source lines 2 are alternated with two distinct drain lines 3 insulated from each other, each drain line 3 is common to only one row of cells 16, each of which is thus accessible through a traditional decoder, which is simpler and occupies a more limited space.

Claims (2)

I claim:
1. A matrix of EPROM memory cells, comprising a semiconductor substrate, a plurality of first and second parallel strips of field oxide formed on the substrate, parallel source lines arranged in buried layers of the substrate under said first strips of field oxide, pairs of parallel drain lines arranged in buried layers of the substrate under each of said second strips of field oxide, floating gases interposed between said source lines and said drain lines and provided with lateral extensions superimposed over lateral portions of said first and second strips of field oxide, and control gate lines parallel to one another and perpendicular to said source and drain lines and superimposed on and aligned with said floating gate areas.
2. A matrix according to claim 1, wherein said first strips of field oxide are narrower than said second strips of field oxide.
US07/488,148 1989-03-15 1990-03-05 Table cloth matrix of EPROM memory cells with buried junctions, individually accessible by a traditional decoder Expired - Lifetime US5028979A (en)

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IT19777A/89 1989-03-15
IT8919777A IT1228720B (en) 1989-03-15 1989-03-15 TABLECLOTH DIE OF MEMORY CELLS EPROM WITH BURIED JOINTS, ACCESSIBLE INDIVIDUALLY THROUGH TRADITIONAL DECODING.

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing
US5289026A (en) * 1991-08-14 1994-02-22 Intel Corporation Asymmetric floating gate overlap for improved device characteristics in buried bit-line devices
US5399891A (en) * 1992-01-22 1995-03-21 Macronix International Co., Ltd. Floating gate or flash EPROM transistor array having contactless source and drain diffusions
US5466624A (en) * 1994-09-30 1995-11-14 Intel Corporation Isolation between diffusion lines in a memory array
US5526307A (en) * 1992-01-22 1996-06-11 Macronix International Co., Ltd. Flash EPROM integrated circuit architecture
US5592000A (en) * 1993-12-14 1997-01-07 Macronix International Co., Ltd. Non-volatile semiconductor memory device programmable and erasable at low voltage
US5618742A (en) * 1992-01-22 1997-04-08 Macronix Internatioal, Ltd. Method of making flash EPROM with conductive sidewall spacer contacting floating gate
US5751637A (en) * 1995-06-07 1998-05-12 Macronix International Co., Ltd. Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width
US20070166903A1 (en) * 2006-01-17 2007-07-19 Bohumil Lojek Semiconductor structures formed by stepperless manufacturing
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits

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JPH088316B2 (en) * 1990-01-31 1996-01-29 株式会社東芝 Ultraviolet erasable nonvolatile semiconductor memory device
US6580120B2 (en) * 2001-06-07 2003-06-17 Interuniversitair Microelektronica Centrum (Imec Vzw) Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure

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US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling

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US4342099A (en) * 1979-06-18 1982-07-27 Texas Instruments Incorporated Electrically erasable programmable MNOS read only memory
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JPS5728364A (en) * 1980-07-28 1982-02-16 Fujitsu Ltd Semiconductor memory device
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US4750024A (en) * 1986-02-18 1988-06-07 Texas Instruments Incorporated Offset floating gate EPROM memory cell
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
JPS63281469A (en) * 1987-05-13 1988-11-17 Seiko Instr & Electronics Ltd Semiconductor device and manufactrue thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing
US6124168A (en) * 1991-08-14 2000-09-26 Intel Corporation Method for forming an asymmetric floating gate overlap for improved device performance in buried bit-line devices
US5289026A (en) * 1991-08-14 1994-02-22 Intel Corporation Asymmetric floating gate overlap for improved device characteristics in buried bit-line devices
US5399891A (en) * 1992-01-22 1995-03-21 Macronix International Co., Ltd. Floating gate or flash EPROM transistor array having contactless source and drain diffusions
US5526307A (en) * 1992-01-22 1996-06-11 Macronix International Co., Ltd. Flash EPROM integrated circuit architecture
US5618742A (en) * 1992-01-22 1997-04-08 Macronix Internatioal, Ltd. Method of making flash EPROM with conductive sidewall spacer contacting floating gate
US5633185A (en) * 1992-01-22 1997-05-27 Macronix International Co., Ltd. Method of making a non-volatile memory cell
US5691938A (en) * 1992-01-22 1997-11-25 Macronix International Co., Ltd. Non-volatile memory cell and array architecture
US5592000A (en) * 1993-12-14 1997-01-07 Macronix International Co., Ltd. Non-volatile semiconductor memory device programmable and erasable at low voltage
US5466624A (en) * 1994-09-30 1995-11-14 Intel Corporation Isolation between diffusion lines in a memory array
US5751637A (en) * 1995-06-07 1998-05-12 Macronix International Co., Ltd. Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width
US20070166903A1 (en) * 2006-01-17 2007-07-19 Bohumil Lojek Semiconductor structures formed by stepperless manufacturing
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits

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Publication number Publication date
IT1228720B (en) 1991-07-03
JP2678674B2 (en) 1997-11-17
EP0387936A1 (en) 1990-09-19
JPH02291168A (en) 1990-11-30
IT8919777A0 (en) 1989-03-15

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