US5144174A - Programmable delay circuit having a buffer stage connected in cascode between the outputs of a plurality of differential amplifiers and the output terminal - Google Patents

Programmable delay circuit having a buffer stage connected in cascode between the outputs of a plurality of differential amplifiers and the output terminal Download PDF

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US5144174A
US5144174A US07/697,670 US69767091A US5144174A US 5144174 A US5144174 A US 5144174A US 69767091 A US69767091 A US 69767091A US 5144174 A US5144174 A US 5144174A
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delay circuit
differential amplifiers
differential amplifier
output terminal
programmable delay
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US07/697,670
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Daisuke Murakami
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6257—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means
    • H03K17/6264—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors with several inputs only combined with selecting means using current steering means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00182—Layout of the delay element using bipolar transistors using constant current sources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00228—Layout of the delay element having complementary input and output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Definitions

  • the present invention generally relates to a programmable delay circuit and, more particularly, is directed to a programmable delay circuit in which linearity of delay characteristic is improved and power consumption is reduced and which is suitably applied to an IC (integrated circuit) tester or the like.
  • a Digitally Programmable Delay Chip with picosecond Resolution in IEEE Proceedings of the 1989 Bipolar Circuit and Technology Meetings Sep. 18-19, 1989, pp. 295 to 297 describes a conventional programmable delay circuit.
  • FIG. 1 shows an example of such a conventional programmable delay circuit.
  • a main or coarse delay circuit 1 is composed of 32 delay gates G 0 to G 31 connected in cascade, a multiplexer 1a and a latch circuit 1b.
  • the latch circuit 1b latches a digital signal of 5 bits (D 0 to D 4 ) input thereto from a control circuit (not shown) and the multiplexer 1a is controlled in response to the digital output of the latch circuit 1b, thereby pulse signals applied to input terminals IN and INB being delayed by an arbitrary delay time of 110 picoseconds per gate.
  • a cascade circuit 2 is connected to an output of the multiplexer 1a to expand the delay time and composed of a multiplexer 2a and a latch circuit 2b which latches a digital signal D 5 .
  • An output of the cascade circuit 2 is supplied through a buffer stage 3 to output terminals Q1 and Q1B, respectively, and a sub or fine tune circuitry 4 is connected to the output of the cascade circuit 2.
  • FIG. 2 is a schematic block diagram showing an example of a conventional multiplexer, and as shown in FIG. 2, the multiplexer 1a of FIG. 1 is generally comprised of 8 stages of delay gates G 1 to G 8 and seven multiplexers A through G which are supplied with control signals S 0 to S 6 delivered from the latch circuit 1b.
  • the multiplexer 1a is composed of seven multiplexers A through G connected in a so-called tournament fashion, which needs 2 n -1 multiplexers if there are provided 2 n delay circuits. Further, since the signal is passed through n multiplexers from each of the delay gates to the output terminal Q 1 , the fixed delay time is increased. In that case, if n is increased, delay error caused by the multiplexer 1a from each of the delay gates to the output terminal Q 1 is increased, thus deteriorating linearity of delay characteristic more.
  • the pulse signals supplied to the input terminals IN and INB are passed through the n multiplexers (e.g., the multiplexers A, E and G), the power consumption is increased.
  • a programmable delay circuit is comprised of input terminals to which input signals to be delayed are supplied, N (N ⁇ 2) delay circuits of a plurality of stages connected in series, a plurality of differential amplifiers connected to respective stages of the plurality of stages of delay circuits and having a pair of differential amplifier transistors and a current switch for supplying a drive current from a common current source to the pair of differential amplifier transistors, a common output terminal commonly connected to respective output terminals of the pair of differential amplifier transistors of the plurality of differential amplifiers, and a control circuit for alternatively controlling the current switches of the plurality of differential amplifiers.
  • a buffer stage connected in cascode is provided between outputs of the plurality of differential amplifiers and the common output terminal.
  • the programmable delay circuit of the present invention even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced.
  • the output capacitances of the differential amplifier transistors can be apparently reduced and thus the programmable delay circuit of the present invention can be operated at high speed.
  • FIG. 1 is a block diagram showing an example of a conventional programmable delay circuit
  • FIG. 2 is a block diagram showing an example of a multiplexer used in the conventional programmable delay circuit of FIG. 1;
  • FIG. 3 is a block circuit diagram showing a fundamental arrangement of a programmable delay circuit of the present invention
  • FIG. 4 (formed of FIGS. 4A and 4B) is a circuit diagram showing an embodiment of the programmable delay circuit according to the present invention.
  • FIG. 5 illustrates how FIGS. 4A and 4B are assembled.
  • FIG. 3 shows in block circuit form a fundamental arrangement of the programmable delay circuit of the present invention.
  • input signals pulse signals such as clock signals or the like
  • the delay circuit 6 has N stages (N ⁇ 2) and composed of a plurality of delay circuits (G l through G n ) which are connected in cascade.
  • Input electrodes (bases) of a pair of differential amplifier transistors Q 11 and Q 12 are connected between the first and second delay circuits G 1 and G 2 of the delay circuit 6.
  • Output electrodes (collectors) of the transistors Q 11 and Q 12 are connected through transistors Q b1 and Q b2 which constitute a buffer stage 7 and connected in cascode to common output terminals VOUT and VOUTB, respectively.
  • the transistors Q b1 and Q b2 are connected in cascode to the differential amplifier transistors.
  • load resistors R 1 and R 2 are connected between a reference voltage source V ref (by way of example, ground potential) and the common output terminals VOUT and VOUTB, respectively.
  • a current switch 8 is composed of transistors Q 1 to Q n-1 , and a common current source 9 has a current value of, for example, I ref .
  • the differential amplifier transistors Q 11 and Q 12 and the transistor Q 1 of the current switch 8 constitute a first differential amplifier D 1 ; differential amplifier transistors Q 21 and Q 22 connected between the second and third delay circuits G 2 and G 3 and a transistor Q 2 of the current switch 8 constitute a second differential amplifier D 2 ; and differential amplifier transistors Q n-11 and Q n-12 connected between the third delay circuit G 3 and an N'th delay circuit G n and a transistor Q n-1 of the current switch 8 constitute a (N-1)th differential amplifier D n-1 .
  • reference numeral 10 designates a control circuit which selectively controls the current switch 8.
  • the control circuit 10 controls the transistors Q 1 to Q n-1 of the current switch 8 in response to, for example, digital signals d 1 to d k of K bits.
  • the transistor Q 1 of the current switch 8 when, for example, the transistor Q 1 of the current switch 8 is selected by the digital signals d l to d k of the control circuit 10, the transistor Q: is turned on to permit the current I ref of the common current source 9 to be supplied to the differential amplifier transistors Q 11 and Q 12 of the first differential amplifier D 1 so that the input signals applied to the input terminals 5a and 5b are supplied to the first delay circuit G 1 .
  • An output of the first delay circuit G 1 is amplified by the first differential amplifier D 1 and supplied through the buffer stage 7 to the common output terminals VOUT and VOUTB.
  • the transistor Q 2 of the current switch 8 when the transistor Q 2 of the current switch 8 is selected, the transistor Q 2 is turned on to permit the current I ref of the common current source 9 to be supplied to the differential amplifier transistors Q 21 and Q 22 of the second differential amplifier D 2 so that the input signals applied to the input terminals 5a and 5b are supplied to the second delay circuit G 2 .
  • An output of the second delay circuit G 2 is amplified by the second differential amplifier D 2 and supplied through the buffer stage 7 to the common output terminals VOUT and VOUTB. That is, the current switch 8 of the plurality of differential amplifiers D 1 to D n-1 is controlled by the control signals C 1 to C n-1 of the control circuit 10, whereby the outputs of the (N-1)th delay circuits G 1 to G n-l can be selectively output.
  • the delay times of the differential amplifiers D l to D n-l are constant and the fixed delay times are reduced so that linearity of delay characteristic can be improved. Also, since the single common current source 9 is used, the power consumption can be reduced.
  • the delay time can be further increased by providing other differential amplifiers (not shown) in the output of th Nth delay circuit G n .
  • FIG. 5 is formed of FIGS. 4A and 4B drawn on two sheets of drawings so as to permit the use of a suitably large scale.
  • the delay circuit 6 of FIG. 3 is composed of eight stages of first delay circuit G 1 to eighth delay circuit G 8 and each of the first to eighth delay circuits G 1 to G 8 is formed of an emitter-follower Circuit and a differential amplifier.
  • the transistors Q 1 to Q 8 constructing the current switch 8 of the first to eighth differential amplifiers D 1 to D 8 are controlled by control signals C 1 to C 8 from a control circuit (not shown).
  • the programmable delay circuit of the present invention even when any one of the current switches of the plurality of differential amplifiers is selected, the delay amounts of the differential amplifiers become constant so that the linearity of the delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced.
  • the cascode-connected buffer stage When the cascode-connected buffer stage is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced so that the programmable delay circuit of the present invention can be operated at higher speed.
  • the programmable delay circuit of the present invention even when the number of stages of the delay circuit is increased, delay errors of the multiplexer can be prevented from being accumulated unlike the example of the prior art, thus making it possible to obtain satisfactory delay characteristic.

Abstract

A programmable delay circuit of the present invention is comprised of an input terminal to which an input signal to be delayed is supplied, N (N≧2) delay circuits of a plurality of stages connected in cascade, a plurality of differential amplifier transistors connected to respective stages between the delay circuits of the plurality of stages and having a pair of differential amplifier transistors and current switches for supplying a drive current from a common current source to the pair of differential amplifier transistors, a common output terminal commonly connected to respective outputs of a pair of differential amplifier transistors of the plurality of differential amplifiers and a control circuit for selectively controlling the current switches of the plurality of differential amplifiers, wherein even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced. When a buffer stage connected in cascode is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced and thus the programmable delay circuit of the present invention can be operated at high speed.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a programmable delay circuit and, more particularly, is directed to a programmable delay circuit in which linearity of delay characteristic is improved and power consumption is reduced and which is suitably applied to an IC (integrated circuit) tester or the like.
2. Description of the Prior Art
A Digitally Programmable Delay Chip with picosecond Resolution in IEEE Proceedings of the 1989 Bipolar Circuit and Technology Meetings Sep. 18-19, 1989, pp. 295 to 297 describes a conventional programmable delay circuit.
A block diagram forming FIG. 1 shows an example of such a conventional programmable delay circuit.
As shown in FIG. 1, a main or coarse delay circuit 1 is composed of 32 delay gates G0 to G31 connected in cascade, a multiplexer 1a and a latch circuit 1b. The latch circuit 1b latches a digital signal of 5 bits (D0 to D4) input thereto from a control circuit (not shown) and the multiplexer 1a is controlled in response to the digital output of the latch circuit 1b, thereby pulse signals applied to input terminals IN and INB being delayed by an arbitrary delay time of 110 picoseconds per gate. A cascade circuit 2 is connected to an output of the multiplexer 1a to expand the delay time and composed of a multiplexer 2a and a latch circuit 2b which latches a digital signal D5. An output of the cascade circuit 2 is supplied through a buffer stage 3 to output terminals Q1 and Q1B, respectively, and a sub or fine tune circuitry 4 is connected to the output of the cascade circuit 2.
FIG. 2 is a schematic block diagram showing an example of a conventional multiplexer, and as shown in FIG. 2, the multiplexer 1a of FIG. 1 is generally comprised of 8 stages of delay gates G1 to G8 and seven multiplexers A through G which are supplied with control signals S0 to S6 delivered from the latch circuit 1b.
However, in the conventional delay circuit of FIG. 2, the multiplexer 1a is composed of seven multiplexers A through G connected in a so-called tournament fashion, which needs 2n -1 multiplexers if there are provided 2n delay circuits. Further, since the signal is passed through n multiplexers from each of the delay gates to the output terminal Q1, the fixed delay time is increased. In that case, if n is increased, delay error caused by the multiplexer 1a from each of the delay gates to the output terminal Q1 is increased, thus deteriorating linearity of delay characteristic more.
Furthermore, since the pulse signals supplied to the input terminals IN and INB are passed through the n multiplexers (e.g., the multiplexers A, E and G), the power consumption is increased.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved programmable delay circuit in which the aforenoted shortcomings and disadvantages encountered with the prior art can be eliminated.
More specifically, it is an object of the present invention to provide a programmable delay circuit in which linearity of delay characteristic can be improved.
It is another object of the present invention to provide a programmable delay circuit in which power consumption can be reduced.
It is still another object of the present invention to provide a programmable delay circuit which can be operated at high speed.
It is a further object of the present invention to provide a programmable delay circuit which can produce satisfactory delay characteristic.
According to a first aspect of the present invention, a programmable delay circuit is comprised of input terminals to which input signals to be delayed are supplied, N (N≧2) delay circuits of a plurality of stages connected in series, a plurality of differential amplifiers connected to respective stages of the plurality of stages of delay circuits and having a pair of differential amplifier transistors and a current switch for supplying a drive current from a common current source to the pair of differential amplifier transistors, a common output terminal commonly connected to respective output terminals of the pair of differential amplifier transistors of the plurality of differential amplifiers, and a control circuit for alternatively controlling the current switches of the plurality of differential amplifiers.
In accordance with a second aspect of the present invention, in a programmable delay circuit, a buffer stage connected in cascode is provided between outputs of the plurality of differential amplifiers and the common output terminal.
According to the programmable delay circuit of the present invention, even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced.
Further, when the buffer stages connected in cascode are provided between the outputs of said plurality of differential amplifiers and said common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced and thus the programmable delay circuit of the present invention can be operated at high speed.
The above, and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof to be taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an example of a conventional programmable delay circuit;
FIG. 2 is a block diagram showing an example of a multiplexer used in the conventional programmable delay circuit of FIG. 1;
FIG. 3 is a block circuit diagram showing a fundamental arrangement of a programmable delay circuit of the present invention;
FIG. 4 (formed of FIGS. 4A and 4B) is a circuit diagram showing an embodiment of the programmable delay circuit according to the present invention; and
FIG. 5 illustrates how FIGS. 4A and 4B are assembled.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention will now be described with reference to the drawings.
FIG. 3 shows in block circuit form a fundamental arrangement of the programmable delay circuit of the present invention. Referring to FIG. 3, input signals (pulse signals such as clock signals or the like) to be delayed are supplied to input terminals 5a and 5b of a delay circuit 6 and, by way of example, these input signals are opposite in phase. The delay circuit 6 has N stages (N≧2) and composed of a plurality of delay circuits (Gl through Gn) which are connected in cascade. Input electrodes (bases) of a pair of differential amplifier transistors Q11 and Q12 are connected between the first and second delay circuits G1 and G2 of the delay circuit 6. Output electrodes (collectors) of the transistors Q11 and Q12 are connected through transistors Qb1 and Qb2 which constitute a buffer stage 7 and connected in cascode to common output terminals VOUT and VOUTB, respectively. As shown in FIG. 3, the transistors Qb1 and Qb2 are connected in cascode to the differential amplifier transistors. Incidentally, load resistors R1 and R2 are connected between a reference voltage source Vref (by way of example, ground potential) and the common output terminals VOUT and VOUTB, respectively. A current switch 8 is composed of transistors Q1 to Qn-1, and a common current source 9 has a current value of, for example, Iref. The differential amplifier transistors Q11 and Q12 and the transistor Q1 of the current switch 8 constitute a first differential amplifier D1 ; differential amplifier transistors Q21 and Q22 connected between the second and third delay circuits G2 and G3 and a transistor Q2 of the current switch 8 constitute a second differential amplifier D2 ; and differential amplifier transistors Qn-11 and Qn-12 connected between the third delay circuit G3 and an N'th delay circuit Gn and a transistor Qn-1 of the current switch 8 constitute a (N-1)th differential amplifier Dn-1. In FIG. 3, reference numeral 10 designates a control circuit which selectively controls the current switch 8. For example, the control circuit 10 controls the transistors Q1 to Qn-1 of the current switch 8 in response to, for example, digital signals d1 to dk of K bits.
Operation of the thus constructed programmable delay circuit will be described below.
Referring to FIG. 3, when, for example, the transistor Q1 of the current switch 8 is selected by the digital signals dl to dk of the control circuit 10, the transistor Q: is turned on to permit the current Iref of the common current source 9 to be supplied to the differential amplifier transistors Q11 and Q12 of the first differential amplifier D1 so that the input signals applied to the input terminals 5a and 5b are supplied to the first delay circuit G1. An output of the first delay circuit G1 is amplified by the first differential amplifier D1 and supplied through the buffer stage 7 to the common output terminals VOUT and VOUTB. Similarly, when the transistor Q2 of the current switch 8 is selected, the transistor Q2 is turned on to permit the current Iref of the common current source 9 to be supplied to the differential amplifier transistors Q21 and Q22 of the second differential amplifier D2 so that the input signals applied to the input terminals 5a and 5b are supplied to the second delay circuit G2. An output of the second delay circuit G2 is amplified by the second differential amplifier D2 and supplied through the buffer stage 7 to the common output terminals VOUT and VOUTB. That is, the current switch 8 of the plurality of differential amplifiers D1 to Dn-1 is controlled by the control signals C1 to Cn-1 of the control circuit 10, whereby the outputs of the (N-1)th delay circuits G1 to Gn-l can be selectively output. Even when any of the transistors Q to Qn-l of the current switch 8 of the plurality of differential amplifiers Dl to Dn-l is selected, the delay times of the differential amplifiers Dl to Dn-l are constant and the fixed delay times are reduced so that linearity of delay characteristic can be improved. Also, since the single common current source 9 is used, the power consumption can be reduced.
Further, when the cascode-connected buffer stage 7 is connected between the outputs of the plurality of differential amplifiers D1 to Dn-1 and the common output terminals VOUT and VOUTB, the output capacitances of the differential amplifier transistors Q11 to Qn-12 are apparently reduced, thereby the programmable delay circuit of the invention being operated at high speed. Incidentally, the delay time can be further increased by providing other differential amplifiers (not shown) in the output of th Nth delay circuit Gn.
Alternatively, though not shown, it is possible to provide a differential amplifier which supplies the input signals applied to the input terminals 5a and 5b directly to the common output terminals VOUT and VOUTB (the first delay circuit G1 is bypassed).
A specific circuit arrangement of the embodiment of the programmable delay circuit according to the present invention will be described with reference to FIG. 5. FIG. 5 is formed of FIGS. 4A and 4B drawn on two sheets of drawings so as to permit the use of a suitably large scale.
In FIG. 5, like parts corresponding to those of FIG. 3 are marked with the same references and therefore need not be described in detail.
As shown in FIG. 5, the delay circuit 6 of FIG. 3 is composed of eight stages of first delay circuit G1 to eighth delay circuit G8 and each of the first to eighth delay circuits G1 to G8 is formed of an emitter-follower Circuit and a differential amplifier. The transistors Q1 to Q8 constructing the current switch 8 of the first to eighth differential amplifiers D1 to D8 are controlled by control signals C1 to C8 from a control circuit (not shown). In the embodiment of FIG. 5, if the delay time of each delay circuit is selected to be, for example, 100 psec, the delay time can be varied in a range of from 100 psec to 800 psec (e.g., 10 nsec in the case of 2n =128), thus achieving similar effects to those of FIG. 3.
Further, in this embodiment, since the input pulse signal is transmitted in a push-pull fashion, there is then the advantage that the duty ratio of the input pulse signal can be maintained constant until it is output.
As will be clear from the above explanation, according to the programmable delay circuit of the present invention, even when any one of the current switches of the plurality of differential amplifiers is selected, the delay amounts of the differential amplifiers become constant so that the linearity of the delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced.
When the cascode-connected buffer stage is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced so that the programmable delay circuit of the present invention can be operated at higher speed.
Furthermore, according to the programmable delay circuit of the present invention, even when the number of stages of the delay circuit is increased, delay errors of the multiplexer can be prevented from being accumulated unlike the example of the prior art, thus making it possible to obtain satisfactory delay characteristic.
Having described the preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications thereof could be effected by one skilled in the art without departing from the spirit or scope of the novel concepts of the invention as defined in the appended claims.

Claims (5)

I claim as my invention:
1. A programmable delay circuit comprising:
(a) an input terminal to which an input signal to be delayed is supplied;
(b) N (N≧2) delay circuits of a plurality of stages connected in cascade;
(c) a plurality of differential amplifiers respectively connected to respective stages between said plurality of stages of delay circuits and having a pair of differential amplifier transistors and current switches for supplying a drive current from a common current source to said pair of differential amplifier transistors;
(d) an output terminal commonly coupled to respective output terminals of said pair of differential amplifier transistors of said plurality of differential amplifiers;
(e) a buffer stage connected in cascode between said respective output terminals of aid plurality of differential amplifiers and said common output terminal; and
(f) a digital control circuit for selecting only one of said current switches of said plurality of differential amplifiers.
2. A programmable delay circuit according to claim 1, wherein a buffer stage connected in cascode is provided between outputs of said plurality of differential amplifiers and said output terminal.
3. A programmable delay circuit according to claim 2, wherein the input signal to be delayed is directly supplied to said output terminal.
4. A programmable delay circuit according to claim 3, wherein an emitter-follower stage is connected between the input terminal to which the input signal to be delayed is supplied and the delay circuit of the first stage.
5. A programmable delay circuit according to claim 4, wherein a push-pull signal is supplied to said input terminal to which the input signal to be delayed is supplied and a push-pull signal delayed by a predetermined delay time is developed at said output terminal.
US07/697,670 1990-05-11 1991-05-09 Programmable delay circuit having a buffer stage connected in cascode between the outputs of a plurality of differential amplifiers and the output terminal Expired - Lifetime US5144174A (en)

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JP02119792A JP3077813B2 (en) 1990-05-11 1990-05-11 Programmable delay circuit
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US5327021A (en) * 1991-06-10 1994-07-05 Shinko Electric Ind., Co., Ltd. Waveform synthesizing circuit
US5347175A (en) * 1992-05-12 1994-09-13 The United States Of America As Represented By The Secretary Of Commerce Voltage comparator with reduced settling time
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US5376833A (en) * 1992-12-11 1994-12-27 Texas Instruments Incorporated Current driver circuit
US5394022A (en) * 1992-01-08 1995-02-28 Sony Corporation Pulse width modulation circuit apparatus
US5479091A (en) * 1992-12-11 1995-12-26 Texas Instruments Incorporated Output current reference circuit and method
US5497263A (en) * 1992-09-10 1996-03-05 Hitachi, Ltd. Variable delay circuit and clock signal supply unit using the same
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US6054889A (en) * 1997-11-11 2000-04-25 Trw Inc. Mixer with improved linear range
US7167523B2 (en) 1997-11-17 2007-01-23 Silicon Graphics, Inc. Spacial derivative bus encoder and decoder
US6775339B1 (en) 1999-08-27 2004-08-10 Silicon Graphics, Inc. Circuit design for high-speed digital communication
US20090034673A1 (en) * 1999-12-30 2009-02-05 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US6803872B2 (en) 1999-12-30 2004-10-12 Silicon Graphics, Inc. Programmable differential delay circuit with fine delay adjustment
US7433441B2 (en) 1999-12-30 2008-10-07 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US8031823B2 (en) 1999-12-30 2011-10-04 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US7031420B1 (en) 1999-12-30 2006-04-18 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US6417713B1 (en) * 1999-12-30 2002-07-09 Silicon Graphics, Inc. Programmable differential delay circuit with fine delay adjustment
US6696897B1 (en) * 2002-08-14 2004-02-24 Applied Microcircuits Corp. System and method for voltage controlled oscillator phase interpolation
US20040056698A1 (en) * 2002-09-25 2004-03-25 Ken Elliott Time delay apparatus and method of using same
US7446584B2 (en) * 2002-09-25 2008-11-04 Hrl Laboratories, Llc Time delay apparatus and method of using same
US20050077941A1 (en) * 2003-10-10 2005-04-14 Fagan John L. Selectable delay pulse generator
US20090284296A1 (en) * 2003-10-10 2009-11-19 Atmel Corporation Selectable delay pulse generator
US8193846B2 (en) 2003-10-10 2012-06-05 Atmel Corporation Selectable delay pulse generator
WO2005036747A3 (en) * 2003-10-10 2006-02-23 Atmel Corp Selectable delay pulse generator
WO2005036747A2 (en) * 2003-10-10 2005-04-21 Atmel Corporation Selectable delay pulse generator
US20060061399A1 (en) * 2004-09-22 2006-03-23 Jianping Xu Programmable high-resolution timing jitter injectors
US7348821B2 (en) * 2004-09-22 2008-03-25 Intel Corporation Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors
US8054876B2 (en) 2005-12-13 2011-11-08 Infinera Corporation Active delay line
US20070133671A1 (en) * 2005-12-13 2007-06-14 Infinera Corporation Active delay line
US7795940B2 (en) 2007-08-03 2010-09-14 International Business Machines Corporation Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures
US7932552B2 (en) 2007-08-03 2011-04-26 International Business Machines Corporation Multiple source-single drain field effect semiconductor device and circuit
US20090033389A1 (en) * 2007-08-03 2009-02-05 Abadeer Wagdi W Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures
US20090033395A1 (en) * 2007-08-03 2009-02-05 Abadeer Wagdi W Multiple source-single drain field effect semiconductor device and circuit
US20090106707A1 (en) * 2007-10-17 2009-04-23 Abadeer Wagdi W Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit
US7814449B2 (en) 2007-10-17 2010-10-12 International Business Machines Corporation Design structure for multiple source-single drain field effect semiconductor device and circuit
US20110273431A1 (en) * 2010-02-23 2011-11-10 Rohm Co., Ltd. Multiplexer for differential signal
US8773421B2 (en) * 2010-02-23 2014-07-08 Rohm Co., Ltd. Multiplexer for differential signal

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EP0456231A1 (en) 1991-11-13
DE69124002D1 (en) 1997-02-20
JP3077813B2 (en) 2000-08-21
DE69124002T2 (en) 1997-07-31
JPH0417410A (en) 1992-01-22
EP0456231B1 (en) 1997-01-08
KR0153245B1 (en) 1998-12-15
KR910021020A (en) 1991-12-20

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