US5270968A - Thin-film transistor for semiconductor memory device and fabricating method thereof - Google Patents

Thin-film transistor for semiconductor memory device and fabricating method thereof Download PDF

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US5270968A
US5270968A US07/906,369 US90636992A US5270968A US 5270968 A US5270968 A US 5270968A US 90636992 A US90636992 A US 90636992A US 5270968 A US5270968 A US 5270968A
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Jhang-rae Kim
Han-soo Kim
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Samsung Electronics Co Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

Definitions

  • the present invention relates to a thin-film-transistor (TFT) for a semiconductor memory device and the fabricating method thereof, and more particularly to a PMOS TFT transistor of an SRAM with a 6-transistor memory cell configuration and the fabricating method thereof.
  • TFT thin-film-transistor
  • SRAMs static random access memories
  • DRAM dynamic random access devices
  • SRAMs are divided into 4-transistor and 6-transistor cell configurations.
  • the 4-transistor type leads with respect to capacity, employing a memory cell of NMOS form having a polysilicon as a high resistance load and periphery circuits of CMOS form. Due to chip size, 256 Kb SRAMs are produced primarily, disregarding low power consumption SRAMs having full CMOS configuration. Therefore, recently, a stack-type TFT changing the high resistance polysilicon load into one for PMOS, is adopted to reduce the power consumption and maintain a chip size similar to that of the conventional 4-transistor type ("Symposium on VLSI Technology," 1990, pp. 19-24).
  • source, drain and channel regions of a conventional TFT are arranged in a two-dimensional plane structure to occupy large areas. Accordingly, the TFT in a two-dimensional structure impedes the high density and large capacity of an SRAM.
  • the object of the present invention is to provide a three-dimensional TFT for a semiconductor memory device.
  • Another object of the present invention is to provide the most suitable method for fabricating the aforementioned TFT.
  • a TFT comprising:
  • a first conductive layer formed on a first insulating layer and doped with first conductive type impurities
  • the TFT according to the present invention is manufactured by the steps of:
  • FIG. 1A is a plane layout of a conventional TFT for a semiconductor memory device
  • FIG. 1B is a cross-sectional view of a TFT taken along line I--I shown in FIG. 1A;
  • FIG. 2A is a plane layout of a TFT for a semiconductor memory device according to the present invention.
  • FIG. 2B is a cross-sectional view of a TFT taken along line II--II shown in FIG. 2A;
  • FIGS. 3A-3E show the fabricating process of a TFT for a semiconductor memory device according to the present invention.
  • a TFT for a conventional semiconductor memory device will be explained prior to the embodiment of the present invention.
  • a pattern of a first conductive layer 2 of a polysilicon provided as a drain contact pad of a PMOS TFT is formed on first insulating layer 1, and then a second insulating layer 3 is formed. After an opening, e.g., a via hole or a contact hole 4 is formed on second insulating layer 3, an amorphous silicon semiconductor layer 5 is deposited and then patterned. After a TFT gate insulating layer 6 is formed on semiconductor layer 5, a second conductive layer 7 of polysilicon is deposited on gate insulating layer 6 and then patterned. Thus, a gate electrode of a TFT is formed to overlap semiconductor layer 5 in a predetermined region on second insulating layer 3.
  • p-type impurities are ion-implanted or ion-injected into that portion of semiconductor layer 5 not overlapped by second conductive layer 7, to be self-aligned, thereby forming source and drain regions 5a and 5b of the PMOS TFT.
  • the semiconductor layer between source and drain regions 5a and 5b is provided as a channel region 5c of the PMOS TFT. That is, since the PMOS TFT provided as a load of a conventional SRAM is formed on a two-dimensional plane, a predetermined region should be allocated, which impedes the high density and large capacity of SRAM.
  • FIG. 2A is a plane layout of a three-dimensional TFT according to the present invention
  • FIG. 2B is a cross-sectional view taken along line II--II of FIG. 2A.
  • the difference between the present invention and the prior art is that a semiconductor layer formed on the inner wall of a drain contact hole of the PMOS TFT is employed as channel region 5c, and a semiconductor layer formed on the bottom of contact hole 4 is employed as source region 5a.
  • the pattern of second conductive layer 7 provided as a gate electrode is formed to cover the contact hole.
  • source region 5a is formed by the upward diffusion of p-type impurities, namely a first conductive impurity placed in first conductive layer 2 provided as a source contact pad.
  • the channel size of the PMOS TFT can be adjusted to the diameter or depth of the contact hole. Therefore, the area is reduced by about 40% as compared with the area occupied by the conventional PMOS TFT. Also, the degree of freedom in wiring is greatly improved.
  • the fabricating method of a preferred embodiment of the TFT according to the present invention comprises the steps shown in FIGS. 3A to 3E.
  • first conductive layer 2 for example, polysilicon or noncrystal silicon
  • first conductive layer 2 for example, polysilicon or noncrystal silicon
  • p-type impurities are ion-implanted or injected to the concentration of 1 ⁇ 10 13-5 ⁇ 10 15 /cm 2 , followed by forming the pattern of first conductive layer 2 by means of an ordinary photo-etching method.
  • a 2,000-10,000 ⁇ thick, second insulating layer 3 is formed on the pattern of first conductive layer 2. Successively, a contact hole 0.2-0.8 ⁇ m in diameter is formed in second insulating layer 3 above first conductive layer 2 by means of an ordinary photo-etching method, to expose first conductive layer 2.
  • a 100-1,000 ⁇ thick, semiconductor layer 5 made of an amorphous silicon is deposited on second insulating layer 3 wherein contact hole 4 is formed, and then the pattern of semiconductor layer 5 is formed by means of an ordinary photo-etching method.
  • a gate insulating layer 6 of the same thickness (100-1000 ⁇ ) serving as an oxide layer is coated on semiconductor layer 5, by chemical vapor method.
  • the p-type impurities are diffused upwardly from first conductive layer 2 into semiconductor layer 5, so that a p-type impurity region, namely, source region 5a, is formed in semiconductor layer 5 and in contact with first conductive layer 2.
  • a 500-2,000 ⁇ thick, second conductive layer 7 (for example, polysilicon or amorphous silicon) is deposited on gate insulating layer 6, and then n-type or p-type impurities are doped into second conductive layer 7 to the concentration of 1 ⁇ 10 14 -1 ⁇ 10 16 /cm 2 .
  • the pattern of second conductive layer 7 is formed by an ordinary photo-etching method, and is provided as a gate electrode.
  • p-type impurities are ion-implanted or injected to the concentration of 1 ⁇ 10 13 -5 ⁇ 10 15 /cm 2 in that portion of semiconductor layer 5 not overlapped by second conductive layer 7, thus forming a p-type impurity region, namely, drain region 5b.
  • a photoresist 8a is formed and then an opening 8b is formed therein. Then, via opening 8b, a p-type impurity region 5b' is formed in a predetermined region of semiconductor layer 5.
  • the PMOS TFT is completed by removing the photoresist (8 or 8a).
  • a channel region 5c of such a PMOS TFT is provided as a semiconductor layer formed on the inner walls of contact hole 4, and as a semiconductor layer where the p-type impurities are not implanted by the pattern of second conductive layer 7.
  • the semiconductor layer on the side walls of the contact hole is provided as a channel region to form a three-dimensional TFT, so that the area occupied by the TFT is reduced, to thereby enhance the density and capacity of a SRAM as well as the degree of freedom in wiring.

Abstract

Disclosed is a TFT for a semiconductor memory device and the fabricating method thereof, comprising a first conductive layer formed on a first insulating layer of a semiconductor substrate and doped with a first conductive type impurity, a second insulating layer formed on the first conductive layer, a contact hole formed in the second insulating layer above the first conductive layer, a semiconductor layer formed on a predetermined portion of the first conductive layer exposed in the contact hole, the inner walls of the contact hole and the second insulating layer, a thin-film gate insulating layer covering the semiconductor layer, a second conductive layer formed on a gate insulating layer to overlap the contact hole and its periphery, a first impurity region formed while upwardly dispersing the impurity of the first conductive layer into the semiconductor layer in contact with the first conductive layer of the contact hole, a second impurity region placed in the semiconductor layer of the second insulating layer, in which the first conductive impurity is doped, and a channel region limited between the first and second impurity regions and provided as a semiconductor layer of the inner side walls of the contact hole.

Description

BACKGROUND OF THE INVENTION
The present invention relates to a thin-film-transistor (TFT) for a semiconductor memory device and the fabricating method thereof, and more particularly to a PMOS TFT transistor of an SRAM with a 6-transistor memory cell configuration and the fabricating method thereof.
Recently, utilizing dynamic random access devices (DRAM) mass production lines, the makers of semiconductor memory devices have strived to increase the production of static random access memories (SRAMs) because of the increasing demand for SRAMs and the unstable price of DRAMs. The increase in the demand for SRAMs is because they have unique characteristics such as high speed, low power consumption, no refresh requirements and a simplified system design, and due to the trend toward multifunctional, high-quality, miniaturized and lightweight systems. However, since SRAMs have a more complicated cell structure than DRAMs, the density of the SRAMs is behind by one generation.
Current SRAMs are divided into 4-transistor and 6-transistor cell configurations. The 4-transistor type leads with respect to capacity, employing a memory cell of NMOS form having a polysilicon as a high resistance load and periphery circuits of CMOS form. Due to chip size, 256 Kb SRAMs are produced primarily, disregarding low power consumption SRAMs having full CMOS configuration. Therefore, recently, a stack-type TFT changing the high resistance polysilicon load into one for PMOS, is adopted to reduce the power consumption and maintain a chip size similar to that of the conventional 4-transistor type ("Symposium on VLSI Technology," 1990, pp. 19-24).
However, source, drain and channel regions of a conventional TFT are arranged in a two-dimensional plane structure to occupy large areas. Accordingly, the TFT in a two-dimensional structure impedes the high density and large capacity of an SRAM.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a three-dimensional TFT for a semiconductor memory device.
Another object of the present invention is to provide the most suitable method for fabricating the aforementioned TFT.
In order to achieve one object of the present invention, there is provided a TFT comprising:
a first conductive layer formed on a first insulating layer and doped with first conductive type impurities;
a second insulating layer covering the first conductive layer;
an opening formed in the second insulating layer on the first conductive layer;
a semiconductor layer formed on the surface of the first conductive layer exposed in the opening and on the surface of the predetermined portion of the second insulating layer;
a thin gate insulating layer covering the semiconductor layer;
a second conductive layer formed on the thin gate insulating layer in and around the opening;
a first impurity region formed in the first portion of the semiconductor layer in contact with the first conductive layer in the bottom of the opening and doped with the first conductive type impurities;
a second impurity region formed in the second portion of the semiconductor layer on the second insulating layer, and doped with the first conductive type impurities; and
a channel region defined between the first and second impurity regions in the semiconductor layer.
To achieve the other object, the TFT according to the present invention is manufactured by the steps of:
forming a first conductive layer doped with a first conductive type impurities on a first insulating layer;
covering the first conductive layer with a second insulating layer;
forming an opening in the second insulating layer of on the first conductive layer;
forming a semiconductor layer on the surface of the first conductive layer exposed in the opening and on the surface of the predetermined portion of the second insulating layer;
covering the semiconductor layer with a thin gate insulating layer and simultaneously forming a first impurity region in a first portion of the semiconductor layer in contact with the exposed first conductive layer by means of the upward diffusion of the impurities in the first conductive layer;
forming a second conductive layer on the thin gate insulating layer in and around the opening; and
forming a second impurity region in a second portion of the semiconductor layer which does not cover the second conductive layer on the second insulating layer by means of an impurity doping process.
BRIEF DESCRIPTION OF THE DRAWINGS
The above object and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment of the present invention with reference to the attached drawings in which:
FIG. 1A is a plane layout of a conventional TFT for a semiconductor memory device;
FIG. 1B is a cross-sectional view of a TFT taken along line I--I shown in FIG. 1A;
FIG. 2A is a plane layout of a TFT for a semiconductor memory device according to the present invention;
FIG. 2B is a cross-sectional view of a TFT taken along line II--II shown in FIG. 2A; and
FIGS. 3A-3E show the fabricating process of a TFT for a semiconductor memory device according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
A TFT for a conventional semiconductor memory device will be explained prior to the embodiment of the present invention.
Conventionally, referring to FIGS. 1A and 1B, a pattern of a first conductive layer 2 of a polysilicon provided as a drain contact pad of a PMOS TFT is formed on first insulating layer 1, and then a second insulating layer 3 is formed. After an opening, e.g., a via hole or a contact hole 4 is formed on second insulating layer 3, an amorphous silicon semiconductor layer 5 is deposited and then patterned. After a TFT gate insulating layer 6 is formed on semiconductor layer 5, a second conductive layer 7 of polysilicon is deposited on gate insulating layer 6 and then patterned. Thus, a gate electrode of a TFT is formed to overlap semiconductor layer 5 in a predetermined region on second insulating layer 3. Successively, p-type impurities are ion-implanted or ion-injected into that portion of semiconductor layer 5 not overlapped by second conductive layer 7, to be self-aligned, thereby forming source and drain regions 5a and 5b of the PMOS TFT. The semiconductor layer between source and drain regions 5a and 5b is provided as a channel region 5c of the PMOS TFT. That is, since the PMOS TFT provided as a load of a conventional SRAM is formed on a two-dimensional plane, a predetermined region should be allocated, which impedes the high density and large capacity of SRAM.
Therefore, in the present invention, there is provided a three-dimensional structure in order to reduce the area occupied by a PMOS TFT of a SRAM. FIG. 2A is a plane layout of a three-dimensional TFT according to the present invention, and FIG. 2B is a cross-sectional view taken along line II--II of FIG. 2A. The difference between the present invention and the prior art is that a semiconductor layer formed on the inner wall of a drain contact hole of the PMOS TFT is employed as channel region 5c, and a semiconductor layer formed on the bottom of contact hole 4 is employed as source region 5a. The pattern of second conductive layer 7 provided as a gate electrode is formed to cover the contact hole. Also, source region 5a is formed by the upward diffusion of p-type impurities, namely a first conductive impurity placed in first conductive layer 2 provided as a source contact pad. According to the above structure, the channel size of the PMOS TFT can be adjusted to the diameter or depth of the contact hole. Therefore, the area is reduced by about 40% as compared with the area occupied by the conventional PMOS TFT. Also, the degree of freedom in wiring is greatly improved.
The fabricating method of a preferred embodiment of the TFT according to the present invention comprises the steps shown in FIGS. 3A to 3E.
Referring to FIG. 3A, a 500-2,000 Å thick, first conductive layer 2 (for example, polysilicon or noncrystal silicon) is deposited on planarized first insulating layer 1 on a semiconductor substrate (not shown). Then, p-type impurities are ion-implanted or injected to the concentration of 1×1013-5×1015 /cm2, followed by forming the pattern of first conductive layer 2 by means of an ordinary photo-etching method.
Referring to FIG. 3B, a 2,000-10,000 Å thick, second insulating layer 3 is formed on the pattern of first conductive layer 2. Successively, a contact hole 0.2-0.8 μm in diameter is formed in second insulating layer 3 above first conductive layer 2 by means of an ordinary photo-etching method, to expose first conductive layer 2.
Referring to FIG. 3C, a 100-1,000 Å thick, semiconductor layer 5 made of an amorphous silicon is deposited on second insulating layer 3 wherein contact hole 4 is formed, and then the pattern of semiconductor layer 5 is formed by means of an ordinary photo-etching method. Successively, a gate insulating layer 6 of the same thickness (100-1000 Å) serving as an oxide layer is coated on semiconductor layer 5, by chemical vapor method. At this time, the p-type impurities are diffused upwardly from first conductive layer 2 into semiconductor layer 5, so that a p-type impurity region, namely, source region 5a, is formed in semiconductor layer 5 and in contact with first conductive layer 2.
Referring to FIG. 3D, a 500-2,000 Å thick, second conductive layer 7 (for example, polysilicon or amorphous silicon) is deposited on gate insulating layer 6, and then n-type or p-type impurities are doped into second conductive layer 7 to the concentration of 1×1014 -1×1016 /cm2. The pattern of second conductive layer 7 is formed by an ordinary photo-etching method, and is provided as a gate electrode. Successively, prior to removing a photoresist 8 for forming the pattern of second conductive layer 7, p-type impurities are ion-implanted or injected to the concentration of 1×1013 -5×1015 /cm2 in that portion of semiconductor layer 5 not overlapped by second conductive layer 7, thus forming a p-type impurity region, namely, drain region 5b. Otherwise, as illustrated in FIG. 3D-1, after photoresist 8 is removed, a photoresist 8a is formed and then an opening 8b is formed therein. Then, via opening 8b, a p-type impurity region 5b' is formed in a predetermined region of semiconductor layer 5.
Referring to FIG. 3E, the PMOS TFT is completed by removing the photoresist (8 or 8a). A channel region 5c of such a PMOS TFT is provided as a semiconductor layer formed on the inner walls of contact hole 4, and as a semiconductor layer where the p-type impurities are not implanted by the pattern of second conductive layer 7.
As above, in the SRAM of the present invention having an amorphous silicon PMOS TFT load, by overlapping the source contact region of the PMOS TFT and the second conductive layer provided as a gate electrode, the semiconductor layer on the side walls of the contact hole is provided as a channel region to form a three-dimensional TFT, so that the area occupied by the TFT is reduced, to thereby enhance the density and capacity of a SRAM as well as the degree of freedom in wiring.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (4)

What is claimed is:
1. A TFT for a semiconductor memory device comprising:
a first conductive layer formed on a first insulating layer and doped with first conductive type impurities;
a second insulating layer covering said first conductive layer;
an opening formed in said second insulating layer on said first conductive layer;
a semiconductor layer formed on the surface of said first conductive layer exposed in said opening and on the surface of the predetermined portion of said second insulating layer;
a thin gate insulating layer covering said semiconductor layer;
a second conductive layer formed on said thin gate insulating layer in and around said opening;
a first impurity region formed in the first portion of said semiconductor layer in contact with said first conductive layer in the bottom of said opening and doped with the first conductive type impurities;
a second impurity region formed in the second portion of said semiconductor layer on said second insulating layer, and doped with the first conductive type impurities; and
a channel region defined between said first and second impurity regions in said semiconductor layer.
2. A TFT for a semiconductor memory device as claimed in claim 1, wherein the size of said channel region is determined by the diameter or depth of said opening.
3. A TFT for a semiconductor memory device as claimed in claim 1, wherein said first conductive type impurities are p-type.
4. A TFT for a semiconductor memory device as claimed in claim 1, wherein the impurities of said first impurity region diffuse upwardly from said first conductive layer.
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US20050156243A1 (en) * 1995-07-24 2005-07-21 Monte Manning Thin film transistors and methods of forming thin film transistors
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US6235570B1 (en) * 1995-12-26 2001-05-22 L.G. Semicon Co., Ltd. Method for fabricating a semiconductor device
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US6172388B1 (en) * 1998-10-26 2001-01-09 United Semiconductor Corp. Method of fabricating dynamic random access memories
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WO2001091192A1 (en) * 2000-05-25 2001-11-29 Nanogate Ltd. A thin film field effect transistor
US20060043527A1 (en) * 2004-08-26 2006-03-02 Won-Kyu Kwak Capacitor
US8895984B2 (en) * 2004-08-26 2014-11-25 Samsung Display Co., Ltd. Capacitor
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CN1032286C (en) 1996-07-10
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IT1255398B (en) 1995-10-31
KR930015098A (en) 1993-07-23
JPH0773114B2 (en) 1995-08-02
KR950001159B1 (en) 1995-02-11
GB9213809D0 (en) 1992-08-12
TW212851B (en) 1993-09-11
ITMI921603A1 (en) 1993-12-30
FR2685818A1 (en) 1993-07-02
CN1073806A (en) 1993-06-30
DE4221420A1 (en) 1993-07-01
ITMI921603A0 (en) 1992-06-30

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