US5276834A - Spare memory arrangement - Google Patents
Spare memory arrangement Download PDFInfo
- Publication number
- US5276834A US5276834A US07/621,869 US62186990A US5276834A US 5276834 A US5276834 A US 5276834A US 62186990 A US62186990 A US 62186990A US 5276834 A US5276834 A US 5276834A
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- Prior art keywords
- memory
- chip
- spare
- cpu
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
Definitions
- This invention relates to semiconductor memories and, more particularly, to a spare memory arrangement that allows one or more outputs of a defective semiconductor memory chip to be electronically switched into a spare memory chip.
- prior art error correction systems have been directed to independent failures on a board.
- substitution of spare elements for defective elements incorporated in a memory involved the alteration of the circuit configuration on an individual chip. This was typically accomplished by the use of fusible links or destructive changes in individual cell characteristics by, for example, a laser beam directed at the chip.
- Other prior art error correction method involve redundant columns of cells which can be electronically substituted by suitable circuitry to columns containing defective cells.
- the present invention is directed to a mechanism for placing spare memory chips at any location in a memory array to replace defective memory chips.
- a memory of 256 MEGABYTES, for example will have about 2500 chips.
- a time between failures of 3/4 of a year for the total system can be assumed. If the offending memory chip is replaced by a spare memory chip, then the 3/4 of a year failure rate can be stretched to the service life of the system.
- a semiconduotor spare memory arrangement is provided.
- one or multiple outputs of a defective semiconductor chip can be electronically switched into a spare chip via a chip called a sparer chip.
- the sparer chip can be used in conjunction with an error correction (ECC) scheme or format, such as a parity or check sum.
- ECC error correction
- the invention broadly stated comprises a memory control system including:
- a detection system such as an (ECC) for detecting a defective chip in the memory array
- a sparer chip means for electronically enabling a spare memory chip to replace the defective memory chip and for establishing a map to and from the spare memory chip.
- the sparer chip includes a cross-point memory cell (CPM) located between bus data lines, memory data lines to the memory chips, and sparing data lines to the spare chips.
- the cross-point memory cell (CPM) includes an address register for locating and mapping data to a defective chip and to-and-from a spare chip.
- data may be written to a memory array using an (ECC), check sum, parity, or the like, and the data may be read and verified;
- ECC ECC
- check sum parity
- parity or the like
- a defective chip may be located in the memory array
- the defective chip may be replaced with a spare chip by actuation of the sparer chip and an electronic route may be established for data through the cross-point memory (CPM) all to and from the spare chip.
- CPM cross-point memory
- FIG. 1 is a schematic diagram showing components of a computer system with a spare memory arrangement constructed in accordance with the invention
- FIG. 2 is a block diagram showing operation of a spare memory system constructed in accordance with the invention
- FIG. 3 is an electrical schematic showing an array of cross-point memory (CPM) cells in a sparer chip and their interface with bus data lines, memory data lines, and spare data lines constructed in accordance with the invention;
- CCM cross-point memory
- FIG. 4 is a schematic of an address register for a cross-point memory cell of the sparer chip of FIG. 3;
- FIG. 5 is an electrical schematic of a spare memory system constructed in accordance with the invention shown with a by-1 memory arrangement;
- FIG. 6 is an electrical schematic of a spare memory system constructed in accordance with the invention shown with a by-4 memory arrangement;
- FIG. 7 is an electrical schematic of a single crosspoint memory (CPM) cell of a sparer chip constructed in accordance with the invention.
- FIG. 8 is a schematic of an address register and control section for the cross-point memory (CPM) cell shown in FIG. 7.
- CCM cross-point memory
- a memory system constructed in accordance with the invention is shown and generally designated as 10.
- the memory system 10 is coupled to a central processing unit (CPU) 12, which is the computer module which fetches, decodes, and executes instructions.
- the (CPU) 12 in turn is coupled to an I/O device 14 which communicates information to and from the (CPU) 12.
- the (CPU) 12 may also be coupled to a read-only memory (ROM) 16 and a memory storage device 18.
- ROM read-only memory
- Memory interface logic 17 physically connects the memory system 10 to the (CPU) 12 and detects errors through an error correction code (ECC) or other suitable means.
- ECC error correction code
- the memory system 10 is comprised of a memory array 19 including a plurality of semiconductor chips that retain data either electronically or magnetically.
- the memory chips 19 may be arranged in a matrix of rows and columns. Each memory chip 19, in turn, reads or writes data through an address register included within the chip.
- a memory system 10 constructed in accordance with the invention also includes a plurality of spare memory chips 20 identical in construction to the memory chips 19 in the memory array and a plurality of sparer chips 22 for replacing a defective memory chip with a spare memory chip.
- the memory system 10 of the invention is intended for use in conjunction with periodic memory testing in which some type of error correction (ECC) is utilized to detect a faulty memory chip 19 in the memory array.
- ECC error correction
- ECC a.
- a cross-point memory (CPM) cell 23 and address register 28 within the sparer chip 22 representing the location of the defective chip is determined;
- the cross-point memory (CPM) cell 23 of a spare chip 22 is actuated and during a read to the defective chip 24 disconnects the defective chip 24 and replaces it with a spare chip 20;
- the data are written to both the defective memory chip 24 and the spare memory chip 20.
- FIG. 2 This sequence of operations is shown in a block diagram in FIG. 2.
- the invention thus allows a replacement or spare memory chip 26 to be enabled upon detection of a defective memory chip 24 to replace the defective chip 24.
- the defective memory chip 24 is first detected and located by an (ECC) scheme, check sum, parity, or any other suitable error detection means.
- ECC error detection
- This error detection may occur as a result of periodic memory testing.
- a memory chip, for example, just before failure may exhibit a gradual increase in failure rate, which can be monitored.
- a defective memory chip 24 along with its location can thus be identified.
- a sparer chip 26 can access the defective memory chip 24 through an address register 28 included within the cross-point memory (CPM) cell 23 of sparer chip 26.
- the cross-point memory (CPM) cell 23 is constructed to be actuated upon a read to the defective memory chip 24 and to replace the defective memory chip 24 with a spare or replacement chip 26. Data can then be routed to and from the spare chip 26 through the cross-point memory (CPM) cell 23 of sparer chip 22 and back to the (CPU) 12.
- a plurality of cross-point memory CPM) cells 23 are located in each sparer chip 22.
- Each cross-point memory (CPM) cell 23 includes a cross-point memory address register 28 that allows data to be mapped to and from the (CPU) through the spare chip 26.
- the cross-point memory (CPM) cell 23 is adapted to switch this data to the spar chip 26 upon signals from the (CPU) 12.
- a read/write map can thus be established to and from the spare chip 26 to the (CPU).
- the sparer chip 22 constructed in accordance with the invention for a by-8 memory device is shown.
- the sparer chip 22 includes eight separate banks B(0:8), any of which can be accessed through a bank select line.
- Each bank B(0:8) includes forty bus data lines (BD o -BD 39 ) as a route for any values moving from memory to the (CPU) 12.
- a plurality of cross-point memory (CPM) cells 23 are located between the data bus lines (BD o -BD 39 ) and memory data lines (MD o -MD 39 ) and are also connected to the spare memory chips 20 through sparer lines (SD o -SD 7 ).
- the memory data lines (MD o -MD 39 ) in turn are connected to the individual semiconductor memory CHIPS 19 of the memory array chips.
- a lesser or greater number of spare memory chips 26 and sparer lines (SD o -SD 7 ) may be provided depending on the application.
- the spare memory chips 26 are preferably of the same construction as the memory chips 19 in the memory array.
- Each sparer chip 22 is thus connected to a sparing line (SD o -SD 7 ) to the memory data lines (MD o -MD 39 ) and to the bus data lines (BD o -BD 39 ) by the plurality of cross-point memory (CPM) cells 23.
- each sparing line (SD o -SD 7 ) is connected to spare chips which are preferably identical in construction to the chips in memory.
- Each spare memory chip 26 is fully independent to any other memory chip.
- the cross-point memory (CPM) cells 23 allow the 8-bit (SD o -SD 39 ) sparing lines to be connected to any of the 40 bus data (BD o -BD 39 ) lines.
- the cross-point memory (CPM) cells 23 function to disconnect a write from a defective chip 24 through the bus data lines (BD o -BD 39 ) to the (CPU) 12.
- Each sparing line (SD o -SD 7 ) connects to all the bus data lines (BD o -BD 39 ) via the plurality of cross-point memory (CPM) cells 23.
- Each cross-point memory (CPM) cell 23 can be actuated by the (CPU) 12 to connect a sparing line (SD o -SD 7 ) to a bus data line (BD o -BD 39 ) while at the same time disconnecting a memory data line (MD o -MD 39 ) during a read to a defective memory chip 24. On a write, the data are written to both the defective memory chip 24 and the spare memory chip 26.
- a cross-point memory (CPM) address register 28 is included in each cross-point memory (CPM) cell 23.
- the (CPM) address register 28 functions as a means for mapping a route to and from the spare chips 26 through the cross-point memory (CPM) cells 23 to the (CPU).
- each actuated cross-point memory (CPM) cell 23 is addressed through a bank number (9 bits), a sparing position coordinate of row (2 bits) and column (3 bits), and read enable and write enable flag bits.
- a spare memory chip 26 can be assigned to shadow a suspected defective memory chip 24 such that data is written to both the defective chip 24 and spare memory chip 26 (i.e., allows only one or the other to be read).
- the cross-point memory (CPM) cell 23 can be actuated to disconnect a read from the defective chip 24 and connect a read from the spared memory chip 26 to the (CPU).
- All cross-point memory (CPM) cells 23 compare their bank number to the incoming bank number.
- a cross-point memory (CPM) cell 23 that matches incoming bank data will connect its bus data (BD o -BD 39 ) to the sparing line (SD o SD 7 ) and actuate the appropriate row and column lines.
- BD o -BD 39 bus data
- SD o SD 7 sparing line
- the same row number must be used for a given bank number to differentiate the row-to-column matrix. If two or more sparer chips 22 are to be assigned per bank number, they must have the same row number for a unique sparer chip 22 to be accessed.
- each cross-point memory (CPM) cell 23 provides a logic circuit for mapping data to and from the spare chips 26 through the sparer data line (SD n ) and to the (CPU) 12.
- the logic circuit is controlled by four control inputs CNTRL 1 -CNTRL 4 which are accessed through the cross-point memory register 28 to the appropriate cross-point memory (CPM) cell 23 for a defective chip 24. It is to be understood that this is an illustrative circuit and that other logic arrangements would also be suitable for this application.
- a first logic circuit 32 is located between the bus data lines (BD n ) and memory data lines (MD n ) and includes a driver component 34 and a receiver component 36 connected in parallel.
- a second logic circuit 38 is located between the bus data lines (BD n ) and spare data lines (SD n ) and includes a driver component 40 and receiver component 42.
- each logic circuit 32, 38 can be controlled by input from CNTRL 1 -CNTRL 4 to control input/output between the bus data lines (BD n ) and either the memory data lines (MD n ) or the spare data lines (SD n ).
- each cross-point memory (CPM) cell 23 may include a control section 46 which accesses a cross-point memory (CPM) cell 23 through the cross-point memory (CPM) register 28.
- FIG. 5 a memory constructed in accordance with the invention for a 32x1 memory (i.e., has only one input/output) is shown.
- a plurality of spare memory chips 26 are connected to a sparer chip 22 via the sparer data lines (SD o -SD 7 ) and row (ROW o -ROW 4 ) and column (COL o -COL 7 ) lines.
- a sparer chip 22 in turn is connected through memory data lines (MD o -MD 39 ) to the memory array 19.
- a sparer chip 22 is also connected to the (CPU) via the bus data lines (BD o -BD 39 ).
- FIG. 6 a memory constructed in accordance with the invention for a 32x4 memory (i.e.
- a by-8 memory sparing chip configuration could be constructed the same as the by-4 illustrated in FIG. 6, except all eight sparer data lines (SD o -SD 8 ) would go to each chip for a total of 32 spare memory chips 26.
- the spare memory chips 26 are preferably identical to the memory chips in the memory array 19. In assigning a spare memory chip 26 for each bank, it must have the same row address number.
- the spare memory arrangement 10 illustrated could also be constructed with a DRAM controller built into it.
- the sparer chips 22, for instance, could control both the memory in the array as well as the sparing memory.
- an (ECC) function and a counter-per-bank could also be built into the sparer chip 22.
- Each counter could total the (ECC) correction and record the bit number that was corrected. This counter could be read periodically to determine if a defective memory chip 24 needs to be replaced. A memory chip just before failure may exhibit a gradual increase in failure rate which could be monitored for switching to a spare memory chip 26.
- the sparing memory arrangement 10 of the invention provides a novel and unobvious means for replacing a defective memory chip 24 with a spare memory chip 26. If a single bit line fails, for instance, a whole chip can be replaced. This is opposed to prior art redundant row and column arrangements which, in general, function to replace single bit lane losses.
- the invention has been described for use with a 32 data bit, with 8 check bits and 8 sparing bits, it is to be understood that this configuration is not fixed. If, for example, greater reliability is required for a memory array, more sparing components can be assigned by increasing the row or column of sparing bits.
Abstract
Description
Claims (13)
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US07/621,869 US5276834A (en) | 1990-12-04 | 1990-12-04 | Spare memory arrangement |
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US07/621,869 US5276834A (en) | 1990-12-04 | 1990-12-04 | Spare memory arrangement |
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Cited By (28)
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WO2001007924A1 (en) * | 1999-07-21 | 2001-02-01 | Credence Systems Corporation | Built-in spare row and column replacement analysis system for embedded memories |
US20010052637A1 (en) * | 1996-10-08 | 2001-12-20 | Salman Akram | Memory modules including capacity for additional memory |
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US20030163767A1 (en) * | 2002-02-27 | 2003-08-28 | Andrew Phelps | Memory subsystem including an error detection mechanism for address and control signals |
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US20040003337A1 (en) * | 2002-06-28 | 2004-01-01 | Cypher Robert E. | Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure |
US20040003336A1 (en) * | 2002-06-28 | 2004-01-01 | Cypher Robert E. | Error detection/correction code which detects and corrects memory module/transmitter circuit failure |
US20040088636A1 (en) * | 2002-06-28 | 2004-05-06 | Cypher Robert E. | Error detection/correction code which detects and corrects a first failing component and optionally a second failing component |
US20040123016A1 (en) * | 2002-12-23 | 2004-06-24 | Doblar Drew G. | Memory subsystem including memory modules having multiple banks |
US20040163002A1 (en) * | 2003-02-18 | 2004-08-19 | Doblar Drew G. | Memory system including independent isolated power for each memory module |
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US20070040109A1 (en) * | 2004-09-16 | 2007-02-22 | Mark Schwartz | Spotlight mounted motion detector |
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US7530008B2 (en) | 2003-08-08 | 2009-05-05 | Sun Microsystems, Inc. | Scalable-chip-correct ECC scheme |
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