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Numéro de publicationUS5332467 A
Type de publicationOctroi
Numéro de demandeUS 08/122,948
Date de publication26 juil. 1994
Date de dépôt20 sept. 1993
Date de priorité20 sept. 1993
État de paiement des fraisPayé
Numéro de publication08122948, 122948, US 5332467 A, US 5332467A, US-A-5332467, US5332467 A, US5332467A
InventeursChing-Tzong Sune, Chih-Yuan Lu
Cessionnaire d'origineIndustrial Technology Research Institute
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Chemical/mechanical polishing for ULSI planarization
US 5332467 A
Résumé
A method of planarizing a wafer surface by using a polishing stop with chemical/mechanical polishing is described. A semiconductor wafer, on which there is a rugged surface with broad indentations, is provided. A first layer is formed over the rugged surface. A hard film layer is formed over the first layer. The first layer and the hard film layer are patterned to form polishing stop islands in the broad indentations. A second layer is formed over the rugged surface and the polishing stop islands, to create a top surface for polishing, the top surface and the rugged surface being less hard than the hard film layer. The top surface is polished in a vertical direction to remove portions of the top surface, until the top surface is co-planar with the top of the polishing stop islands. The remainder of the hard film layer is removed to complete the planar surface.
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Revendications(20)
What is claimed is:
1. A method of forming a planar surface on a semiconductor wafer, on which there is a rugged surface with broad indentations, comprising the steps of:
forming a first layer over said rugged surface;
forming a hard film layer over said first layer;
patterning said first layer and said hard film layer to form polishing stop islands in the broad indentations;
forming a second layer over said rugged surface and said polishing stop islands, to create a top surface for polishing, said top surface and said rugged surface being less hard than said hard film layer;
polishing said top surface in a vertical direction to remove portions of said top surface, until said top surface is co-planar with top of said polishing stop islands; and
removing the remainder of said hard film layer to complete said planar surface.
2. The method of claim 1 wherein said polishing is by chemical/mechanical polishing.
3. The method of claim 2 wherein said chemical/mechanical polishing is with a polishing slurry containing aluminum oxide.
4. The method of claim 1 wherein said hard film layer is a diamond film.
5. The method of claim 4 wherein said diamond film is a diamond-like carbon film.
6. The method of claim 4 wherein said diamond film is patterned by ion beam assisted etching.
7. The method of claim 1 wherein said hard film layer is niobium carbide.
8. A method of forming a planar surface on a semiconductor wafer on which there is a first dielectric layer and a patterned first metal layer, comprising the steps of:
forming a second dielectric layer with broad indentations over said first dielectric layer and said patterned first metal layer;
forming a third dielectric layer over said second dielectric layer;
forming a hard film layer over said third dielectric layer;
patterning said third dielectric layer and said hard film layer to form polishing stop islands in said broad indentations;
forming a fourth dielectric layer over said second dielectric layer and said polishing stop islands, to create a top surface for polishing, said fourth and second dielectric layers being less hard than said hard film layer;
polishing said top surface in a vertical direction to remove portions of said top surface, until said top surface is co-planar with top of said polishing stop islands; and
removing the remainder of said hard film layer to complete said planar surface.
9. The method of claim 8 wherein said polishing is by chemical/mechanical polishing.
10. The method of claim 9 wherein said chemical/mechanical polishing is with a polishing slurry containing aluminum oxide.
11. The method of claim 8 wherein said hard film layer is a diamond film.
12. The method of claim 11 wherein said diamond film is patterned by ion beam assisted etching.
13. The method of claim 8 wherein said second, third and fourth dielectric layers are silicon oxide deposited by low pressure chemical vapor deposition.
14. A method of forming a semiconductor wafer having multiple levels of metallization with planar interlevel dielectric layers between each level of metallization, on which there is a first dielectric layer with broad indentations and a patterned first metal layer, comprising the steps of:
forming a second dielectric layer over said first dielectric layer and said patterned first metal layer;
forming a third dielectric layer over said second dielectric layer;
forming a hard film layer over said third dielectric layer;
patterning said third dielectric layer and said hard film layer to form polishing stop islands in the broad indentations;
forming a fourth dielectric layer over said second dielectric layer and said polishing stop islands, to create a top surface for polishing, said fourth and second dielectric layers being less hard than said hard film layer;
polishing said top surface in a vertical direction to remove portions of said top surface, until said top surface is co-planar with top of said polishing stop islands; and
removing the remainder of said hard film layer to complete said planar surface and form an interlevel dielectric.
15. The method of claim 14 further comprising the steps of:
etching said planar surface to create vias and thus expose said first metal layer; and
forming and patterning a second metal layer on said planar surface and in said vias.
16. The method of claim 15 further comprising the steps of creating a plurality of planar interlevel dielectrics and levels of metal on top of said second metal layer, by repeating the same steps.
17. The method of claim 14 wherein said polishing is by chemical/mechanical polishing.
18. The method of claim 17 wherein said chemical/mechanical polishing is with a polishing slurry containing aluminum oxide.
19. The method of claim 14 wherein said hard film layer is a diamond film.
20. The method of claim 19 wherein said diamond film is a diamond-like carbon film.
Description
BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to semiconductor manufacturing, and, more particularly, to a method for making planar interlevel dielectric surfaces, using chemical/mechanical polishing and a hard film to act as a polishing stop.

(2) Description of the Related Art

Semiconductor devices created on a substrate need to be connected together, which is accomplished typically by a layer of metal that contacts the devices and connects them together or to pads at the exterior surface of the chip. As the density of semiconductor devices increases, there is an increasing need to use more than one layer of metallization for interconnection. Each layer of metal is separated by an insulating layer, also referred to as an interlevel dielectric (ILD), with connections made between the layers by vias in the ILD. However, for each additional layer of metal, the top surface of the ILD layers become less and less planar, or smooth, which ultimately leads to reliability problems due to the difficulty of depositing metal on these uneven surfaces.

There is thus a need to planarize the ILD surfaces. Planarization in semiconductor manufacturing has typically been accomplished by such techniques as BPSG reflow, planarization with resist, or SOG planarization. In BPSG reflow, a layer of borophosphosilicate (BPSG) glass is deposited and then heated to a temperature of greater than 800° C. The heating step causes this material to soften and flow, providing a smoother surface, as described in S.M. Sze, "VLSI TECHNOLOGY", published by McGraw-Hill Internaltional - Singapore, 1988, pages 255-257. However, the temperatures used in this process are too high if aluminum, the most common metallization material, has already been deposited on the wafer. Also, BPSG reflow is most effective for narrow indentations, that is, very small areas of the ILD surface. Broad indentations in the surface are not made planar, and thus BPSG reflow does not provide for adequate "global" planarization (planarization across the entire wafer surface).

A second planarization technique is planarization with resist or "resist etchback". One example method is described by Fujii et al in "A Planarization Technology Using a Bias-Deposited Dielectric Film and an Etch-Back Process", published in IEEE Transactions on Electron Devices, November, 1988. However, the resist etchback techniques require an increased dielectric thickness, additional process steps, and typically require that the dielectric and resist have similar etch rates, which is difficult to accomplish and control.

An example of SOG planarization is described in U.S. Pat. No. 4,676,867 by Elkins et al. This method requires the curing of a spin-on glass (SOG) layer, which converts the SOG to silicon dioxide. However, contaminants result when the structure is heated to greater than 300° C., which evolve and corrode the aluminum vias.

A more recent planarization method is known as chemical/mechanical polishing, or CMP. A semiconductor wafer is held and rotated against a polishing surface, on which there is a polishing slurry containing abrasive material such as alumina or silica. At the same time, a chemical etchant may be introduced so that material is removed from the wafer by both chemical and mechanical means. U.S. Pat. Nos. 5,084,419 and 5,084,071 describe the use of CMP for providing a smooth substrate, prior to any metallization steps.

One difficulty in using CMP is determining when the planarization is complete. U.S. Pat. No. 5,036,015 describes a method to detect the planarization endpoint using the frictional difference between two materials. U.S. Pat. No. 5,081,421 describes the use of a capacitive measure of the dielectric thickness for insitu endpoint detection. U.S. Pat. No. 5,081,796 uses a laser interferometer for endpoint detection. However, these methods all require additional instrumentation to detect the completion of the chemical/mechanical polishing.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide a simple method for providing a polishing stop when using chemical/mechanical polishing for planarization of a wafer surface.

It is a further object of this invention to provide a simple method for providing a polishing stop when using chemical/mechanical polishing for planarization of interlevel dielectric surfaces with multiple levels of metallization.

This object is achieved by providing a semiconductor wafer, on which there is a rugged surface with broad indentations. A first layer is formed over the rugged surface. A hard film layer is formed over the first layer. The first layer and the hard film layer are patterned to form polishing stop islands in the broad indentations. A second layer is formed over the rugged surface and the polishing stop islands, to create a top surface for polishing, the top surface and the rugged surface being less hard than the hard film layer. The top surface is polished in a vertical direction to remove portions of the top surface, until the top surface is co-planar with the top of the polishing stop islands. The remainder of the hard film layer is removed to complete the planar surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 8 are a cross-sectional representation of a method for providing a CMP polishing stop for planarization of interlevel dielectrics.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, a substrate 10 is shown, along with field isolation region 12 and transistor 14. These are formed by methods well known in the art and as they are not significant to the invention, will not be described in detail. Although a metal oxide semiconductor (MOS) device is depicted as transistor 14, it will be understood by those familiar with the art that a bipolar transistor could also be used.

A dielectric layer 16, composed of, for instance, silicon oxide formed by low pressure chemical vapor deposition (LPCVD), is deposited to a thickness of between about 2000 and 5000 Angstroms. This layer is patterned to form vias 17 through which metal layer 18 contacts with the active regions of transistor 14. The metal layer 18 is formed of titanium / aluminum (Ti/Al), titanium nitride / aluminum (TiN/Al), or titanium / titanium nitride / aluminum (Ti/TiN/Al). The preceding metal combinations could also be formed with silicon or copper in place of the aluminum. Titanium nitride / tungsten (TiN/W) could also be used, as could many other metal combinations as is well known by those skilled in the art. The metal layer 18 is formed to a thickness of between about 8000 and 12,000 Angstroms and is deposited by sputtering, evaporation, or chemical vapor deposition. This metal layer is then patterned as required for device interconnection.

Referring now to FIG. 2, a dielectric layer 20 is blanket-deposited by low pressure chemical vapor deposition (LPCVD) over dielectric layer 16 and metal layer 18. This layer is a high-quality oxide, for instance, silicon dioxide SiO2, formed to a thickness of between about 5000 and 10,000 Angstroms. In the prior art SOG planarization, curing of the spin-on-glass (SOG) causes contamination and degradation of the adjacent metal, which is avoided in this invention by the use of a high-quality oxide, and no curing requirement.

As can be seen in FIG. 2, the top surface 22 follows the contours of the underlying surfaces and is not planar. Narrow indentations 24 and broad indentations 26 are formed, and it is these broad indentations that prior art processes such as BPSG reflow can not fill, thus failing to provide global planarization.

Referring now to FIG. 3, second dielectric layer 28, which would typically be silicon oxide deposited by LPCVD, is deposited to a thickness of between about 5000 and 10,000 Angstroms over first dielectric 20. In the critical step of this invention, a hard film layer 30 is deposited. This is preferably diamond, which is deposited, for example, by radio frequency (RF) plasma CVD as described in "Diamond-like carbon as an electrical insulator of copper devices for chip cooling", by E. Marotta et al, in Thin Solid Films, 206(1991), to a thickness of between about 1000 and 2000 Angstroms. In this process, the diamond-like carbon (DLC) film is formed by the r.f. plasma decomposition of acetylene (C2 H2). The Knoop hardness of the diamond-like carbon thus formed is between about 3000 and 9000 kg/mm2. This layer could also be formed of materials such as niobium carbide NbC, niobium Nb, cobalt Co or aluminum oxide Al2 O3. The primary requirement for this hard film layer material is that it have a hardness greater than that of silicon oxide, or whatever alternate dielectric material is being used. The hardnesses of various relevant materials are shown below in Table I.

              TABLE I______________________________________(source: CRC Handbook of metal etchants, P. Walkerand W. H. Tam, CRC Press Inc., 1991)Material        Hardness (Mohs scale)______________________________________diamond         10niobium carbide NbC           9+Al2 O3           9cobalt Co       8+niobium Nb      7-8silicon         7SiO2       6-7Si3 N4           6-7______________________________________

The hard film layer 30 will be used as a polishing stop for chemical/mechanical polishing of the top surface. The polishing stop film was chosen to have a high selectivity of polishing rate as compared to the dielectric, and the hardness of the polishing stop film is larger than that of the polishing slurry, or may be less than the slurry hardness but greater than the dielectric.

The wafer is now patterned by conventional lithography, and etched to form polishing stop islands 31. When diamond is used for layer 30, it is etched by, for example, ion-beam assisted etching, as described in "Ion-beam-assisted etching of diamond", N.N. Efremow et al, J. Vac. Scio Technol., Jan/Feb 1985. This approach uses a Xe+ beam and a reactive gas flux of NO2 to achieve a high etch rate ratio of 20 between the diamond and an aluminum mask.

Layer 28 is etched, using the same mask as for the hard film layer 30, by reactive ion etch or wet chemical etching. A reactive ion etch of layer 28 would use, for example, CHF3 as a source gas with the addition of 02. This completes formation of polishing stop islands 31, which are formed in broad indentations on the top surface 22.

Referring now to FIG. 4, a third dielectric layer 32, of, for example, SiO2, is deposited to a thickness of between about 10,000 and 15,000 Angstroms. This layer fills in the gaps between the polishing stop islands, and other indentations on the surface.

Referring now to FIG. 5, chemical/mechanical polishing is used to planarize the top surface. The wafer is held and rotated against a polishing surface, on which there is a polishing slurry containing abrasive material such as alumina or silica. At the same time, a chemical etchant may be introduced, as is well known in the art, so that material is removed from the wafer by both chemical and mechanical means. As the polishing rate of the polishing stop islands is relatively low compared to the rate of the surrounding dielectric, the polishing will stop as the wafer surface reaches the level of the top hard film of the polishing stop islands. Due to the chemical etch, the surface of the now planar layer 34 will be slightly lower than the top of polishing stop island 30.

There are several possible combinations of hardnesses of the materials used for the top hard film, the polishing slurry, and the dielectric. The polishing slurry hardness must always be greater than that of the dielectric, in order for the mechanical polishing to take place. If the material chosen for the top hard film has a hardness that is greater than that of the polishing slurry (for instance, a diamond film (hardness 10 on the Mohs scale) with Al2 O3 slurry (hardness 9)), the hard film layer will inhibit further polishing when the polishing surface reaches the hard film. The thickness of the hard film layer may be kept to a minimum in this instance, which will improve the overall planarization after the hard film is removed.

The hardness of the hard film layer material could also be chosen to be between that of the slurry and dielectric. As long as the hard film hardness is much greater than that of the dielectric, endpoint detection is not needed. The completion of polishing is controlled by monitoring the polishing time. Since the slurry will also polish the hard film layer, though at a lower rate than the dielectric, a thicker hard film layer is required to provide sufficient process latitude. If the hard film hardness is close to that of the dielectric, then a combination of the hard film layer and endpoint detection could be used to planarize the wafer.

Referring now to FIG. 6, hard film layer 30 is removed by either dry or wet chemical etching or, for example, ion-beam-assisted etching for a diamond film. This results in the final, globally planarized surface 35. If more layers of metal are desired to be added, vias 36 may be etched as shown in FIG. 7, to provide openings to contact the first metal. A second metal layer 38 is deposited, using the same materials and process as the first metal layer, to fill vias 36 and on top surface 35. It is patterned by conventional lithography and etching, and then a similar planarization process as that described above is accomplished.

Referring now to FIG. 8, this would result in planar top surface 40. This process could be repeated to provide n planarized surfaces with n dielectric/via/metal layers for up to n levels of metallization, with nth dielectric 42, nth via 44, nth metal 46 and nth planar top surface 48.

Referring now back to FIG. 2, it may be understood by those skilled in the art that top surface 22 could be any rugged surface, regardless of the underlying structures. Polishing islands may be formed in broad indentations 26, and a subsequent layer added which is polished back using the chemical/mechanical polishing steps discussed above. The hard film layer needs only to be harder than the surfaces that are to be polished, in order for the hard film to act as a polishing stop. The hard film is then removed, resulting in a planar top surface.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Citations de brevets
Brevet cité Date de dépôt Date de publication Déposant Titre
US4676867 *6 juin 198630 juin 1987Rockwell International CorporationPlanarization process for double metal MOS using spin-on glass as a sacrificial layer
US5036015 *24 sept. 199030 juil. 1991Micron Technology, Inc.Method of endpoint detection during chemical/mechanical planarization of semiconductor wafers
US5081421 *1 mai 199014 janv. 1992At&T Bell LaboratoriesIn situ monitoring technique and apparatus for chemical/mechanical planarization endpoint detection
US5081796 *6 août 199021 janv. 1992Micron Technology, Inc.Method and apparatus for mechanical planarization and endpoint detection of a semiconductor wafer
US5084071 *23 févr. 199028 janv. 1992International Business Machines CorporationMethod of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US5084419 *23 mars 198928 janv. 1992Nec CorporationMethod of manufacturing semiconductor device using chemical-mechanical polishing
US5094972 *14 juin 199010 mars 1992National Semiconductor Corp.Means of planarizing integrated circuits with fully recessed isolation dielectric
US5246884 *30 oct. 199121 sept. 1993International Business Machines CorporationCvd diamond or diamond-like carbon for chemical-mechanical polish etch stop
Citations hors brevets
Référence
1"A Planarization Technology Using a Bias-Deposited Dielectric Film and an Etch-Back Process" published in IEEE Transactions on Electron Devices, No. 1988.
2 *A Planarization Technology Using a Bias Deposited Dielectric Film and an Etch Back Process published in IEEE Transactions on Electron Devices, No. 1988.
3 *VLSI Technology, published by McGraw Hill International Singapore, 1988, pp. 255 257.
4VLSI Technology, published by McGraw-Hill International-Singapore, 1988, pp. 255-257.
Référencé par
Brevet citant Date de dépôt Date de publication Déposant Titre
US5449314 *25 avr. 199412 sept. 1995Micron Technology, Inc.Planarizing
US5468682 *13 déc. 199421 nov. 1995Nec CorporationForming wiring layer on insulating film covering semiconductor substrate, forming interlayer insulating film with silicon oxide film on wiring and insulating film, polishing interlayer film with fluorinated silicon oxide abrasive particles
US5532188 *30 mars 19942 juil. 1996Wright; Peter J.Global planarization of multiple layers
US5534462 *24 févr. 19959 juil. 1996Motorola, Inc.Method for forming a plug and semiconductor device having the same
US5536202 *27 juil. 199416 juil. 1996Texas Instruments IncorporatedSemiconductor substrate conditioning head having a plurality of geometries formed in a surface thereof for pad conditioning during chemical-mechanical polish
US5578523 *18 mai 199526 nov. 1996Motorola, Inc.Method for forming inlaid interconnects in a semiconductor device
US5595527 *7 juin 199521 janv. 1997Texas Instruments IncorporatedApplication of semiconductor IC fabrication techniques to the manufacturing of a conditioning head for pad conditioning during chemical-mechanical polish
US5633207 *14 oct. 199427 mai 1997Kabushiki Kaisha ToshibaMethod of forming a wiring layer for a semiconductor device
US5668063 *23 mai 199516 sept. 1997Watkins Johnson CompanyMethod of planarizing a layer of material
US5731245 *28 oct. 199624 mars 1998International Business Machines Corp.High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap
US5747380 *26 févr. 19965 mai 1998Taiwan Semiconductor Manufacturing Company, Ltd.Robust end-point detection for contact and via etching
US5795495 *8 sept. 199518 août 1998Micron Technology, Inc.Method of chemical mechanical polishing for dielectric layers
US5844362 *12 juil. 19961 déc. 1998Matsushita Electric Industrial Co., Ltd.Electroluminescent light element having a transparent electrode formed by a paste material which provides uniform illumination
US5866436 *31 mai 19952 févr. 1999Lucent Technologies Inc.Process of manufacturing an intergrated circuit having an interferometrically profiled mounting film
US5904563 *20 mai 199618 mai 1999Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuits
US5904573 *22 mars 199618 mai 1999Taiwan Semiconductor Manufacturing Company,Ltd.PE-TEOS process
US5916453 *20 sept. 199629 juin 1999Fujitsu LimitedMethods of planarizing structures on wafers and substrates by polishing
US5928960 *24 oct. 199627 juil. 1999International Business Machines CorporationProcess for reducing pattern factor effects in CMP planarization
US5994241 *31 juil. 199630 nov. 1999International Business Machines CorporationMethod of forming conductive lines on a semiconductor wafer
US626531524 juin 199824 juil. 2001Taiwan Semiconductor Manufacturing CompanyMethod for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits
US627112329 mai 19987 août 2001Taiwan Semiconductor Manufacturing CompanyChemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG
US6514865 *11 janv. 20024 févr. 2003Advanced Micro Devices, Inc.Method of reducing interlayer dielectric thickness variation feeding into a planarization process
US653713328 sept. 200025 mars 2003Applied Materials, Inc.Method for in-situ endpoint detection for chemical mechanical polishing operations
US667671728 sept. 200013 janv. 2004Applied Materials IncApparatus and method for in-situ endpoint detection for chemical mechanical polishing operations
US671981824 févr. 199813 avr. 2004Applied Materials, Inc.Apparatus and method for in-situ endpoint detection for chemical mechanical polishing operations
US673368512 juin 200111 mai 2004Fujitsu LimitedMethods of planarizing structures on wafers and substrates by polishing
US684915219 juil. 20011 févr. 2005Applied Materials, Inc.In-situ real-time monitoring technique and apparatus for endpoint detection of thin films during chemical/mechanical polishing planarization
US686079125 nov. 20031 mars 2005Applied Materials, Inc.Polishing pad for in-situ endpoint detection
US687507825 mars 20035 avr. 2005Applied Materials, Inc.Apparatus and method for in-situ endpoint detection for chemical mechanical polishing operations
US688167428 déc. 199919 avr. 2005Intel CorporationAbrasives for chemical mechanical polishing
US700124216 avr. 200221 févr. 2006Applied Materials, Inc.Method and apparatus of eddy current monitoring for chemical mechanical polishing
US702406325 janv. 20054 avr. 2006Applied Materials Inc.In-situ real-time monitoring technique and apparatus for endpoint detection of thin films during chemical/mechanical polishing planarization
US703740314 août 19982 mai 2006Applied Materials Inc.In-situ real-time monitoring technique and apparatus for detection of thin films during chemical/mechanical polishing planarization
US70871885 févr. 20038 août 2006Intel CorporationAbrasives for chemical mechanical polishing
US756911921 févr. 20064 août 2009Applied Materials, Inc.In-situ real-time monitoring technique and apparatus for detection of thin films during chemical/mechanical polishing planarization
US758218324 oct. 20071 sept. 2009Applied Materials, Inc.Apparatus for detection of thin films during chemical/mechanical polishing planarization
US759170826 sept. 200522 sept. 2009Applied Materials, Inc.Method and apparatus of eddy current monitoring for chemical mechanical polishing
US818790026 oct. 201029 mai 2012Hong Kong Applied Science and Technology Research Institute Company LimitedOptimization of polishing stop design
US822206427 juil. 201117 juil. 2012Hong Kong Applied Science and Technology Research Institute Company LimitedVertical light emitting diode device structure and method of fabricating the same
US8395168 *6 juin 200812 mars 2013Hong Kong Applied Science And Technology Research Institute Co. Ltd.Semiconductor wafers and semiconductor devices with polishing stops and method of making the same
US841518610 août 20079 avr. 2013Hong Kong Applied Science And Technology Research Institute Co. Ltd.Method of super flat chemical mechanical polishing technology and semiconductor elements produced thereof
US20090302336 *6 juin 200810 déc. 2009Hong Kong Applied Science And Technology Research InstituteSemiconductor wafers and semiconductor devices and methods of making semiconductor wafers and devices
CN101244533B16 févr. 200715 sept. 2010香港应用科技研究院有限公司Method of ultra-flation chemical-mechanical polishing technique and semiconductor component manufactured by using the method
WO2001048807A1 *20 nov. 20005 juil. 2001Cadien Kenneth CAbrasives for chemical mechanical polishing
WO2004021430A1 *16 juil. 200311 mars 2004Advanced Micro Devices IncMethod for endpoint detection during etch
Classifications
Classification aux États-Unis438/633, 438/693, 438/699, 257/E21.244, 438/624
Classification internationaleH01L21/3105
Classification coopérativeH01L21/31053
Classification européenneH01L21/3105B2
Événements juridiques
DateCodeÉvénementDescription
2 déc. 2008ASAssignment
Owner name: TRANSPACIFIC IP LTD.,, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE;REEL/FRAME:021901/0822
Effective date: 20081114
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Year of fee payment: 12
7 déc. 2001FPAYFee payment
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8 août 1997FPAYFee payment
Year of fee payment: 4
21 sept. 1993ASAssignment
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUNE, CHING-TZONG;LU, CHIH-YUAN;REEL/FRAME:006719/0075
Effective date: 19930825