US5403772A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- US5403772A US5403772A US08/160,908 US16090893A US5403772A US 5403772 A US5403772 A US 5403772A US 16090893 A US16090893 A US 16090893A US 5403772 A US5403772 A US 5403772A
- Authority
- US
- United States
- Prior art keywords
- semiconductor device
- nitrogen
- film
- hydrogen
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 141
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000010408 film Substances 0.000 claims abstract description 219
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 127
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 94
- 239000010703 silicon Substances 0.000 claims abstract description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 92
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 65
- 238000000137 annealing Methods 0.000 claims abstract description 55
- 238000002425 crystallisation Methods 0.000 claims abstract description 44
- 230000008025 crystallization Effects 0.000 claims abstract description 44
- 239000013078 crystal Substances 0.000 claims abstract description 34
- 239000013039 cover film Substances 0.000 claims abstract description 24
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000010409 thin film Substances 0.000 claims abstract description 19
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 14
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 12
- 239000010931 gold Substances 0.000 claims abstract description 12
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- 229910052802 copper Inorganic materials 0.000 claims abstract description 11
- 229910052737 gold Inorganic materials 0.000 claims abstract description 11
- 229910052742 iron Inorganic materials 0.000 claims abstract description 11
- 229910052762 osmium Inorganic materials 0.000 claims abstract description 11
- 239000010948 rhodium Substances 0.000 claims abstract description 11
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 11
- 229910052706 scandium Inorganic materials 0.000 claims abstract description 11
- 229910052709 silver Inorganic materials 0.000 claims abstract description 11
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052741 iridium Inorganic materials 0.000 claims abstract description 10
- 229910052703 rhodium Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052720 vanadium Inorganic materials 0.000 claims abstract description 10
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 10
- 239000011701 zinc Substances 0.000 claims abstract description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 8
- -1 paradium Chemical compound 0.000 claims abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 7
- 239000010941 cobalt Substances 0.000 claims abstract description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 7
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims abstract description 7
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims abstract description 7
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- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000004332 silver Substances 0.000 claims abstract description 7
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- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims abstract description 6
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims abstract description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 116
- 239000012298 atmosphere Substances 0.000 claims description 103
- 238000010438 heat treatment Methods 0.000 claims description 87
- 239000001257 hydrogen Substances 0.000 claims description 70
- 229910052739 hydrogen Inorganic materials 0.000 claims description 70
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 61
- 239000001301 oxygen Substances 0.000 claims description 61
- 229910052760 oxygen Inorganic materials 0.000 claims description 61
- 239000000758 substrate Substances 0.000 claims description 60
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 58
- 229910052757 nitrogen Inorganic materials 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 38
- 239000012535 impurity Substances 0.000 claims description 31
- 239000011159 matrix material Substances 0.000 claims description 28
- 239000011248 coating agent Substances 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 26
- 230000000873 masking effect Effects 0.000 claims description 13
- 150000002431 hydrogen Chemical class 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 12
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 11
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 11
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- 239000000126 substance Substances 0.000 claims description 10
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- 239000002245 particle Substances 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 58
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- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 23
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- 239000004973 liquid crystal related substance Substances 0.000 description 12
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- 239000011574 phosphorus Substances 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
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- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 3
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- WSLDOOZREJYCGB-UHFFFAOYSA-N 1,2-Dichloroethane Chemical class ClCCCl WSLDOOZREJYCGB-UHFFFAOYSA-N 0.000 description 1
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- 229910052750 molybdenum Inorganic materials 0.000 description 1
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- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
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- 238000002310 reflectometry Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
Definitions
- the present invention relates to a method for fabricating an integrated, circuit or more concretely to a semiconductor circuit having a matrix device (including an electro-optic display and semiconductor memory) having a matrix structure and a MOS or MIS (metal-insulator-semiconductor) type field effect element (hereinafter generally referred to as a MOS type element) as a switching element and characterized in its dynamic operation such as a liquid crystal display device and dynamic RAM (DRAM) and a driving circuit therefor or an integrated driving circuit like an image sensor.
- a matrix device including an electro-optic display and semiconductor memory
- MOS or MIS metal-insulator-semiconductor type field effect element
- the present invention particularly relates to a device employing a thin film semiconductor element such as a thin film semiconductor transistor or the like which is formed on an insulating surface as a MOS type element and to a device having a thin film transistor whose active layer is formed by crystal silicon.
- a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate type field effect transistor (TFT) has been fabricated by crystallizing an amorphous silicon film formed by a plasma CVD or thermal CVD method within such an apparatus as an electric furnace for many hours of more than 24 hours at a temperature more than 600° C.
- the many hours of heat treatment has been required in order to obtain sufficient characteristics such as a high field mobility and high reliability.
- Coning 7059 Another problem lies in the temperature of the heat treatment.
- substrates used for fabricating a TFT are roughly divided into those composed of pure silicon oxide such as silica glass and non-alkaline boro-silicated glass such as Coning No. 7059 (hereinafter referred to as Coning 7059).
- the former has no problem in terms of temperature because it has an excellent heat resistance and can be handled in the same manner with the wafer process of normal semiconductor integrated circuits.
- its cost is high and increases exponentially as the substrate area increases. Accordingly, it is used only for TFT integrated circuits having a relatively small area.
- non-alkaline glass has a problem in terms of heat resistance, though its cost is sufficiently low as compare to that of silica glass. Because its strain point is generally around 550° to 650° C., or less than 600° C. in case of a readily available material, such problems as irreversible shrinkage and warp are caused on the substrate in a heat treatment at 600° C. and it is remarkable in such a substrate whose diagonal distance exceeds 10 cm. From above reasons, it has been considered to be indispensable to keep the heat treatment conditions under 550° C. and within 4 hours to reduce the cost in crystallizing silicon semiconductor films. It is then an object of the present invention to provide a semiconductor fabricating method that clears such conditions and a semiconductor device fabricating method using such a semiconductor.
- a thin film insulated gate transistor or so-called a thin film transistor has been fervently studied. They are formed on a transparent insulating substrate to use to control each picture element and to drive its matrix in a display device such as a liquid crystal display having a matrix structure or to use as a driving circuit of an image sensor formed similarly on an insulating substrate. They are categorized as an amorphous silicon TFT or crystalline silicon (or called as polycrystalline silicon) TFT depending on a material and crystal state of a semiconductor used.
- a crystalline silicon TFT is used also in a monocrystal silicon integrated circuit as a so-called SOI technology and it is used as a load transistor for example in a highly integrated SRAM. In this case, however, an amorphous silicon TFT is rarely used.
- a field mobility of a semiconductor in an amorphous state is small and accordingly, it cannot be used for a TFT requiring a high speed operation. Furthermore, because a field mobility of P-type is remarkably small in an amorphous silicon, a P-channel type TFT (a TFT of PMOS) cannot be fabricated and accordingly, a complementary MOS circuit (CMOS) cannot be formed by combining with a N-channel type TFT (a TFT of NMOS).
- CMOS complementary MOS circuit
- a TFT formed by an amorphous semiconductor has an advantage that OFF current is small. Then it is utilized in the use in which a very high speed operation is not required, only one conductive type will do and a TFT having a high charge retaining ability is required such as transistors of an active matrix of a liquid crystal display having a small matrix scale.
- amorphous silicon TFT for an advanced application such as a liquid crystal display having a large scale matrix. Further, it could not be used naturally for peripheral circuits of a display and for a driving circuit of an image sensor which require a high speed operation.
- a crystalline semiconductor has a field mobility larger than that of the amorphous semiconductor and accordingly, a high speed operation is possible.
- a large value as 300 cm 2 /Vs has been obtained as a field mobility in a TFT using a silicon film re-crystallized by laser annealing.
- an operation speed of the MOS circuit on the monocrystal silicon is limited by a parasitic capacity between the substrate and wires, there is no such limit in terms of the TFT using crystallized silicon film because it is formed on the insulating substrate. Accordingly, a remarkable high speed operation is being expected to be achieved in such TFT.
- CMOS circuit by the crystalline silicon because not only a NMOS TFT but also a PMOS TFT can be similarly obtained.
- CMOS crystalline silicon TFT for example, among liquid crystal displays in an active matrix system, one having a so-called monolithic structure in which not only the active matrix section but also peripheral circuits (such as a driver) are constructed by a CMOS crystalline silicon TFT is known.
- the TFT used in the aforementioned SRAM is what this point is noticed, wherein time PMOS is constructed by the TFT as a load transistor.
- the crystalline silicon TFT has such an advantage that a parasitic capacity can be remarkably suppressed because the self-aligning process can be adopted.
- a leak current of the crystalline silicon TFT when no voltage is applied to the gate is great as compare to that of the amorphous silicon TFT, and such countermeasures have been taken that an auxiliary capacity is provided to compensate the leak current and that two TFTs are connected in series to reduce the leak current when it is used in a liquid crystal display.
- a method to form an amorphous silicon and to irradiate laser selectively on it to crystallize only a peripheral circuit has been proposed for forming the peripheral circuit of polysilicon TFTs having a high mobility monolithically on the same substrate while utilizing a high OFF resistance of the amorphous silicon TFT.
- the present invention is intended to solve such difficult problems, but it is not desirable to complicate the process and to lower its yield or to increase its cost for that end.
- What the present invention intends is to fabricate two kinds of TFTs, i.e. a TFT in which a high mobility is required and a TFT in which a leak current is required to be low, readily and discriminately while keeping mass-producibility and while minimizing changes of its process.
- the reduced difference between the NMOS and PMOS allows to increase a degree of freedom in designing the circuit.
- the present invention is suited for an active matrix circuit for displaying images by utilizing such materials which change transmittivity or reflectivity of light by an effect of electric field, by sandwiching those materials between electrodes facing to each other and by applying the electric field between those electrodes such as a liquid crystal display; a memory device for holding memory by storing charge in capacitors such as DRAM; a circuit having a dynamic circuit such as a dynamic shift register which drives the next circuit by capacitors of MOS structure portion of MOS transistors or other capacitors; and a circuit having a digital circuit and a circuit for controlling analog signal outputs such as a driving circuit of an image sensor.
- the present invention is suited especially to a circuit in which dynamic circuits and static circuits are mixedly mounted.
- the present invention is characterized in that a crystalline silicon film is obtained by forming island film, dots, particles, clusters or lines containing a material selected from the group consisting of nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold and silver and a combination thereof on or under the silicon film which is in an amorphous state or in a random crystal state (e.g.
- a state in which portions having a good crystallinity and amorphous portions are mixed which can be said substantially as being in an amorphous state, and by annealing it at a temperature lower than a crystallization temperature in a mere heat treatment of normal amorphous silicon for a shorter time.
- This annealing may be carried out in a hydrogen, oxygen or nitrogen atmosphere.
- This annealing can be carried out by (1) heating for A hours in an atmosphere containing oxygen and then heating for B hours in an atmosphere containing hydrogen: (2) heating for C hours in an atmosphere containing oxygen and then heating for D hours in an atmosphere containing nitrogen: (3) heating for E hours in an atmosphere containing hydrogen and then heating for F hours in an atmosphere containing oxygen: (4) heating for G hours in an atmosphere containing hydrogen and then heating for H hours in an atmosphere containing nitrogen: (5) heating for I hours in an atmosphere containing nitrogen and then heating for J hours in an atmosphere containing oxygen: (6) heating for K hours in an atmosphere containing nitrogen and then heating for L hours in an atmosphere containing hydrogen: (7) heating for M hours in an atmosphere containing oxygen, heating for N hours in an atmosphere containing hydrogen and then heating for P hours in an atmosphere containing nitrogen: (8) heating for Q hours in an atmosphere containing oxygen, heating for E hours in an atmosphere containing nitrogen and then heating for S hours in an atmosphere containing hydrogen: (9) heating for T hours in an atmosphere containing hydrogen, heating for U hours in an atmosphere containing oxygen and then
- nickel silicide NiSi x , 0.4 ⁇ 2.5
- a lattice constant of nickel silicide is close to that of silicon crystal.
- a potential of the block of this reaction is fully low and a reaction temperature is also low.
- This reaction formula indicates that the reaction proceeds while converting amorphous silicon into crystal silicon by nickel. It was found that the reaction actually started at less than 580° C. and that the reaction could be observed even at 450° C. Though it is a matter of course, the higher the temperature, the faster the speed of the advancement of reaction was. The same effect was also recognized with other metal elements described above.
- a crystal silicon region is expanded by forming a film, particle or cluster containing at least one of Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag such as island, stripe, line, dot or film of nickel or other simple metal substances described above or their silicide as a starting point and by developing those metal elements from the point to surroundings along the reaction described above.
- oxide is not preferable as a material containing those metal elements, because oxide is a stable compound and cannot start the aforementioned reaction.
- the crystal silicon expanded from a specific point has a structure close to monocrystal with good continuity of crystallinity, though it differs from the conventional solid phase epitaxial growth, so that it is convenient in using for semiconductor devices such as a TFT.
- an infinite number of crystallization starting points existed when a material containing the aforementioned metals for accelerating the crystallization such as nickel was provided homogeneously on a substrate and due to that, it was difficult to obtain a film having a good crystallinity.
- the concentration of hydrogen within the crystal silicon of the present invention was typically more than 0.01 atomic percent and less than 5 atomic percent.
- Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag are used in the present invention, these materials are not generally preferable for silicon as a semiconductor material and it is necessary to remove them.
- nickel because nickel silicide which reached the end of the crystallization as a result of the aforementioned reaction is easily resolved in hydrofluoric acid or hydrochloric acid or dilution of them, nickel can be reduced from the substrate by means of a treatment by those acids. Further, those metal elements can be positively reduced by treating at 400° to 600° C.
- chlorine such as hydrogen chloride, various methane chlorides (CH 3 Cl, CH 2 Cl 2 , CHCl 3 ), various ethane chlorides (C 2 H 5 Cl, C 2 H 4 Cl 2 , C 2 H 3 Cl 3 , C 2 H 2 Cl 4 , C 2 HCl 5 ) or various ethylene chlorides (C 2 H 3 Cl, C 2 H 2 Cl 2 , C 2 HCl 3 ) after the end of the crystallization process.
- trichloroethylene C 2 HCl 3
- C 2 HCl 3 is a material which can be easily used.
- a concentration of Ni, Fe, Co, Ru, Rh, Pd, Os, It, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag in the silicon film of the present invention was typically more than 0.005 atomic percent and less than 1 atomic percent.
- the crystal silicon film fabricated according to the present invention for a semiconductor element such as a TFT, it is not preferable to provide the semiconductor element on the end of the crystallization (it is also a portion where the crystallization started from a plurality of starting points hit each other) because a large grain boundary (a portion where crystallinity is discontinued) exists and the concentration of metal elements which accelerate the crystallization such as nickel is high there as it is obvious from the description above. Accordingly, a pattern of a coating film containing the metal elements which become the starting point of the crystallization and accelerate it such as nickel and a pattern of the semiconductor element must be optimized in forming the semiconductor element utilizing the present invention.
- a first method is to selectively form a film or the like of those metals before forming an amorphous silicon film and a second method is to selectively form a film or the like of those metals after forming the amorphous silicon film.
- the first method can be implemented by using a normal photolithographic means or lift-off means.
- the second method is complicated more or less. That is, if the film or the like of the metals which accelerate the crystallization is formed adhering to the amorphous silicon film, the metal and the amorphous silicon partially react each other producing silicide when forming the film. Therefore, it is necessary to fully etch such silicide layer when patterning after forming the metal film or the like.
- the lift-off method is relatively easily carried out.
- organic materials such as photoresist or non-organic materials such as silicon oxide or silicon nitride may be used as a masking material.
- a processing temperature must be taken into consideration in selecting the masking material. Further, because a masking action differs depending on materials, a full attention needs to be paid on it.
- a film of silicon oxide or silicon nitride formed by various CVD methods has many pinholes and the crystallization may advance from an unexpected section if the film is not fully thick.
- patterning is implemented after forming the coating film using those masking materials to selectively expose the surface of amorphous silicon. Then the metal film or the like which accelerates the crystallization is formed.
- the metal film or the like selectively formed is coated by the amorphous silicon film, it cannot be taken out later to adjust its amount.
- the thickness of the metal film or the like is so thin as several to several tens angstrom, so that it is difficult to form the film with a good reproducibility.
- the same also applies to the second method.
- the metal film or the like which accelerate the crystallization exists on the surface in this method. That is, a fully thick metal film is formed and a heat treatment (pre-annealing) is implemented at a temperature lower than an annealing temperature before annealing to react a part of the amorphous silicon film and the metal film and to produce silicide. Then the metal film which did not react is etched.
- pre-annealing pre-annealing
- a thickness of the silicide layer obtained is determined by the temperature and time of the heat treatment (pre-annealing) and the thickness of the metal layer has almost nothing to do with it. Due to that, the very small amount of metal element introduced in the amorphous silicon film can be controlled.
- the present invention also utilizes that there is a difference in degrees of crystallization when the surface of semiconductor is covered by a coating film (cover film) of silicon oxide or silicon nitride and when not covered when crystallizing a crystalline silicon TFT in a temperature at 450 ° to 1000° C. or preferably at 500° to 800° C. in an atmosphere containing oxygen, hydrogen or nitrogen.
- atmosphere can be an atmosphere containing oxygen, atmosphere containing hydrogen, atmosphere containing nitrogen, atmosphere containing oxygen and hydrogen, atmosphere containing oxygen and nitrogen, atmosphere containing hydrogen and nitrogen or atmosphere containing oxygen, hydrogen and nitrogen.
- the aforementioned crystallization can be carried out by (1) heating for A hours in the atmosphere containing oxygen and then heating for B hours in the atmosphere containing hydrogen: (2) heating for C hours in the atmosphere containing oxygen and then heating for D hours in the atmosphere containing nitrogen: (3) heating for E hours in the atmosphere containing hydrogen and then heating for F hours in the atmosphere containing oxygen: (4) heating for G hours in the atmosphere containing hydrogen and then heating for H hours in the atmosphere containing nitrogen: (5) heating for I hours in the atmosphere containing nitrogen and then heating for J hours in the atmosphere containing oxygen: (6) heating for K hours in the atmosphere containing nitrogen and then heating for L hours in the atmosphere containing hydrogen: (7) heating for M hours in the atmosphere containing oxygen, heating for N hours in the atmosphere containing hydrogen and then heating for P hours in the atmosphere containing nitrogen: (8) heating for Q hours in the atmosphere containing oxygen, heating for (9) hours in the atmosphere containing nitrogen and then heating for S hours in the atmosphere containing hydrogen: (9) heating for T hours in the atmosphere containing hydrogen, heating for U hours in the atmosphere containing
- This characteristic is considered to be governed by the existence of hydrogen, oxygen or nitrogen within the atmosphere infiltrated to the active layer. This crystallization may be carried out by implementing it in nitrogen for example and then in hydrogen or oxygen.
- TFTs having different characteristics may be formed on the same substrate in the same time and in the same process.
- the former high mobility TFT can be used as a driving circuit of a matrix and the latter low leak current TFTs can be used as TFTs in the matrix portion.
- a mobility in the NMOS can be relatively reduced as compare to that in the PMOS and a difference between the both can be almost eliminated in the optimum condition by not providing the cover film on the NMOS region and providing it on the PMOS region in the CMOS circuit.
- the temperature of the thermal crystallization is an important parameter and the crystallinity of a TFT is determined by the temperature in the present invention.
- the temperature of thermal annealing is restricted by a substrate and other materials.
- a thermal annealing of up to 1100° C. is possible when silicon and silica are used as a substrate.
- the annealing temperature When the annealing temperature is high, generally a growth of crystal of TFT advances, the mobility is increased and the leak current increases. Accordingly, the annealing temperature should be 450° to 1000° C. or preferably 500° to 800° C. in order to obtain TFTs having different characteristics on the same substrate like the present invention.
- One such example of the present invention is that in a display section of an active matrix circuit of a liquid crystal display or the like, polysilicon TFTs are used as switching transistors and that no cover film is provided in the active matrix region when crystallizing an active layer and on the other hand the cover film is provided on the peripheral circuit region to turn the former into low leak current TFTs and the latter into high mobility TFTs.
- FIG. 8(A) shows a conceptual drawing of a device having a display circuit section (active matrix) and a driving circuit (peripheral circuit) therefor as described above.
- a display device is shown in which a data driver 101 and gate driver 102 are arranged, an active matrix 103 having TFTs is arranged in the middle and those driver sections and the active matrix are connected through gate lines 105 and data lines 106 on an insulating substrate 107.
- the active matrix 103 is an aggregate of picture element cells 104 having a NMOS or PMOS TFT (PMOS in the figure).
- a concentration of impurities such as oxygen, nitrogen and carbon in the active layer is desirable to be less than 10 18 cm -3 or preferably less than 10 17 cm -3 in order to obtain a high mobility.
- a threshold voltage of the TFT was 0.5 to 2 V in the NMOS and -0.5 to -3 V in the PMOS for example and a mobility was 30 to 150 cm 2 /Vs in the NMOS and 20 to 100 cm 2 /Vs in the PMOS.
- an auxiliary capacity could be reduced and further be totally eliminated in the active matrix section by using single or a plurality of elements in series having as low as about 1 pA of leak current with 1 V of drain voltage.
- a second example of the present invention relates to a semiconductor memory.
- a semiconductor memory device by means of monocrystal ICs has already reached to its limit in terms of speed. Although it is necessary to increase a current capacity of transistors in order to operate it in a higher speed, it causes a further increase of power consumption and it cannot but be dealt by increasing driving voltage so long as a capacity o:F capacitors cannot be increased further for a DRAM which carries out memory operations by storing charge in the capacitors.
- a circuit arrangement of the DRAM is almost the same with that of the aforementioned liquid crystal display device in a case of 1 Tr/cell structure and in a DRAM having a structure other than that (for example 3 Tr/cell structure), no cover film is provided in a memory bit section when crystallizing an active layer and on the other hand, a cover film is provided on a region of a driving circuit because it is required to operate in fully high speed in the same manner with the case of the aforementioned liquid crystal display device to turn the former into low leak current TFTs and the later into high leak current TFTs.
- the reference numeral (101) can be a column decoder, (102) a row decoder, (103) a memory elements section, (104) a unit memory bit, (105) bit lines, (106) word lines, and (107) an (insulating) substrate.
- FIG. 8(B) shows an example of a one bit circuit of an image sensor, wherein a flip-flop circuit 108 and a buffer circuit 109 are normally constructed by a CMOS circuit and are required to respond in such high speed that they can follow up high speed pulses applied to a scan line.
- a TFT 110 in a signal output stage plays a role of a dam that discharges a charge accumulated in a capacitor by a photodiode to a data line by receiving a signal from the shift register sections 108 and 109.
- Such TFT 110 is required not only to respond in high speed but also to have less leak current. Accordingly, the region of the circuits 108 and 109 is crystallized by providing a cover film to turn it into a high mobility TFT and the region of the TFT 110 on the other hand is crystallized without providing cover film to turn it into a low leak current TFT in such a circuit.
- silicon oxide, silicon nitride or silicon oxinitride may be used as the cover film.
- the covering ability differs depending on a quality of film, typically the thickness must be more than 20 nm for a silicon oxide film and more than 10 nm for a silicon nitride film.
- the thickness is desired to be 20 to 200 nm for both of the silicon oxide film and the silicon nitride film when considering mass-producibility and reliability.
- FIGS. 1(A) to 1(C) are top views showing a process of the present embodiment (crystallization and arrangement of TFT);
- FIGS. 2(A-1), 2(A-2) and 2(B) to 2(D) are section views showing the process of the embodiment (a selectively crystallizing process)
- FIGS. 3(A) to 3(C) are section views showing the process of the embodiment (see a first embodiment);
- FIGS. 4(A) to 4(C) are section views showing the process of the embodiment (see the first embodiment);
- FIGS. 5(A) to 5(C) are section views showing the process of the embodiment (see a second embodiment);
- FIGS. 6(A) to 6(C) are section views showing the process of the embodiment (see a third embodiment).
- FIGS. 7(A) to 7(E) are section views showing the process of the embodiment (see a fourth embodiment).
- FIG. 8(A) is a block diagram showing a case when the present invention is applied to an active matrix device
- FIG. 8(B) is a circuit diagram of an exemplified circuit when the present invention is applied to a drive circuit of an image sensor;
- FIGS. 9(A) to 9(C) are section views showing the process of the embodiment.
- FIGS. 10(A) to 10(C) are section views showing the process of the embodiment.
- FIGS. 11(A) to 11(D) are section views showing the process of the embodiment.
- FIG. 2(A-1) shows the method wherein it is formed under the film
- FIG. 2(A-2) shows the method wherein it is formed on the film.
- the influence of the residual nickel may be suppressed by oxidizing nickel other than that of the island region by treating the substrate by oxygen plasma or ozone.
- a ground silicon oxide film 1B with a thickness of 2000 angstrom was formed on a substrate 1A (Coning 7059) by a plasma CVD method.
- the amorphous silicon film 1 was fabricated by a plasma CVD method or vacuum CVD method with a thickness of 200 to 3000 angstrom or preferably 500 to 1500 angstrom.
- the amorphous silicon film was readily crystallized after removing hydrogen by annealing 0.1 to 2 hours at 350° to 450° C. to keep the hydrogen concentration within the film to less than 5 atomic percent.
- the nickel film was accumulated up to a thickness of 50 to 1000 angstrom or preferably to 100 to 500 angstrom by sputtering and was patterned to form the island nickel regions 2 before forming the amorphous silicon film 1.
- the nickel film was accumulated up to 50 to 1000 angstrom or preferably to 100 to 500 angstrom by sputtering and was patterned to form the island nickel regions 2 after forming the amorphous silicon film 1.
- FIG. 1(A) shows this state seen from above.
- Each of the island nickel is a square with a side of 2 micron and an interval therebetween was set at 5 to 50 micron or 20 micron for example.
- a similar effect may be obtained by using nickel silicide instead of nickel.
- a good result could be obtained when the substrate was heated up to 100° to 500° C. or preferably to 180° to 250° C. when the nickel was to be formed. It is because an adhesion of the ground silicon oxide film with the nickel film is improved and because nickel silicide is produced by the reaction of silicon oxide and nickel.
- the same effect can be obtained by using silicon nitride, silicon carbide or silicon instead of silicon oxide.
- FIG. 2(B) shows the intermediate state of this process wherein nickel advance from the island nickel regions 2 near the edge to the center as nickel silicide 3A and portions 3 where nickel had passed have become crystal silicon. Then as shown in FIG. 2(C), the crystallizations which started from the two island nickel films hit and the nickel silicide 3A remains in the middle, thereby ending the crystallization.
- FIG. 1(B) shows the substrate in this state seen from above, wherein the nickel silicide 3A in FIG. 2(C) is an intercrystalline boundary 4.
- the nickel silicide 3A in FIG. 2(C) is an intercrystalline boundary 4.
- Crystal silicon can be obtained by the aforementioned process, but it is not desirable for nickel to diffuse within the semiconductor coating film from the nickel silicide 3A produced at this time. Accordingly, it is desirable to eliminate the region where nickel is highly concentrated by etching by hydrofluoric acid or hydrochloric acid. By the way, because an etching rate of the nickel and nickel silicide is fully large, the silicon film is not affected in the etching by means of hydrofluoric acid or hydrochloric acid. The regions where the growing point of nickel had been located were removed together in the same time.
- FIG. 2(D) shows the state after the etching. The portion where there was the intercrystalline boundary turns out to be a groove 4A.
- TFT semiconductor regions (active layer or the like) of a TFT so as to pinch this groove.
- the TFT was arranged so that semiconductor regions 6 would not cross the intercrystalline boundary 4 as shown in FIG. 1(C). That is, the TFT was formed in a crystal growth region in the horizontal direction parallel to the substrate, not in the thickness direction of the coating film, by the action of nickel. Then, the growth direction of the crystal could be uniformly arranged and residual nickel could be minimized. As a result, a high TFT characteristics could be obtained.
- gate wires 7 may cross the intercrystalline boundaries 4.
- FIGS. 3 and 4 show examples of the method for fabricating a TFT using the crystal silicon obtained in the process described above.
- the reference character X in the middle indicates the place where there was the groove 4A in FIG. 2.
- island semiconductor regions 11a and 11b were formed by patterning the crystal silicon film 3 obtained in the process shown in FIG. 2.
- a silicon oxide film 12 which functions as a gate insulating film was formed by such methods as RF plasma CVD, ECR plasma CVD or sputtering.
- gate electrodes 13a and 13b were formed by forming a polycrystalline silicon film with a thickness of 3000 to 6000 angstrom in which 1 ⁇ 10 20 to 5 ⁇ 10 20 cm -3 of phosphorus is doped by a vacuum CVD method and then by patterning it (FIG. 3(A)).
- impurity was doped by a plasma doping method.
- phosphine PH 3
- diborane B 2 H 6
- the figure shows the N type TFT.
- An acceleration voltage was 80 keV for phosphine and 65 keV for diborane.
- the impurity was activated by annealing for four hours at 550° C. to form impurity regions 14a through 14d.
- a method of using optical energy such as laser annealing or flash lamp annealing may be also used for the activation (FIG. 3(B)).
- a silicon oxide film with a thickness of 5000 angstrom was deposited as an interlayer insulator 15 similarly to a case when TFT is normally fabricated, and contact holes were formed therethrough to form wires and electrodes 16a through 16d in source and drain regions (FIG. 3(C)).
- the TFT (N channel type in the figure) was thus fabricated in the process described above.
- the field effect mobility of the TFT obtained was 40 to 60 cm 2 /Vs in the N channel type and 30 to 50 cm 2 /Vs in the P channel type.
- FIG. 4 shows a process how a TFT for aluminum gate was fabricated.
- the reference character X in the middle indicates the place where there was the groove 4A in FIG. 2.
- island semiconductor regions 21a and 21b were formed buy patterning the crystal silicon film 3 obtained in the process shown in FIG. 2.
- a silicon oxide film 22 which functions as a gate insulating film was formed by such methods as RF plasma CVD, ECR plasma CVD or sputtering.
- TEOS tetra-ethoxi-silane
- oxygen as original gases.
- an aluminum film (5000 angstrom thick) containing 1% of silicon was deposited by sputtering and was patterned to form gate wires and electrodes 23a and 23b.
- anodic oxidation was implemented by setting platinum as a cathode and an aluminum wire as an anode and by flowing current therebetween.
- the current was applied so that its voltage would increase 2V/min. initially and the voltage was fixed when it reached to 220 V.
- the current was stopped when it became less than 10 microA/m 2 .
- anode oxides 24a and 24b with a thickness of 2000 angstrom were formed as shown in FIG. 4(A).
- impurity was doped by a plasma doping method.
- phosphine PH 3
- diborane B 2 H 6
- the figure shows the N type TFT.
- An acceleration voltage was 80 keV for phosphine and 65 keV for diborane.
- the impurity was activated by annealing by laser to form impurity regions 25a through 25d.
- the laser used was a KrF laser (wavelength: 248 nanometer) and five shots of laser lights having 250 to 300 mJ/cm 2 of energy density were irradiated (FIG. 4(B)).
- a silicon oxide film with a thickness of 5000 angstrom was deposited as an interlayer insulator 26 similarly to the case when TFT is normally fabricated and contact holes were formed therethrough to form wires and electrodes 27a through 27d in source and drain regions (FIG. 4(C)).
- the field effect mobility of the TFT obtained was 60 to 120 cm 2 /Vs in the N channel type and 50 to 90 cm 2 /Vs in the P channel type TFT.
- a shift register fabricated by using this TFT operations at 6 MHz in 17 volts of drain voltage and at 11 MHz in 20 V were confirmed.
- FIG. 5 shows a case when a TFT for an aluminum gate was fabricated similarly to that shown in FIG. 4.
- the amorphous silicon was used as an active layer in this embodiment;
- a ground silicon oxide film 32 was deposited on a substrate 31 and an amorphous silicon film 33 with a thickness of 2000 to 3000 angstrom was deposited further on that.
- An adequate amount of P type or N type impurities may be mixed in the amorphous silicon film.
- island nickel or nickel silicide coating film 34A and 34B were formed as described above and the amorphous silicon film was crystallized by growing laterally by annealing for 8 hours at 550° C. or for four hours at 600° C. in this state.
- a coating film was formed by such substances as silicon nitride and silicon oxide as a gate insulating film 37.
- a gate electrode 38 was formed by aluminum and an anodic oxidation was implemented in the same manner with the case of FIG. 4.
- impurity was diffused by an ion doping method to form impurity regions 39A and 39B.
- the TFT was completed by depositing further an interlayer insulator 40, by forming contact holes and forming metallic electrodes 41A and 41B at source and drain regions.
- This TFT is characterized in that the semiconductor film at the source and drain portions is thick and that a resistance thereof is small. As a result, a resistance in the source and drain regions is reduced and the characteristics of the TFT is improved. Further, contact holes can be readily formed.
- FIG. 6 shows a process when a CMOS type TFT was fabricated.
- a ground silicon oxide film 52 was deposited on a substrate 51 and an amorphous silicon film 53 with a thickness of 1000 to 1500 angstrom was deposited further on that.
- island nickel or nickel silicide coating film 54 was formed and annealing was implemented in this state at 550° C.
- a silicon silicide region 55 moved in the direction of plane, not in the direction of thickness, of the coating film and the crystallization advances by this process.
- the amorphous silicon film changed into crystal silicon as shown in FIG. 6(B) by four hours of annealing.
- the silicon silicide regions 59A and 59B were driven away toward the edge along the advancement of the crystallization.
- an island silicon region 56 was formed by patterning the crystal silicon film thus obtained as shown in FIG. 6(B).
- a gate insulating film 57 and gate electrodes 58A and 58B were formed.
- N type impurity regions 60A and P type impurity regions 60B were formed by diffusing an impurity by an ion doping method as shown in FIG. 6(C).
- the doping can be carried out by using phosphorus as a N type impurity (doping gas is phosphine PH 3 ) and by doping across the whole surface by 60 to 110 kV of acceleration voltage and then after covering the region of the N channel type TFT by a photoresist, by using boron for example as a P type impurity (doping gas is diborane B 2 H 6 ) and by doping with 40 to 80 kV of acceleration voltage.
- the source and drain region were activated by irradiating laser light similarly to the case in FIG. 4. Then the TFT was completed by depositing further an interlayer insulator 61, by forming contact holes and forming metallic electrodes 62A, 62B and 62C at the source and drain regions.
- FIG. 7 shows the fourth embodiment.
- the present embodiment relates to a method in which silicide is produced by reacting a nickel film with a portion of amorphous silicon film by a first heat treatment (pre-annealing) and the amorphous silicon is crystallized by annealing after removing a non-reactive nickel film.
- a ground silicon oxide film 702 (thickness: 2000 angstrom) was formed on a substrate (Coning No. 7059) 701 by a sputtering method. Then a silicon film 703 with a thickness of 300 to 800 angstrom or 500 angstrom thick for example was formed. Further, a silicon oxide film 704 was formed by a plasma CVD method. This silicon oxide film 704 acts as a masking material and its thickness was preferred to be 500 to 2000 angstrom. If it is too thin, the crystallization advances from an unexpected location by pinholes and if it is too thick, it takes a time to form the film and is not suited for mass-production. Then it was set at 1000 angstrom here.
- the silicon oxide film 704 was patterned by a known photolithographic process. Then a nickel film 705 (thickness: 500 angstrom) was formed by a sputtering method. The thickness of the nickel film 705 was preferred to be more than 100 angstrom (FIG. 7(A)).
- a pre-annealing process For example, it was annealed for 20 minutes at 450° C.
- a nickel silicide layer 708 was formed within the amorphous silicon. A thickness of this layer was determined by a temperature and time of the pre-annealing and the thickness of the nickel film 705 was almost nothing to do with it (FIG. 7(B)).
- Nitric or hydrochloric solution was suitable for the etching.
- the nickel silicide layer was barely etched during the etching of the nickel film by those etchants.
- After removing the nickel film, it was annealed for 4 to 8 hours at 550° C. (a crystallizing annealing process).
- a first method was to implement this process while remaining the masking material 704 as shown in FIG. 7(C). The crystallization advances as indicated by arrows in FIG. 7(C).
- a second method was to anneal after removing all the masking material and exposing the silicon film.
- a third method was to anneal after removing the masking material and after forming a new coating film 707 composed of silicon oxide or silicon nitride on the surface of silicon film as a protection film as shown in FIG. 7 (D).
- the first method was simple, the surface of the masking material 704 reacted with nickel in the pre-annealing step, and became silicate in the crystallizing annealing process at a higher temperature, and became hard to be etched. That is, because an etching rate of the silicon film and masking material 704 becomes almost equal, the portion where the silicon film is exposed is also largely etched when the masking material is removed later, creating steps on the substrate.
- the second method is very simple and etching can be easily carried out since the reaction of the masking material with nickel is mild before the crystallizing annealing process. However, because the silicon surface was wholly exposed when the crystallizing annealing was carried out, characteristics of TFT or the like fabricated later degraded.
- the third method allowed to firmly obtain a good quality crystal silicon film, it was complicated because the number of processes was increased.
- a fourth method which was an improved version of the third method, a method comprising steps of putting into a furnace in a state when the silicon surface is exposed, heating for about one hour at 500° to 550° C. initially in an oxygen flow to form a thin silicon oxide film with a thickness of 20 to 60 angstrom thick on the surface and switching to a nitrogen flow as it is was studied as a crystallizing annealing condition. According to this method, an oxide film was formed in the initial stage of the crystallization.
- the crystal silicon film was thus obtained. Since then, the silicon film 703 was patterned while removing a portion where a value of concentration of nickel was high (a region where the origin of growth was located) and growth points (slanted portions at the end of the arrows in the figure) and while remaining only the region where the concentration of nickel was low. An island silicon region 708 which would be used for an active layer of the TFT was formed as described above. Then a gate insulating film 709 composed of silicon oxide with a thickness of 1200 angstrom was formed covering the region 708 by a plasma CVD method.
- a gate electrode 710 and a wire 711 in a first layer were formed by a phosphorus doped silicon film with a thickness of 6000 angstrom and source/drain regions 712 were formed by injecting an impurity into the active layer 708 in a self-aligning manner using the gate electrode 710 as a mask. It was then effective for improving the crystallinity to irradiate visible or near infrared strong light. Further, a silicon oxide film with a thickness of 6000 angstrom was formed by a plasma CVD method as an interlayer insulator 713.
- FIG. 9 shows the present embodiment.
- a polysilicon TFT is formed in a peripheral circuit and an active matrix region of a TFT type liquid crystal display device.
- a ground oxide film 121 was deposited into a thickness of 20 to 200 nm by a sputtering method on a glass substrate 120 having a heat resisting quality such as a silica glass. Further on that, an amorphous silicon film was deposited into a thickness of 30 to 50 nm by a plasma CVD method or vacuum CVD method using mono-silane or di-silane as an original material.
- a concentration of oxygen or nitrogen in the amorphous silicon film should have been less than 10 18 cm -2 or preferably less than 10 17 cm -2 . The oxygen concentration was set to be less than 10 17 cm -2 in the present embodiment.
- a silicon oxide film with a thickness of 100 to 150 nm or silicon nitride film with a thickness of 30 to 100 nm was formed on the amorphous silicon film by a sputtering method as a cover film. It was then patterned to leave a cover film 122 only in the peripheral circuit region. Then it was crystallized by leaving for 4 to 100 hours in an argon or nitrogen atmosphere (600° C.) containing 20 to 100 volume percent of oxygen or hydrogen. As a result, a crystallinity of a silicon film 123A in the peripheral circuit region was good and that of a silicon film 123B in the picture element region was not good.
- FIG. 9(A) shows this state.
- a gate oxide film 125 was formed by means of sputtering or the like. It can be formed by a plasma CVD method using TEOS (tetraethoxisilane) instead of the sputtering method. It is desirable to anneal for 0.5 to 3 hours at a temperature more than 650° C. during or after the formation when forming the film using TEOS.
- TEOS tetraethoxisilane
- a N-type silicon film with a thickness of 200 nm to 2 micron was formed by a LPCVD method and by patterning it, gate electrodes 126A through 126C were formed on each island region.
- a metallic material having a relatively good heat resistance such as tantalum, chrome, titanium, tungsten and molybdenum may be used instead of the N-type silicon film.
- an impurity was injected to the island silicon film of each TFT by an ion doping method in a self-aligning manner using the gate electrode section as a mask.
- phosphorus was injected across the whole surface employing phosphine (PH 3 ) as a doping gas at first and after covering the right side of the island region 124A and the matrix region in the figure by a photoresist, boron was injected to the left side of the island region 124A employing diborane (B 2 H 6 ) as a doping gas.
- the dosage of phosphorus was set to be 20 to 8 ⁇ 10 15 cm -2 and that of boron was 4 to 10 ⁇ 10 15 cm -2 so that the dosage of boron would exceed that of phosphorus.
- a P-type region 127A and N-type regions 127B and 127C were thus created.
- This process can be implemented by laser annealing. Because a thermal damage on the substrate is small when annealed by laser, a normal non-alkaline glass such as Coning 7059 can be used. Further, at that time, a material having an inferior heat resistance such as aluminum can be used as a material for the gate electrode.
- the P-type region 127A and N-type regions 127B and 127C were created by the process described above. A sheet resistance of those regions was 200 to 800 ohm/sheet.
- a silicon oxide film with a thickness of 300 to 1000 nm was formed across the whole surface by a sputtering method as an interlayer insulator 128.
- This may be a silicon oxide film formed by a plasma CVD method.
- a silicon oxide film having a good step coverage can be obtained by the plasma CVD method especially using TEOS as an original material.
- FIG. 9(C) shows that an inverter circuit have been created by the NTFT and PTFT on the left side.
- the wires 130A through 130E may be a multi-layered wire with aluminum based on chrome or titanium nitride in order to reduce a sheet resistance.
- it was annealed for 0.5 to 2 hours at a temperature between 200° and 350° C. in hydrogen to reduce a dangling bond of the silicon active layer.
- the peripheral circuit and the active matrix circuit could be integrally created.
- a typical mobility was 80 cm 2 /Vs in the NMOS, 50 cm 2 /Vs in the PMOS in the peripheral circuit section and 5 to 30 cm 2 /Vs in the picture element TFT (NMOS).
- FIG. 10 shows the present embodiment.
- a difference of mobility of NMOS and PMOS is reduced in a CMOS circuit utilizing the present invention.
- a ground oxide film 132 was deposited into a thickness of 20 to 200 nm by a sputtering method on a Coning 7059 substrate 131.
- an amorphous silicon film was deposited into a thickness of 50 to 250 nm by a plasma CVD method or vacuum CVD method using mono-silane or di-silane as an original material.
- a concentration of oxygen or nitrogen in the amorphous silicon film should have been less than 10 18 cm -2 or preferably less than 10 17 cm -2 .
- the vacuum CVD method was suited for this purpose.
- the oxygen concentration was set to be less than 10 17 cm -2 in the present embodiment.
- a cover film 133 (a silicon oxide film with a thickness of 50 to 150 nm) was provided on the region of PMOS. Then it was crystallized by annealing for 4 to 100 hours at 600° C. in an argon or nitrogen atmosphere at 600° C. containing more than 50 percent of oxygen or hydrogen. As a result, although a crystallinity of a region 134A under the cover film was good, that of a region 134B where there was no cover film was not good. FIG. 10(A) shows this state.
- the silicon film was patterned into a shape of island to form a PMOS region 135A and an NMOS region 135B as shown in FIG. 10(B). Then a silicon oxide film 125 with a thickness of 50 to 150 nm was formed by a sputtering method covering those island regions as a gate insulating film 136. Then an aluminum film was formed with a thickness of 200 nm to 2 micron by a sputtering method, and patterned to form a gate electrode. An anodic oxide film was formed on the upper and side surfaces of the gate electrode by feeding power to it in an electrolyte. Gate electrode sections 137A and 137B were formed on each island region by the process described above.
- an impurity was injected to the island silicon film of each TFT by an ion doping method in a self-aligning manner using the gate electrode section as a mask.
- phosphorus was injected across the whole surface employing phosphine (PH 3 ) as a doping gas at first and after covering only the island region 135B in the figure by a photoresist, boron was injected to the island region 135A employing diborane (B 2 H 6 ) as a doping gas.
- the dosage of phosphorus was set to be 2 to 8 ⁇ 10 15 cm -2 and that of boron to be 4 to 10 ⁇ 10 15 cm -2 so that the dosage of boron would exceed that of phosphorus.
- the crystallinity of the silicon film is broken by the doping process, it was possible to keep its sheet resistance around 1 kohm/sheet. However, if the sheet resistance of this degree is to much, the sheet resistance can be lowered by annealing further for 2 to 24 hours at 600° C. The same effect can be obtained by irradiating such a strong light as laser light.
- a P-type region 138A and N-type regions 138B were thus created.
- a sheet resistance of those regions was 200 to 800 ohm/sheet.
- a silicon oxide film with a thickness of 300 to 1000 nm was formed across the whole surface by a sputtering method as an interlayer insulator 139.
- This may be a silicon oxide film formed by a plasma CVD method.
- a silicon oxide film having a good step coverage can be obtained by the plasma CVD method especially using TEOS as an original material.
- FIG. 11 shows the present embodiment.
- the present embodiment relates to a circuit in which a transistor and silicon resistance are combined. Silicon doped by impurity can be used as a protecting circuit of the transistor.
- a ground oxide film 141 was deposited into a thickness of 20 to 200 nm by a sputtering method on a Coning 7059 substrate 140.
- an amorphous silicon film 142 was deposited into a thickness of 100 to 250 nm by a plasma CVD method or vacuum CVD method using mono-silane or di-silane as an original material.
- a concentration of oxygen or nitrogen in the amorphous silicon film should have been less than 10 18 cm -2 or preferably less than 10 17 cm -2 .
- a cover film 143 of a silicon oxide film with a thickness of 20 to 200 nm was deposited and it was crystallized by annealing for 4 to 100 hours in an argon or nitrogen atmosphere at 600° C.
- FIG. 11(A) shows this state.
- the silicon film was patterned into a shape of island to form a transistor region 144A and a resistance region 144B as shown in FIG. 11(B). Then a silicon oxide film with a thickness of 50 to 150 nm was formed by a sputtering method covering those island regions as a gate insulating film 145. Then an aluminum film was formed with a thickness of 200 nm to 2 micron by a sputtering method, and patterned to form a gate electrode. An anode oxide film was formed on the upper and side surfaces of the gate electrode by feeding power to it in an electrolyte. Gate electrode section 146 was formed on each island region by tile process described above.
- an impurity e.g. phosphorus
- an impurity e.g. phosphorus
- the dosage of phosphorus was 2 to 8 ⁇ 10 15 cm -2 .
- Impurity regions 147A and 147B were created by the doping process described above. Since the same amount of impurity is being injected in those two impurity regions, they show the same resistivity when they are thermally annealed as they are. However, there is a such case for example when a higher resistance is demanded to the latter whereas a lower resistance is always demanded to the former. Then, a cover film 148 of a silicon oxide film with a thickness of 50 to 150 nm was formed only on the transistor region as shown in FIG. 11(C). It was then annealed for 4 to 20 hours at a temperature between 550 ° and 650° in an argon or nitrogen atmosphere containing more than 50 volume percent of oxygen or hydrogen.
- Phosphine (PH 3 ) may be used instead of oxygen or hydrogen.
- the annealing temperature is preferable to be less than 800° C. because if the annealing temperature is too high, phosphine is thermally decomposed and diffuses within the semiconductor, lowering the resistivity on the contrary.
- Diborane (B 2 H 6 ) may be used when the impurity region of the resistance is P-type.
- a sheet resistance of the impurity region of the transistor was 20 to 800 ohm/sheet, that of the impurity region of the resistance was 2 k to 100 kohm/sheet by the process above.
- a silicon oxide film with a thickness of 300 to 1000 nm was formed across the whole surface by a sputtering method as an interlayer insulator 149.
- This may be a silicon oxide film formed by a plasma CVD method.
- a silicon oxide film having a good step coverage can be obtained by the plasma CVD method especially using TEOS as an original material.
- the present invention is an epoch-making invention in a sense that it promotes the implementation of lower temperature and shorter time crystallization of amorphous silicon and provides an immeasurable benefit to the industry because facility, equipment and technique therefor are very common and are excellent for mass-production.
- the same process can be applied to another metal element that accelerates the crystallization, i.e. any one of Fe, Co, Ru, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag.
- the present invention allows to reduce the number of the annealing furnaces to less than 1/6 of that because the annealing time can be shortened to four hours or less.
- the improvement of productivity and the reduction of amount of investment on facility brought about by that will lead to the drop of substrate processing cost as well as to the drop of a cost of TFTs and thereby to the rise of new demand. Accordingly, the present invention is very beneficial to the industry and deserves to be patented.
- the present invention solves the problem in the conventional fabrication process of crystalline silicon TFTs by such minimum modification of the crystallization condition of active layer of the TFTs that whether a cover film exists or not.
- the present invention allowed to improve especially a reliability and performance of a dynamic circuit and of a device having such circuit.
- crystalline silicon TFTs had low an ON/OFF ratio for such purpose as an active matrix of a liquid crystal display and was difficult in various ways to put it into practical use, such problems have been considered to be solved by the present invention.
- the present invention will be effective, when implemented, in TFTs used as means for implementing a stereo-monocrystal semiconductor integrated circuit.
- a memory elements section can be constructed by constructing a peripheral logic circuit by semiconductor circuits on a monocrystal semiconductor and by providing TFTs on that through the intermediary of an interlayer insulator.
- the memory elements section can be a DRAM circuit using the TFTs of the present invention and its driving circuit is constructed by being CMOS-implemented to the monocrystal semiconductor circuit.
- CMOS-implemented to the monocrystal semiconductor circuit when such circuit is used for a microprocessor, its area can be saved because the memory section is raised to the upstairs.
- the present invention is considered to be a very beneficial invention to the industry.
Abstract
Description
Claims (27)
Priority Applications (13)
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US08/248,220 US5604360A (en) | 1992-12-04 | 1994-05-24 | Semiconductor device including a plurality of thin film transistors at least some of which have a crystalline silicon film crystal-grown substantially in parallel to the surface of a substrate for the transistor |
US08/341,106 US5563426A (en) | 1992-12-04 | 1994-11-18 | Thin film transistor |
US08/661,013 US5888857A (en) | 1992-12-04 | 1996-06-10 | Semiconductor device and method for manufacturing the same |
US08/670,122 US6413805B1 (en) | 1993-03-12 | 1996-06-25 | Semiconductor device forming method |
US08/688,229 US6479331B1 (en) | 1993-06-30 | 1996-07-29 | Method of fabricating a semiconductor device |
US08/709,111 US6140165A (en) | 1993-03-12 | 1996-09-06 | Semiconductor device forming method |
US09/233,146 US6323071B1 (en) | 1992-12-04 | 1999-01-19 | Method for forming a semiconductor device |
US09/439,997 US6338991B1 (en) | 1992-12-04 | 1999-11-15 | Semiconductor device and method for manufacturing the same |
US09/993,492 US6806125B2 (en) | 1992-12-04 | 2001-11-27 | Method of manufacturing a thin film transistor device |
US10/254,546 US6872605B2 (en) | 1992-12-04 | 2002-09-26 | Semiconductor device and method of fabricating the same |
US10/926,059 US7622335B2 (en) | 1992-12-04 | 2004-08-26 | Method for manufacturing a thin film transistor device |
US12/579,642 US8062935B2 (en) | 1992-12-04 | 2009-10-15 | Semiconductor device and method for manufacturing the same |
US13/282,515 US8278660B2 (en) | 1992-12-04 | 2011-10-27 | Semiconductor device and method for manufacturing the same |
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JP35054592 | 1992-12-04 | ||
JP4-350545 | 1992-12-04 | ||
JP5204775A JP2852853B2 (en) | 1993-07-27 | 1993-07-27 | Method for manufacturing semiconductor device |
JP5-204775 | 1993-07-27 | ||
JP29894493 | 1993-11-04 |
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US08/248,220 Continuation-In-Part US5604360A (en) | 1992-12-04 | 1994-05-24 | Semiconductor device including a plurality of thin film transistors at least some of which have a crystalline silicon film crystal-grown substantially in parallel to the surface of a substrate for the transistor |
US08/266,712 Continuation-In-Part US5403762A (en) | 1992-12-04 | 1994-06-28 | Method of fabricating a TFT |
US08/341,106 Division US5563426A (en) | 1992-12-04 | 1994-11-18 | Thin film transistor |
US36574394A Division | 1992-12-04 | 1994-12-29 |
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US08/341,106 Expired - Lifetime US5563426A (en) | 1992-12-04 | 1994-11-18 | Thin film transistor |
US08/661,013 Expired - Lifetime US5888857A (en) | 1992-12-04 | 1996-06-10 | Semiconductor device and method for manufacturing the same |
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US08/661,013 Expired - Lifetime US5888857A (en) | 1992-12-04 | 1996-06-10 | Semiconductor device and method for manufacturing the same |
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Publication number | Publication date |
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CN1091943C (en) | 2002-10-02 |
CN1299331C (en) | 2007-02-07 |
US5888857A (en) | 1999-03-30 |
CN1052570C (en) | 2000-05-17 |
CN1348199A (en) | 2002-05-08 |
CN1090426A (en) | 1994-08-03 |
CN1285611A (en) | 2001-02-28 |
CN100437907C (en) | 2008-11-26 |
TW226478B (en) | 1994-07-11 |
CN1152792A (en) | 1997-06-25 |
US5563426A (en) | 1996-10-08 |
CN1658389A (en) | 2005-08-24 |
KR970004450B1 (en) | 1997-03-27 |
CN1658389B (en) | 2010-12-29 |
CN1149634C (en) | 2004-05-12 |
CN1599030A (en) | 2005-03-23 |
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