US5506396A - Microcomputer for IC card - Google Patents

Microcomputer for IC card Download PDF

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Publication number
US5506396A
US5506396A US08/193,460 US19346094A US5506396A US 5506396 A US5506396 A US 5506396A US 19346094 A US19346094 A US 19346094A US 5506396 A US5506396 A US 5506396A
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test
data
burn
microcomputer
routine
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US08/193,460
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Kazuo Asami
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/355—Personalisation of cards for use
    • G06Q20/3558—Preliminary personalisation for transfer to user

Definitions

  • This invention relates to a microcomputer for an IC card and, more particularly, to a microcomputer including a user program for performing various processes and a test program for performing a test (a product test) of the microcomputer.
  • test program performs a product test to which the microcomputer is subjected, the test program giving access to any arbitrary address of all regions of the microcomputer to perform the function test satisfactorily.
  • the test program is usually used by a manufacturer (of the microcomputer) or an issuer, and execution of the test program and access to the same must be secured by means of collation of passwords or the like after shipment of the IC card in order to prevent abuse of the test program, e.g., giving access to a region of another person's program for copying or falsifying data.
  • FIG. 13 is a functional block diagram of a conventional microcomputer for an IC card of the foregoing type.
  • reference numeral 1 represents a microcomputer for an IC card (hereinafter called a microcomputer for a card)
  • 2 represents a CPU for processing data
  • 3 represents a mask ROM, a nonvolatile memory in which a variety of programs are stored
  • 4 represents a RAM, a volatile memory for temporarily storing data
  • 5 represents an input/output control circuit for controlling data input to and output from an external device.
  • Reference numeral 6 represents an EEPROM, a write-enable nonvolatile memory for storing data of the results of a process or the like
  • 7 represents a bus mutually connecting the foregoing elements.
  • Reference numeral 8 represents a power source terminal (a Vcc terminal), 9 represents a ground terminal (a GND terminal), 10 represents a reset terminal (an RST terminal), 11 represents a clock terminal (a CLK terminal) and 12 represents an input/output terminal (an I/O terminal).
  • the foregoing terminals form a terminal group for establishing electrical contact with an external device.
  • FIG. 14 is a flow chart of the operation of the conventional microcomputer for a card.
  • FIGS. 15A and 15B illustrate memory maps for the conventional microcomputer for a card.
  • FIG. 15A illustrates a memory map for executing the user program
  • FIG. 15B is a memory map for executing the test program.
  • a branch routine 34 is performed in step S2 shown in FIG. 14.
  • a user program 31, a test program 32, and a burn-in test program 33 are respectively performed in a user mode (step S3), a test mode (step S5), and a burn-in mode (step S6).
  • a password confirmation routine 35 is performed in a password confirmation routine (step S4).
  • Reference numeral 61 represents a test EEPROM that cannot be accessed from the user mode.
  • the test EEPROM region 61 is realized by using a means for limiting addresses to prevent access thereto in, for example, the user mode.
  • the detailed structure of the test EEPROM region has been disclosed in Japanese Published Patent Application 2-293196.
  • the password confirmation routine 35 a password to be subjected to a collation with a key code supplied from outside is stored in the test EEPROM region 61. Referring to FIGS. 15A and 15B, the EEPROM 6 and the test EEPROM region 61 are stored in the EEPROM 6, while the branch routine 34, the password confirmation routine 35, the user program 31, the test program 32, and the burn-in test program 33 are stored in the mask ROM 3.
  • the microcomputer 1 for an IC card is connected to an external device at the Vcc terminal 8, the GND terminal 9, the RST terminal 10, the CLK terminal 11, and the I/O terminal 12.
  • the CPU 2 executes the branch routine 34 previously stored at a predetermined address in the mask ROM 3 (step S2).
  • the branch routine 34 causes branching to the user mode to take place if a user mode execution command has been supplied through the I/O terminal 12 (step S3).
  • serial data supplied from outside is serial/parallel converted by the input/output control circuit 5, the parallel data being then received by the CPU 2 through the bus 7.
  • the CPU 2 processes the data in accordance with the user program 31 so that data that must be temporarily stored is stored in the RAM 4.
  • Data to be transmitted outside is parallel/serial converted by the input/output control circuit 5 and the serial data being transferred outside through the I/O terminal 12 (step S3).
  • step S5 branching to the test mode (step S5) takes place.
  • the password confirmation routine 35 step S4 is performed in order to prevent access to the foregoing test program 32.
  • the key code supplied through the I/O terminal 12 and the password previously stored in the test EEPROM region 61 in the EEPROM 6 are collated with each other. If they agree, branching to the test mode (step S5) is permitted so that the test is performed in accordance with the test program 32.
  • the test program 32 accesses any arbitrary address so that the CPU 2 gives access to each address in accordance with the test program 32 to perform the product test. If the key code and the password do not agree in the password confirmation routine 35 (step S4), branching to the test mode (step S5) cannot be performed and, therefore, the operation of the microcomputer for an IC card is stopped.
  • step S6 branching to the burn-in mode (step S6) takes place so that the CPU 2 performs any one of a burn-in test selected from a group consisting of a read-only burn-in test, a write burn-in test, and a dummy write burn-in test by selecting a mode in accordance with the burn-in test program 33.
  • the test program can be performed even after the shipment if the test mode execution command has been supplied in the branch routine and if the key code supplied from outside and the password agree by chance in the password confirmation routine. In this case, there arises a problem in that access to data of another person can be obtained through the test program and, therefore, the data can be copied or falsified.
  • the burn-in test program having access to any arbitrary address in all regions of the microcomputer is provided with no security means against the execution of and access to the burn-in test program. Therefore, branching to the burn-in test program can easily be performed simply by inputting a burn-in mode execution command in the branch routine, causing a problem in that access to data of another person can be given through the burn-in test program.
  • the present invention is directed to overcoming the foregoing problems and, therefore, an object is to produce a reliable microcomputer for an IC card in which branching is limited to a user mode after the microcomputer has been shipped to a user.
  • a microcomputer for an IC card comprising a mask ROM storing a user program, a test program and a branch routine for selectively branching to the programs in accordance with an execution command branch; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the mask ROM includes a shipment confirmation routine performed before the branch routine is performed, the test EEPROM region includes a region in which shipment data representing that the microcomputer has been shipped is written, and branching to the user program takes place without exception if confirmation has been made in the shipment confirmation routine that the shipment data has been written in the test EEPROM region.
  • a microcomputer for an IC card comprising a mask ROM storing a user program, a test program and a branch routine for selectively branching to the programs in accordance with an execution command; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the terminal group includes a power source terminal, the microcomputer comprises voltage detection means for detecting whether the power supply voltage at the power source terminal has decreased, the mask ROM includes, before the branch routine, a shipment confirmation routine and a voltage detection routine for detecting the power supply voltage of the power source terminal before or after the shipment confirmation routine has been performed, the test EEPROM region includes a region in which shipment data representing that the microcomputer
  • a microcomputer for an IC card comprising a mask ROM storing a user program, a test program, a burn-in test program and a branch routine for selectively branching to the programs in accordance with an execution command; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the mask ROM includes a burn-in data confirmation routine performed before branching to the burn-in test program takes place, the test EEPROM region includes a region in which burn-in data for previously declaring that the burn-in test program has been executed is written, and branching to the burn-in test program takes place without exception if the burn-in data has not been written in the test
  • a microcomputer for an IC card comprising a mask ROM storing a user program, a test program, a burn-in test program having a plurality of modes and a branch routine for selectively branching to the programs in accordance with an execution command; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the terminal group includes an input/output terminal, and the burn-in test program includes a discrimination signal output step in which a mode discrimination signal representing the mode, among the plurality of the modes, which is being executed, is transmitted through the input/output terminal.
  • a microcomputer for an IC card according to the invention is arranged in so that the shipment confirmation routine is performed before the branch routine is performed. Therefore, branching in the shipment confirmation routine is limited only to the user mode after the microcomputer for an IC card having the shipment data written in the test EEPROM region has been shipped.
  • a microcomputer for an IC card according to the invention also includes voltage detection means and a voltage detection routine. Therefore, even if branching to the user mode is performed in the shipment confirmation routine, branching to the user mode is performed in the voltage detection routine when a reduction in the power supply voltage has been detected.
  • a microcomputer for an IC card according to the invention includes a burn-in data confirmation routine performed prior to branching to the burn-in test program. Therefore, the burn-in test program cannot be performed if the burn-in data has not been written on the test EEPROM region. As a result, execution of the burn-in test in accordance with an erroneous execution command is prevented. Therefore, unauthorized execution and access to the burn-in test program can be prevented.
  • a microcomputer for an IC card according to the invention includes the burn-in test program having a discrimination signal output step in which a mode discrimination signal representing the mode which is being executed is transmitted to the outside through the input/output terminal. Therefore, the current burn-in mode can be detected from outside the microcomputer.
  • FIG. 1 is a block diagram that illustrates the functions of a microcomputer for an IC card according to the present invention
  • FIG. 2 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention
  • FIG. 3 illustrates a memory map for use at the time of executing a test program in a microcomputer for an IC card according to the present invention
  • FIG. 4 is a block diagram that illustrates the functions of a microcomputer for an IC card according to the present invention
  • FIG. 5 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention
  • FIG. 6 illustrates a memory map for use at the time of executing a test program in a microcomputer for an IC card according to the present invention
  • FIG. 7 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention.
  • FIG. 8 illustrates a memory map for use at the time of executing a test program in a microcomputer for an IC card according to the present invention
  • FIG. 9 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention.
  • FIG. 10 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention.
  • FIG. 11 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention.
  • FIG. 12 illustrates a memory map for use at the time of executing a test program in the microcomputer for an IC card shown in FIG. 11;
  • FIG. 13 is a functional block diagram that illustrates the functions of a conventional microcomputer for an IC card
  • FIG. 14 is a flow chart that illustrates the operation of the conventional microcomputer for an IC card
  • FIG. 15A illustrates a memory map for use at the time of executing a test program in the conventional microcomputer for an IC card
  • FIG. 15B is a view that illustrates a memory map for use at the time of executing a test program in the conventional microcomputer for an IC card.
  • FIG. 1 is a functional block diagram that illustrates a microcomputer for an IC card according to the present invention.
  • FIG. 2 is a flow chart that illustrates the operation of the microcomputer for an IC card shown in FIG. 1.
  • FIG. 3 illustrates a memory map for use at the time of executing a test program in the microcomputer for an IC card shown in FIG. 1.
  • the elements of the microcomputer 1a for an IC card that are the same or correspond to those of the conventional microcomputer are given the same reference numerals and their descriptions are omitted here.
  • a mask ROM 3a contains the conventional user program 31, the test program 32, the burn-in test program 33, the branch routine 34, the password confirmation routine 35, and a shipment confirmation routine 36 shown in FIG. 3.
  • the EEPROM region 61 of the EEPROM 6a shown in FIG. 3 includes shipment data 612 to be used in the shipment confirmation routine 36 as well as a password code 611 for use in the password confirmation routine 35.
  • a test mode (step S6) is commenced to execute the test program 32 so that the arbitrary shipment data 612 is written on the test EEPROM region 61.
  • the microcomputer 1a for an IC card or the IC card including the foregoing microcomputer is shipped.
  • the password 611 is sometimes written simultaneously with the shipment data 612 or sometimes written during the manufacturing process to maintain secrecy of the program between a manufacturer of the microcomputer for an IC card (or the IC card) and an issuer of the IC card.
  • step S1 When a reset signal has been received through the RST terminal 10 (step S1), the CPU 2 executes the shipment confirmation routine 36 (step S2) previously stored at a predetermined address in the mask ROM 3a.
  • the shipment confirmation routine 36 determines whether the shipment data 612 has been written in the test EEPROM region 61. Since the shipment data 612 has not been written before the shipment, the process shifts to the branch routine (step S4).
  • the operations from the branch routine 34 (step S4) are the same as those of the conventional technology in that branching is performed in accordance with any one of the mode execution commands supplied externally through the I/O terminal 12 so that the program for each mode is performed.
  • step S2 After the product has been shipped, the shipment data 612 has been written. Therefore, if that writing is confirmed in the shipment confirmation routine 36 (step S2), the process branches to the user mode (step S3). Therefore, branching to the test mode or the burn-in mode is inhibited after shipment. As a result, execution of and access to the test program and the burn-in test program is satisfactorily secured.
  • the password confirmation routine 35 (step S5) performed before branching to the test mode (step S6)
  • the password confirmation routine 35 (step S5) may be dispensed with, if necessary, because execution of and access to the test program and the burn-in test program are reliably prevented after shipment due to the shipment confirmation routine 36 (step S2).
  • FIG. 4 is a functional block diagram that illustrates a microcomputer for an IC card according to the present invention.
  • the microcomputer for an IC card according to this embodiment comprises, in addition to the microcomputer for an IC card according to the first embodiment, a voltage detection circuit 13 for detecting whether the power supply voltage at the Vcc terminal 8 has decreased.
  • the voltage detection circuit 13 is arranged to prevent undesirable branching to the branch routine depending upon an erroneous discrimination made in the shipment confirmation routine that no shipment data has been written if the power supply voltage is too low even the shipment data has been written.
  • the voltage detection circuit 13 comprises a known voltage comparator, such as an M5120TL or LP.
  • FIG. 5 is a flow chart that illustrates the operation of the microcomputer for the IC card shown in FIG. 4.
  • FIG. 5 is a flow chart that illustrates the operation of the microcomputer for the IC card shown in FIG. 4.
  • FIG. 6 illustrates a memory map for use at the time of executing the test program for the microcomputer the IC card shown in FIG. 4.
  • the operational flow shown in FIG. 5 has a voltage detection routine (step S4) so that the voltage detection routine 37 shown in FIG. 6 is executed.
  • the voltage detection routine 37 is, similar to the shipment confirmation routine 36, included in the mask ROM 3a.
  • the microcomputer 1a for an IC card according to this embodiment or the IC card including the microcomputer 1a is, prior to shipment, brought into a test mode (step S7) in which the test program 32 is executed so that the arbitrary shipment data 612 is written in the test EEPROM region 61.
  • step S1 When shipment has been made, a reset signal is supplied through the RST terminal 10 (step S1), the CPU 2 executes the shipment confirmation routine 36 (step S2) previously stored at a predetermined address in the mask ROM 3a. Whether the shipment data has been written in the test EEPROM region 61 is confirmed in the shipment confirmation routine 36. If the confirmation is made, branching to the test mode (step S7) takes place. In this case, branching to the test mode (step S7) and to the burn-in mode (step S8) are inhibited.
  • step S2 If the power supply voltage is too low, although the shipment data 612 has been written on the test EEPROM region 61, an erroneous determination is made in the shipment confirmation routine 36 (step S2) that the shipment data 612 has not been written. Therefore, there is a probability of branching to the branch routine 34 (step S5). Accordingly, the voltage detection routine 37 (step S4) is arranged so that the power supply voltage at the Vcc terminal 8 is detected by the voltage detection circuit 13. If the detected power supply voltage is lower than a predetermined voltage level (low voltage), the discrimination made in the shipment confirmation routine 36 (step S3) is performed. As a result, execution of and access to the test program and the burn-in test program are reliably prohibited after shipment has been made.
  • step S4 follows the shipment confirmation routine (step S2) in the foregoing embodiment, a similar effect can be obtained if the voltage detection routine is performed prior to performing the shipment confirmation routine. Since the foregoing embodiment includes the shipment confirmation routine 36 (step S2) and the voltage detection routine 37 (step S4), execution of and access to the test program and the burn-in test program are reliably secured after shipment. Therefore, the password confirmation routine 35 may be dispensed with, if necessary.
  • FIG. 7 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention.
  • FIG. 8 illustrates a memory map to be used at the time of executing the test program for the microcomputer for an IC card according to this embodiment.
  • the functional block diagram adapted to the microcomputer for an IC card according to this embodiment is the same as shown in FIG. 1.
  • the microcomputer for an IC card according to this embodiment is arranged in such a manner that execution of the burn-in test program with an erroneous burn-in mode execution command is prevented and that the execution and access to the burn-in test program are secured.
  • a burn-in data confirmation routine (step S6) is performed before the burn-in mode (step S7) is performed.
  • the burn-in mode (step S7) includes step S71, a mode selection routine, step S72, a read-only mode, step S73, a write mode, step S74, a dummy write mode, and step S75, an operation stoppage step.
  • the burn-in data confirmation routine 38 and the mode selection routine 39 respectively are performed in step S6 and step S71 in burn-in mode step S7 shown in FIG. 7, the burn-in data confirmation routine 38 and the mode selection routine 39 being stored in the mask ROM 3a.
  • the mode selection routine 39 is included as a portion of the burn-in test program 33. Prior to executing the burn-in test, the burn-in data 613 must be written in the test EEPROM region 61, as shown in FIG. 8.
  • step S7 Prior to executing the burn-in test program 33, arbitrary burn-in data 613 is written in the EEPROM region 61 without exception.
  • step S7 branching to the burn-in mode (step S7) takes place, similar to the operation of the conventional technology.
  • the burn-in data confirmation routine 38 Prior to branching to the burn-in mode, the burn-in data confirmation routine 38 (step S6) is performed. In the burn-in data confirmation routine, confirmation is made as to whether the burn-in data 613 has been written in the test EEPROM region 61. If it has been written, branching to the burn-in mode (step S7) is permitted.
  • step S75 If it has not been written, the operation of, for example, the microcomputer for an IC card is stopped (step S75).
  • a mode selection signal 14 is supplied from outside through the I/O terminal 12 in the mode selection routine 9 (step S71).
  • any one mode is selected from a group consisting of the read-only mode (step S72), the write mode (step S73), the dummy write mode (step S74), and the operation stoppage (step S75).
  • FIG. 9 is a flow chart of the operation of a microcomputer for an IC card according to another embodiment of the present invention.
  • the functional block diagram for the microcomputer for an IC card according to this embodiment is the same as that shown in FIG. 1.
  • This embodiment is arranged in such a manner that a mode is selected in the burn-in mode in accordance with the burn-in data 613 according to the third embodiment. Therefore, the memory map according to this embodiment omits the mode selection routine 39 from the memory map shown in FIG. 8.
  • the burn-in data 613 to be written in the test EEPROM region 61 is predetermined data with respect to a mode to be executed in the burn-in mode. If a read-only mode is selected, for example, the burn-in data 613 to be written is 55 H . If the write mode is selected, the burn-in data 613 to be written is AA H . If the dummy write mode is selected, the burn-in data 613 to be written is 5A H .
  • step S2 the burn-in data 613 for selecting a mode to be executed must be written in the test EEPROM region 61 without exception. If a burn-in test mode execution command has been supplied from outside through the I/O terminal 12 in the branch routine 34 (step S2), branching to the burn-in mode (step S7) takes place. However, the burn-in data confirmation routine 38 (step S6) is performed prior to branching to the burn-in mode. In the burn-in data confirmation routine, reference to the contents of the burn-in data 613 in the test EEPROM region 61 is made. If the burn-in data 613 is 55 H , the read-only mode (step S72) is executed.
  • step S73 the write mode (step S73) is executed. If it is 5A H , the dummy write mode (step S74) is executed. If the burn-in data 613 is other than the foregoing data, operation is stopped (step S75).
  • this embodiment is arranged in such a manner that the burn-in data 613 is used to discriminate whether branching to the burn-in mode (step S7) has been permitted and to detect the mode to be selected in the burn-in mode (step S7). Therefore, the necessity of providing a routine for supplying, from outside, the mode selection signal for selecting a mode in the burn-in mode in the mode selection routine (step S71) shown in FIG. 7 according to the third embodiment can be eliminated.
  • FIG. 10 is a partial flow chart that illustrates the operation of a microcomputer for an IC card according to a fourth embodiment of the present invention wherein the branch routine is branched to the burn-in mode.
  • the overall operation is the same as that according to the third embodiment shown in FIG. 7.
  • the microcomputer for an IC card according to this embodiment is arranged so that a discrimination signal representing a mode that is being executed during the execution of the burn-in test is transmitted to an outside terminal.
  • the burn-in test program 33 has a discrimination signal output step (steps S76 to S78) for transmitting to the I/O terminal 12 a mode discrimination signal 15 representing the mode that is being executed.
  • the residual portions are the same as those according to the third embodiment, the functional block diagram is the same as that shown in FIG. 1, and the memory map shown in FIG. 6 is employed.
  • step S7 branching to the burn-in mode takes place, similar to the operation of the conventional technology.
  • the burn-in data confirmation routine 38 Prior to branching to the burn-in mode, the burn-in data confirmation routine 38 (step S6) is performed. In the burn-in data confirmation routine, confirmation is made as to whether the burn-in data 613 has been written in the test EEPROM region 61. If it has been written, branching to the burn-in mode (step S7) is permitted. If it has not been written, the operation of, for example, the microcomputer for an IC card is stopped (step S75).
  • the mode selection signal 14 is, in the mode selection routine 39 (step S71), supplied from outside through the I/O terminal 12.
  • a mode is selected from a group consisting of the read-only mode (step S72), the write mode (step S73), the dummy write mode (step S74), and the operation stop (step S75).
  • 55 H is, as the mode discrimination signal 15, always transmitted to the I/O terminal 12 (step S76).
  • 5A H is, as the mode discrimination signal 15, always transmitted (step S77).
  • 5A H is, as the mode discrimination signal 15, always transmitted (step S78).
  • the mode that is being executed can be determined from outside.
  • FIG. 11 is a flow chart that illustrates the operation of the microcomputer for an IC card according to this embodiment.
  • FIG. 12 is a memory map for use at the time of executing the test program in the microcomputer for an IC card.
  • the functional block diagram for the microcomputer for an IC card according to this embodiment is the same as that shown in FIG. 4. In each of the drawings, the same reference numerals are given to the same elements as those according to the foregoing embodiments.
  • the shipment confirmation routine (step S2) and the voltage detection routine 37 (step S4) are performed before the branch routine 34 (step S5) is performed.
  • the password confirmation routine step S6 is performed before the test mode (step S7) is performed.
  • the burn-in data confirmation routine (step S8) is performed before the burn-in mode (step S9) is performed. Further, the burn-in test program 33 to be executed in the burn-in mode (step S9) includes a discrimination signal output step (step S10) for generating a signal representing a mode that is being executed.
  • the password 611, the shipment data 612, and the burn-in data 613 are written in the test EEPROM region 61 of the EEPROM 6a (see FIG. 12).
  • step S7 Prior to the shipment of the microcomputer 1a for an IC card according to this embodiment or an IC card including the microcomputer 1a, the test mode (step S7) is commenced so that the test program 32 is executed and arbitrary shipment data 612 is written in the EEPROM region 61.
  • step S1 When a reset signal has been supplied through the RST terminal 10 after shipment has been made (step S1), the CPU 2 executes the shipment confirmation routine 36 (step S2) previously stored at a predetermined address in the mask ROM 3a.
  • the shipment confirmation routine 36 confirmation is made as to whether the shipment data 612 has been written in the test EEPROM region 61. If it has been written, branching to the user mode (step S3) takes place and branching to the test mode (step S7) and to the burn-in mode (step S8) are inhibited.
  • step S2 If the power supply voltage is too low although the shipment data 612 has been written in the test EEPROM region 61, an erroneous determination is made that the shipment data 612 has not been written in the shipment confirmation routine 36 (step S2). In this case, there is a possibility of branching to the branch routine 34 (step S5). Accordingly, the power supply voltage at the Vcc terminal 8 is detected by the voltage detection circuit 13 in the voltage detection routine (step S4). If the detected power supply voltage is lower than a predetermined voltage (low voltage), the determination made in the shipment confirmation routine 36 (step S2) is made invalid and branching to the user mode (step S3) takes place. As a result, execution of and access to the test program and the burn-in program can reliably be secured after shipment has been made.
  • a predetermined voltage low voltage
  • step S9 If, for example, the burn-in mode (step S9) is performed before shipment, the burn-in data 613 is written in the test EEPROM region 61. If the fact that the burn-in data 613 has been written has been confirmed in the burn-in data confirmation routine (step S8), branching to the burn-in mode (step S9) is permitted so that the burn-in test program 33 is executed. In order to determine the existing mode from the read-only mode, the write mode, and the dummy write mode that is being executed in the burn-in mode (step S9), the mode determination signal is transmitted to the outside through the I/O terminal 12 in the discrimination signal output step (step S10).
  • step S9 the mode being executed in the burn-in mode (step S9) can be determined from the mode discrimination signal.
  • a microcomputer according to the present invention is arranged so that the shipment data is written in the test EEPROM region before shipment and the shipment confirmation routine is performed before the branch routine is performed. Therefore, only the user program can be performed after shipment has been made. As a result, a reliable microcomputer for an IC card in which execution of and access to the test program and the burn-in test program are reliably secured is obtained.
  • a voltage detection circuit for detecting the power supply voltage is included and the shipment confirmation routine and the voltage detection routine are performed before the branch routine is performed. Therefore, only the user program can be executed after shipment has been made even if the power supply voltage is low. As a result, an erroneous determination that can be made in the ship confirmation routine due to a reduction of the power supply voltage is prevented. As a result, a still more reliable microcomputer for an IC card is obtained.
  • the burn-in data confirmation routine is performed before branching to the burn-in test program takes place, when the burn-in mode execution command has been received, the burn-in data is written in the test EEPROM region before the burn-in test program is performed, and branching to the burn-in test is inhibited if the burn-in data has not been written in the test EEPROM region in the burn-in data confirmation routine.
  • the burn-in test program cannot easily be executed and execution of the burn-in test program in accordance with an erroneous execution command is prevented. Therefore, a microcomputer for an IC card is obtained in which execution of and access to the burn-in test program is secured.
  • the burn-in test program includes a discrimination signal output step in which a mode discrimination signal representing each mode is transmitted to the outside through the input/output terminal during execution of the respective modes. Therefore, the current mode can be determined from outside the card.

Abstract

A microcomputer for an IC card arranged so that only a user mode can be performed after the microcomputer has been shipped to a user. Data representing that the microcomputer has been shipped is written at the time of shipment in a test region of an EEPROM. A shipment confirmation routine for confirming whether the shipment data has been written is performed before execution of a branch routine for branching to other programs in accordance with an executed command supplied from outside the microcomputer. If the shipment data has been written in the test region of the EEPROM as confirmed in the shipment confirmation routine, only branching to the user mode is permitted.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a microcomputer for an IC card and, more particularly, to a microcomputer including a user program for performing various processes and a test program for performing a test (a product test) of the microcomputer.
2. Description of the Related Art
An IC card including a microcomputer of the foregoing type has been disclosed in Japanese Published Patent Application 2-293196. The test program performs a product test to which the microcomputer is subjected, the test program giving access to any arbitrary address of all regions of the microcomputer to perform the function test satisfactorily. The test program is usually used by a manufacturer (of the microcomputer) or an issuer, and execution of the test program and access to the same must be secured by means of collation of passwords or the like after shipment of the IC card in order to prevent abuse of the test program, e.g., giving access to a region of another person's program for copying or falsifying data.
FIG. 13 is a functional block diagram of a conventional microcomputer for an IC card of the foregoing type. Referring to FIG. 13, reference numeral 1 represents a microcomputer for an IC card (hereinafter called a microcomputer for a card), 2 represents a CPU for processing data, 3 represents a mask ROM, a nonvolatile memory in which a variety of programs are stored, 4 represents a RAM, a volatile memory for temporarily storing data, and 5 represents an input/output control circuit for controlling data input to and output from an external device. Reference numeral 6 represents an EEPROM, a write-enable nonvolatile memory for storing data of the results of a process or the like, and 7 represents a bus mutually connecting the foregoing elements. Reference numeral 8 represents a power source terminal (a Vcc terminal), 9 represents a ground terminal (a GND terminal), 10 represents a reset terminal (an RST terminal), 11 represents a clock terminal (a CLK terminal) and 12 represents an input/output terminal (an I/O terminal). The foregoing terminals form a terminal group for establishing electrical contact with an external device.
FIG. 14 is a flow chart of the operation of the conventional microcomputer for a card. FIGS. 15A and 15B illustrate memory maps for the conventional microcomputer for a card. FIG. 15A illustrates a memory map for executing the user program and FIG. 15B is a memory map for executing the test program. Referring to FIGS. 14, 15A, and 15B, a branch routine 34 is performed in step S2 shown in FIG. 14. A user program 31, a test program 32, and a burn-in test program 33 are respectively performed in a user mode (step S3), a test mode (step S5), and a burn-in mode (step S6). A password confirmation routine 35 is performed in a password confirmation routine (step S4). Reference numeral 61 represents a test EEPROM that cannot be accessed from the user mode. The test EEPROM region 61 is realized by using a means for limiting addresses to prevent access thereto in, for example, the user mode. The detailed structure of the test EEPROM region has been disclosed in Japanese Published Patent Application 2-293196. In the password confirmation routine 35, a password to be subjected to a collation with a key code supplied from outside is stored in the test EEPROM region 61. Referring to FIGS. 15A and 15B, the EEPROM 6 and the test EEPROM region 61 are stored in the EEPROM 6, while the branch routine 34, the password confirmation routine 35, the user program 31, the test program 32, and the burn-in test program 33 are stored in the mask ROM 3.
Referring to the flow chart shown in FIG. 14, the microcomputer 1 for an IC card is connected to an external device at the Vcc terminal 8, the GND terminal 9, the RST terminal 10, the CLK terminal 11, and the I/O terminal 12. When a reset signal is received from outside through the RST terminal 10 (step S1), the CPU 2 executes the branch routine 34 previously stored at a predetermined address in the mask ROM 3 (step S2). In the branch routine 34, the branch routine 34 causes branching to the user mode to take place if a user mode execution command has been supplied through the I/O terminal 12 (step S3). In the user mode, serial data supplied from outside is serial/parallel converted by the input/output control circuit 5, the parallel data being then received by the CPU 2 through the bus 7. The CPU 2 processes the data in accordance with the user program 31 so that data that must be temporarily stored is stored in the RAM 4. Data concerning the results of the process or the like, which must always be stored, is stored in the EEPROM 6. Data to be transmitted outside is parallel/serial converted by the input/output control circuit 5 and the serial data being transferred outside through the I/O terminal 12 (step S3).
If a test mode execution command has been received in the branch routine (step S2) through the I/O terminal 12, branching to the test mode (step S5) takes place. Prior to branching to the test mode, the password confirmation routine 35 (step S4) is performed in order to prevent access to the foregoing test program 32. In the password confirmation routine 35, the key code supplied through the I/O terminal 12 and the password previously stored in the test EEPROM region 61 in the EEPROM 6 are collated with each other. If they agree, branching to the test mode (step S5) is permitted so that the test is performed in accordance with the test program 32. The test program 32, as described above, accesses any arbitrary address so that the CPU 2 gives access to each address in accordance with the test program 32 to perform the product test. If the key code and the password do not agree in the password confirmation routine 35 (step S4), branching to the test mode (step S5) cannot be performed and, therefore, the operation of the microcomputer for an IC card is stopped.
If a burn-in mode execution command has been supplied through the I/O terminal in the branch routine (step S2), branching to the burn-in mode (step S6) takes place so that the CPU 2 performs any one of a burn-in test selected from a group consisting of a read-only burn-in test, a write burn-in test, and a dummy write burn-in test by selecting a mode in accordance with the burn-in test program 33.
Since the conventional microcomputer for an IC card has been constituted as described above, the test program can be performed even after the shipment if the test mode execution command has been supplied in the branch routine and if the key code supplied from outside and the password agree by chance in the password confirmation routine. In this case, there arises a problem in that access to data of another person can be obtained through the test program and, therefore, the data can be copied or falsified. Further, similar to the test program, the burn-in test program having access to any arbitrary address in all regions of the microcomputer is provided with no security means against the execution of and access to the burn-in test program. Therefore, branching to the burn-in test program can easily be performed simply by inputting a burn-in mode execution command in the branch routine, causing a problem in that access to data of another person can be given through the burn-in test program.
There arises another problem in that the burn-in mode has no means for detecting whether a mode has been normally selected during the execution of the burn-in test.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming the foregoing problems and, therefore, an object is to produce a reliable microcomputer for an IC card in which branching is limited to a user mode after the microcomputer has been shipped to a user.
In order to achieve the foregoing object, according to the present invention, there is provided a microcomputer for an IC card comprising a mask ROM storing a user program, a test program and a branch routine for selectively branching to the programs in accordance with an execution command branch; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the mask ROM includes a shipment confirmation routine performed before the branch routine is performed, the test EEPROM region includes a region in which shipment data representing that the microcomputer has been shipped is written, and branching to the user program takes place without exception if confirmation has been made in the shipment confirmation routine that the shipment data has been written in the test EEPROM region.
According to the present invention, there is provided a microcomputer for an IC card comprising a mask ROM storing a user program, a test program and a branch routine for selectively branching to the programs in accordance with an execution command; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the terminal group includes a power source terminal, the microcomputer comprises voltage detection means for detecting whether the power supply voltage at the power source terminal has decreased, the mask ROM includes, before the branch routine, a shipment confirmation routine and a voltage detection routine for detecting the power supply voltage of the power source terminal before or after the shipment confirmation routine has been performed, the test EEPROM region includes a region in which shipment data representing that the microcomputer has been shipped is written, and branching to the user program takes place without exception when a decrease in the power supply voltage at the power source terminal has been detected in the voltage detection routine even if the shipment data has not been written in the test EEPROM region.
According to the present invention, there is provided a microcomputer for an IC card comprising a mask ROM storing a user program, a test program, a burn-in test program and a branch routine for selectively branching to the programs in accordance with an execution command; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the mask ROM includes a burn-in data confirmation routine performed before branching to the burn-in test program takes place, the test EEPROM region includes a region in which burn-in data for previously declaring that the burn-in test program has been executed is written, and branching to the burn-in test program takes place without exception if the burn-in data has not been written in the test EEPROM region.
According to the present invention, there is provided a microcomputer for an IC card comprising a mask ROM storing a user program, a test program, a burn-in test program having a plurality of modes and a branch routine for selectively branching to the programs in accordance with an execution command; a CPU for processing data in accordance with the branch routine and the programs stored in the mask ROM; a RAM for temporarily storing data; an EEPROM storing data and including a test EEPROM region that cannot be accessed from the user program; an input/output control circuit for controlling input/output of data to and from outside; a terminal group for establishing external electrical connections; and a bus mutually connecting the elements, wherein the terminal group includes an input/output terminal, and the burn-in test program includes a discrimination signal output step in which a mode discrimination signal representing the mode, among the plurality of the modes, which is being executed, is transmitted through the input/output terminal.
A microcomputer for an IC card according to the invention is arranged in so that the shipment confirmation routine is performed before the branch routine is performed. Therefore, branching in the shipment confirmation routine is limited only to the user mode after the microcomputer for an IC card having the shipment data written in the test EEPROM region has been shipped.
A microcomputer for an IC card according to the invention also includes voltage detection means and a voltage detection routine. Therefore, even if branching to the user mode is performed in the shipment confirmation routine, branching to the user mode is performed in the voltage detection routine when a reduction in the power supply voltage has been detected.
A microcomputer for an IC card according to the invention includes a burn-in data confirmation routine performed prior to branching to the burn-in test program. Therefore, the burn-in test program cannot be performed if the burn-in data has not been written on the test EEPROM region. As a result, execution of the burn-in test in accordance with an erroneous execution command is prevented. Therefore, unauthorized execution and access to the burn-in test program can be prevented.
A microcomputer for an IC card according to the invention includes the burn-in test program having a discrimination signal output step in which a mode discrimination signal representing the mode which is being executed is transmitted to the outside through the input/output terminal. Therefore, the current burn-in mode can be detected from outside the microcomputer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram that illustrates the functions of a microcomputer for an IC card according to the present invention;
FIG. 2 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention;
FIG. 3 illustrates a memory map for use at the time of executing a test program in a microcomputer for an IC card according to the present invention;
FIG. 4 is a block diagram that illustrates the functions of a microcomputer for an IC card according to the present invention;
FIG. 5 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention;
FIG. 6 illustrates a memory map for use at the time of executing a test program in a microcomputer for an IC card according to the present invention;
FIG. 7 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention;
FIG. 8 illustrates a memory map for use at the time of executing a test program in a microcomputer for an IC card according to the present invention;
FIG. 9 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention;
FIG. 10 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention;
FIG. 11 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention;
FIG. 12 illustrates a memory map for use at the time of executing a test program in the microcomputer for an IC card shown in FIG. 11;
FIG. 13 is a functional block diagram that illustrates the functions of a conventional microcomputer for an IC card;
FIG. 14 is a flow chart that illustrates the operation of the conventional microcomputer for an IC card;
FIG. 15A illustrates a memory map for use at the time of executing a test program in the conventional microcomputer for an IC card; and
FIG. 15B is a view that illustrates a memory map for use at the time of executing a test program in the conventional microcomputer for an IC card.
DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
FIG. 1 is a functional block diagram that illustrates a microcomputer for an IC card according to the present invention. FIG. 2 is a flow chart that illustrates the operation of the microcomputer for an IC card shown in FIG. 1. FIG. 3 illustrates a memory map for use at the time of executing a test program in the microcomputer for an IC card shown in FIG. 1. The elements of the microcomputer 1a for an IC card that are the same or correspond to those of the conventional microcomputer are given the same reference numerals and their descriptions are omitted here. Referring to the drawings, a mask ROM 3a contains the conventional user program 31, the test program 32, the burn-in test program 33, the branch routine 34, the password confirmation routine 35, and a shipment confirmation routine 36 shown in FIG. 3. The EEPROM region 61 of the EEPROM 6a shown in FIG. 3 includes shipment data 612 to be used in the shipment confirmation routine 36 as well as a password code 611 for use in the password confirmation routine 35.
Operation will now be described with reference to the flow chart shown in FIG. 2. Prior to shipment of the microcomputer 1a for an IC card according to this embodiment or an IC card including the foregoing microcomputer, a test mode (step S6) is commenced to execute the test program 32 so that the arbitrary shipment data 612 is written on the test EEPROM region 61. After the shipment data 612 has been written, the microcomputer 1a for an IC card or the IC card including the foregoing microcomputer is shipped. The password 611 is sometimes written simultaneously with the shipment data 612 or sometimes written during the manufacturing process to maintain secrecy of the program between a manufacturer of the microcomputer for an IC card (or the IC card) and an issuer of the IC card.
The operations performed before shipment will now be described. When a reset signal has been received through the RST terminal 10 (step S1), the CPU 2 executes the shipment confirmation routine 36 (step S2) previously stored at a predetermined address in the mask ROM 3a. The shipment confirmation routine 36 determines whether the shipment data 612 has been written in the test EEPROM region 61. Since the shipment data 612 has not been written before the shipment, the process shifts to the branch routine (step S4). The operations from the branch routine 34 (step S4) are the same as those of the conventional technology in that branching is performed in accordance with any one of the mode execution commands supplied externally through the I/O terminal 12 so that the program for each mode is performed.
After the product has been shipped, the shipment data 612 has been written. Therefore, if that writing is confirmed in the shipment confirmation routine 36 (step S2), the process branches to the user mode (step S3). Therefore, branching to the test mode or the burn-in mode is inhibited after shipment. As a result, execution of and access to the test program and the burn-in test program is satisfactorily secured.
Although the foregoing embodiment, similar to the conventional technology, includes the password confirmation routine 35 (step S5) performed before branching to the test mode (step S6), the password confirmation routine 35 (step S5) may be dispensed with, if necessary, because execution of and access to the test program and the burn-in test program are reliably prevented after shipment due to the shipment confirmation routine 36 (step S2).
Second Embodiment
FIG. 4 is a functional block diagram that illustrates a microcomputer for an IC card according to the present invention. The microcomputer for an IC card according to this embodiment comprises, in addition to the microcomputer for an IC card according to the first embodiment, a voltage detection circuit 13 for detecting whether the power supply voltage at the Vcc terminal 8 has decreased. The voltage detection circuit 13 is arranged to prevent undesirable branching to the branch routine depending upon an erroneous discrimination made in the shipment confirmation routine that no shipment data has been written if the power supply voltage is too low even the shipment data has been written. The voltage detection circuit 13 comprises a known voltage comparator, such as an M5120TL or LP. FIG. 5 is a flow chart that illustrates the operation of the microcomputer for the IC card shown in FIG. 4. FIG. 6 illustrates a memory map for use at the time of executing the test program for the microcomputer the IC card shown in FIG. 4. The operational flow shown in FIG. 5 has a voltage detection routine (step S4) so that the voltage detection routine 37 shown in FIG. 6 is executed. The voltage detection routine 37 is, similar to the shipment confirmation routine 36, included in the mask ROM 3a.
Operation will now be described with reference to the flow chart in FIG. 5. Similar to the microcomputer for an IC card according to the first embodiment, the microcomputer 1a for an IC card according to this embodiment or the IC card including the microcomputer 1a is, prior to shipment, brought into a test mode (step S7) in which the test program 32 is executed so that the arbitrary shipment data 612 is written in the test EEPROM region 61.
Since the operations performed before shipment are the same as those performed in the first embodiment, their description is omitted.
When shipment has been made, a reset signal is supplied through the RST terminal 10 (step S1), the CPU 2 executes the shipment confirmation routine 36 (step S2) previously stored at a predetermined address in the mask ROM 3a. Whether the shipment data has been written in the test EEPROM region 61 is confirmed in the shipment confirmation routine 36. If the confirmation is made, branching to the test mode (step S7) takes place. In this case, branching to the test mode (step S7) and to the burn-in mode (step S8) are inhibited.
If the power supply voltage is too low, although the shipment data 612 has been written on the test EEPROM region 61, an erroneous determination is made in the shipment confirmation routine 36 (step S2) that the shipment data 612 has not been written. Therefore, there is a probability of branching to the branch routine 34 (step S5). Accordingly, the voltage detection routine 37 (step S4) is arranged so that the power supply voltage at the Vcc terminal 8 is detected by the voltage detection circuit 13. If the detected power supply voltage is lower than a predetermined voltage level (low voltage), the discrimination made in the shipment confirmation routine 36 (step S3) is performed. As a result, execution of and access to the test program and the burn-in test program are reliably prohibited after shipment has been made.
Although the voltage detection routine (step S4) follows the shipment confirmation routine (step S2) in the foregoing embodiment, a similar effect can be obtained if the voltage detection routine is performed prior to performing the shipment confirmation routine. Since the foregoing embodiment includes the shipment confirmation routine 36 (step S2) and the voltage detection routine 37 (step S4), execution of and access to the test program and the burn-in test program are reliably secured after shipment. Therefore, the password confirmation routine 35 may be dispensed with, if necessary.
Third Embodiment
FIG. 7 is a flow chart that illustrates the operation of a microcomputer for an IC card according to the present invention. FIG. 8 illustrates a memory map to be used at the time of executing the test program for the microcomputer for an IC card according to this embodiment. The functional block diagram adapted to the microcomputer for an IC card according to this embodiment is the same as shown in FIG. 1. The microcomputer for an IC card according to this embodiment is arranged in such a manner that execution of the burn-in test program with an erroneous burn-in mode execution command is prevented and that the execution and access to the burn-in test program are secured.
As shown in the flow chart of FIG. 7, a burn-in data confirmation routine (step S6) is performed before the burn-in mode (step S7) is performed. Moreover, the burn-in mode (step S7) includes step S71, a mode selection routine, step S72, a read-only mode, step S73, a write mode, step S74, a dummy write mode, and step S75, an operation stoppage step. As shown in FIG. 8, the burn-in data confirmation routine 38 and the mode selection routine 39 respectively are performed in step S6 and step S71 in burn-in mode step S7 shown in FIG. 7, the burn-in data confirmation routine 38 and the mode selection routine 39 being stored in the mask ROM 3a. The mode selection routine 39 is included as a portion of the burn-in test program 33. Prior to executing the burn-in test, the burn-in data 613 must be written in the test EEPROM region 61, as shown in FIG. 8.
Operation will now be described with reference to the flow chart shown in FIG. 7. Prior to executing the burn-in test program 33, arbitrary burn-in data 613 is written in the EEPROM region 61 without exception. When the burn-in mode execution command has been supplied from outside through the I/O terminal 12 in the branch routine 34 (step S2), branching to the burn-in mode (step S7) takes place, similar to the operation of the conventional technology. Prior to branching to the burn-in mode, the burn-in data confirmation routine 38 (step S6) is performed. In the burn-in data confirmation routine, confirmation is made as to whether the burn-in data 613 has been written in the test EEPROM region 61. If it has been written, branching to the burn-in mode (step S7) is permitted. If it has not been written, the operation of, for example, the microcomputer for an IC card is stopped (step S75). In the burn-in mode (step S7), a mode selection signal 14 is supplied from outside through the I/O terminal 12 in the mode selection routine 9 (step S71). In response to the thus-supplied signal, any one mode is selected from a group consisting of the read-only mode (step S72), the write mode (step S73), the dummy write mode (step S74), and the operation stoppage (step S75).
Since branching to the burn-in mode is not permitted if the burn-in data is not written in the test EEPROM region 61 in the EEPROM 6a before the burn-in test is performed, execution of the burn-in test program in accordance with an erroneous burn-in mode execution command is prevented. Further, execution of and access to the burn-in test program are reliably secured.
Fourth Embodiment
FIG. 9 is a flow chart of the operation of a microcomputer for an IC card according to another embodiment of the present invention. The functional block diagram for the microcomputer for an IC card according to this embodiment is the same as that shown in FIG. 1. This embodiment is arranged in such a manner that a mode is selected in the burn-in mode in accordance with the burn-in data 613 according to the third embodiment. Therefore, the memory map according to this embodiment omits the mode selection routine 39 from the memory map shown in FIG. 8. Further, the burn-in data 613 to be written in the test EEPROM region 61 is predetermined data with respect to a mode to be executed in the burn-in mode. If a read-only mode is selected, for example, the burn-in data 613 to be written is 55H. If the write mode is selected, the burn-in data 613 to be written is AAH. If the dummy write mode is selected, the burn-in data 613 to be written is 5AH.
Operation will now be described with reference to the flow chart in FIG. 9. Prior to executing the burn-in test program 33, the burn-in data 613 for selecting a mode to be executed must be written in the test EEPROM region 61 without exception. If a burn-in test mode execution command has been supplied from outside through the I/O terminal 12 in the branch routine 34 (step S2), branching to the burn-in mode (step S7) takes place. However, the burn-in data confirmation routine 38 (step S6) is performed prior to branching to the burn-in mode. In the burn-in data confirmation routine, reference to the contents of the burn-in data 613 in the test EEPROM region 61 is made. If the burn-in data 613 is 55H, the read-only mode (step S72) is executed. If it is AAH, the write mode (step S73) is executed. If it is 5AH, the dummy write mode (step S74) is executed. If the burn-in data 613 is other than the foregoing data, operation is stopped (step S75).
As described above, this embodiment is arranged in such a manner that the burn-in data 613 is used to discriminate whether branching to the burn-in mode (step S7) has been permitted and to detect the mode to be selected in the burn-in mode (step S7). Therefore, the necessity of providing a routine for supplying, from outside, the mode selection signal for selecting a mode in the burn-in mode in the mode selection routine (step S71) shown in FIG. 7 according to the third embodiment can be eliminated.
Fifth Embodiment
FIG. 10 is a partial flow chart that illustrates the operation of a microcomputer for an IC card according to a fourth embodiment of the present invention wherein the branch routine is branched to the burn-in mode. The overall operation is the same as that according to the third embodiment shown in FIG. 7. The microcomputer for an IC card according to this embodiment is arranged so that a discrimination signal representing a mode that is being executed during the execution of the burn-in test is transmitted to an outside terminal. In order to realize this feature, the burn-in test program 33 has a discrimination signal output step (steps S76 to S78) for transmitting to the I/O terminal 12 a mode discrimination signal 15 representing the mode that is being executed. The residual portions are the same as those according to the third embodiment, the functional block diagram is the same as that shown in FIG. 1, and the memory map shown in FIG. 6 is employed.
Operation will now be described with reference to a flow chart shown in FIG. 10. When a burn-in mode execution command is supplied in the branch routine, branching to the burn-in mode (step S7) takes place, similar to the operation of the conventional technology. Prior to branching to the burn-in mode, the burn-in data confirmation routine 38 (step S6) is performed. In the burn-in data confirmation routine, confirmation is made as to whether the burn-in data 613 has been written in the test EEPROM region 61. If it has been written, branching to the burn-in mode (step S7) is permitted. If it has not been written, the operation of, for example, the microcomputer for an IC card is stopped (step S75). In the burn-in mode (step S7), the mode selection signal 14 is, in the mode selection routine 39 (step S71), supplied from outside through the I/O terminal 12. In response to the foregoing signal, a mode is selected from a group consisting of the read-only mode (step S72), the write mode (step S73), the dummy write mode (step S74), and the operation stop (step S75). During execution of the read-only mode (step S72), 55H is, as the mode discrimination signal 15, always transmitted to the I/O terminal 12 (step S76). During execution of the write mode (step S73), 5AH is, as the mode discrimination signal 15, always transmitted (step S77). During execution of the dummy write mode (step S74), 5AH is, as the mode discrimination signal 15, always transmitted (step S78).
By transmitting the mode discrimination signal representing the mode that is being executed in the burn-in test, the mode that is being executed can be determined from outside.
Sixth Embodiment
FIG. 11 is a flow chart that illustrates the operation of the microcomputer for an IC card according to this embodiment. FIG. 12 is a memory map for use at the time of executing the test program in the microcomputer for an IC card. The functional block diagram for the microcomputer for an IC card according to this embodiment is the same as that shown in FIG. 4. In each of the drawings, the same reference numerals are given to the same elements as those according to the foregoing embodiments. In this embodiment, the shipment confirmation routine (step S2) and the voltage detection routine 37 (step S4) are performed before the branch routine 34 (step S5) is performed. Furthermore, the password confirmation routine (step S6) is performed before the test mode (step S7) is performed. The burn-in data confirmation routine (step S8) is performed before the burn-in mode (step S9) is performed. Further, the burn-in test program 33 to be executed in the burn-in mode (step S9) includes a discrimination signal output step (step S10) for generating a signal representing a mode that is being executed. The password 611, the shipment data 612, and the burn-in data 613 are written in the test EEPROM region 61 of the EEPROM 6a (see FIG. 12).
The operation will now be described briefly with reference to the flow chart in FIG. 11. Prior to the shipment of the microcomputer 1a for an IC card according to this embodiment or an IC card including the microcomputer 1a, the test mode (step S7) is commenced so that the test program 32 is executed and arbitrary shipment data 612 is written in the EEPROM region 61.
When a reset signal has been supplied through the RST terminal 10 after shipment has been made (step S1), the CPU 2 executes the shipment confirmation routine 36 (step S2) previously stored at a predetermined address in the mask ROM 3a. In the shipment confirmation routine 36, confirmation is made as to whether the shipment data 612 has been written in the test EEPROM region 61. If it has been written, branching to the user mode (step S3) takes place and branching to the test mode (step S7) and to the burn-in mode (step S8) are inhibited.
If the power supply voltage is too low although the shipment data 612 has been written in the test EEPROM region 61, an erroneous determination is made that the shipment data 612 has not been written in the shipment confirmation routine 36 (step S2). In this case, there is a possibility of branching to the branch routine 34 (step S5). Accordingly, the power supply voltage at the Vcc terminal 8 is detected by the voltage detection circuit 13 in the voltage detection routine (step S4). If the detected power supply voltage is lower than a predetermined voltage (low voltage), the determination made in the shipment confirmation routine 36 (step S2) is made invalid and branching to the user mode (step S3) takes place. As a result, execution of and access to the test program and the burn-in program can reliably be secured after shipment has been made.
If, for example, the burn-in mode (step S9) is performed before shipment, the burn-in data 613 is written in the test EEPROM region 61. If the fact that the burn-in data 613 has been written has been confirmed in the burn-in data confirmation routine (step S8), branching to the burn-in mode (step S9) is permitted so that the burn-in test program 33 is executed. In order to determine the existing mode from the read-only mode, the write mode, and the dummy write mode that is being executed in the burn-in mode (step S9), the mode determination signal is transmitted to the outside through the I/O terminal 12 in the discrimination signal output step (step S10). As a result, execution of the burn-in test program in accordance with an erroneous burn-in mode execution command is prevented. Further, execution and access to the burn-in test program can be secured. Moreover, the mode being executed in the burn-in mode (step S9) can be determined from the mode discrimination signal.
The foregoing embodiments including the sixth embodiment may be combined variously so that a microcomputer for an IC card having a plurality of desired functions can be realized.
As described above, a microcomputer according to the present invention is arranged so that the shipment data is written in the test EEPROM region before shipment and the shipment confirmation routine is performed before the branch routine is performed. Therefore, only the user program can be performed after shipment has been made. As a result, a reliable microcomputer for an IC card in which execution of and access to the test program and the burn-in test program are reliably secured is obtained.
According to the present invention, in addition, a voltage detection circuit for detecting the power supply voltage is included and the shipment confirmation routine and the voltage detection routine are performed before the branch routine is performed. Therefore, only the user program can be executed after shipment has been made even if the power supply voltage is low. As a result, an erroneous determination that can be made in the ship confirmation routine due to a reduction of the power supply voltage is prevented. As a result, a still more reliable microcomputer for an IC card is obtained.
According to another aspect of the present invention, the burn-in data confirmation routine is performed before branching to the burn-in test program takes place, when the burn-in mode execution command has been received, the burn-in data is written in the test EEPROM region before the burn-in test program is performed, and branching to the burn-in test is inhibited if the burn-in data has not been written in the test EEPROM region in the burn-in data confirmation routine. As a result, the burn-in test program cannot easily be executed and execution of the burn-in test program in accordance with an erroneous execution command is prevented. Therefore, a microcomputer for an IC card is obtained in which execution of and access to the burn-in test program is secured.
According to still another aspect of the present invention, the burn-in test program includes a discrimination signal output step in which a mode discrimination signal representing each mode is transmitted to the outside through the input/output terminal during execution of the respective modes. Therefore, the current mode can be determined from outside the card.

Claims (4)

What is claimed is:
1. A microcomputer for an IC card comprising:
a mask ROM storing a user program, a test program, and a branch routine for selectively branching to the user and test programs in accordance with an execution command;
a CPU for processing data in accordance with the branch routine and the user and test programs stored in said mask ROM;
a RAM for temporarily storing data;
an EEPROM for storing data, having a plurality of memory locations, and including designated memory locations forming a test EEPROM region that cannot be accessed from the user program;
an input/output control circuit for controlling input of data to and output of data from said microcomputer;
terminals for establishing external electrical connections to said microcomputer; and
a bus mutually connecting said mask ROM, said CPU, said RAM, said EEPROM, and said input/output circuit, wherein said mask ROM includes a shipment confirmation routine performed before the branch routine is performed, said test EEPROM region includes memory locations where shipment data representing whether said microcomputer has been shipped is written, and branching to the user program takes place without exception if confirmation has been made in the shipment confirmation routine that the shipment data has been written in the test EEPROM region.
2. The microcomputer for an IC card of claim 1 wherein said mask ROM stores a password confirmation routine, and wherein, if the shipment confirmation routine confirms that the shipment data has not been written, branching to the test program only occurs if the password confirmation routine determines that a valid password has been input through said input/output control circuit.
3. A microcomputer for an IC card comprising:
a mask ROM storing a user program, a test program, and a branch routine for selectively branching to the user and test programs in accordance with an execution command;
a CPU for processing data in accordance with the branch routine and the user and test programs stored in said mask ROM;
a RAM for temporarily storing data;
an EEPROM for storing data, having a plurality of memory locations, and including designated memory locations forming a test EEPROM region that cannot be accessed from the user program;
an input/output control circuit for controlling input of data to and output of data from said microcomputer;
terminals for establishing external electrical connections to said microcomputer; and
a bus mutually connecting said mask ROM, said CPU, said RAM, said EEPROM, and said input/output circuit, wherein said terminals include a power source terminal;
voltage detection means for detecting whether a power supply voltage at said power source terminal has decreased, said mask ROM including, before the branch routine, a shipment confirmation routine and a voltage detection routine for detecting the power supply voltage at said power source terminal regardless of whether the shipment confirmation routine has been performed, said test EEPROM region includes a region in which shipment data representing that said microcomputer has been shipped is written, and branching to the user program takes place without exception when a decrease in the power supply voltage at said power source terminal has been detected in the voltage detection routine even if the shipment data has not been written in said test EEPROM region as determined in said shipment confirmation routine.
4. A microcomputer for an IC card comprising:
a mask ROM storing a user program, a test program, a burn-in test program, and a branch routine for selectively branching to the user, test, and burn-in test programs in accordance with an execution command;
a CPU for processing data in accordance with the branch routine and the user, test, and burn-in test programs stored in said mask ROM;
a RAM for temporarily storing data;
an EEPROM for storing data, having a plurality of memory locations, and including designated memory locations forming a test EEPROM region that cannot be accessed from the user program;
an input/output control circuit for controlling input of data to and output of data from said microcomputer;
terminals for establishing external electrical connections to said microcomputer; and
a bus mutually connecting said mask ROM, said CPU, said RAM, said EEPROM, and said input/output circuit, wherein said mask ROM includes a burn-in data confirmation routine performed before branching to the burn-in test program takes place, said test EEPROM region includes memory locations where burn-in data indicating that the burn-in test program has been executed is written, and stopping operation of the microcomputer, without exception, if the burn-in data confirmation routine determines that the burn-in data has not been written in said test EEPROM region.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230291B1 (en) * 1997-08-28 2001-05-08 Nec Corporation Microcomputer including burn-in test circuit and burn-in test method thereof including mode switching device
US6587901B2 (en) * 2000-11-17 2003-07-01 Hitachi, Ltd. Information processing system, portable electronic equipment and information processing apparatus
US20030140261A1 (en) * 2002-01-24 2003-07-24 Minoru Takasaki Control apparatus
US20040111655A1 (en) * 2002-12-06 2004-06-10 Mitsuhiro Watanabe Microcomputer and test method therefore
US20040138810A1 (en) * 2003-01-10 2004-07-15 Yoshihiko Sugawara Map search system
US20040168072A1 (en) * 2003-02-24 2004-08-26 Yannick Teglia Method and device for selecting the operating mode of an integrated circuit
US20100138915A1 (en) * 2008-12-02 2010-06-03 Antonino La Malfa Password Protected Built-In Test Mode For Memories

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2732133B1 (en) * 1995-03-21 1997-04-25 Sgs Thomson Microelectronics COHERENCE DETECTOR OF INFORMATION CONTAINED IN AN INTEGRATED CIRCUIT
EP0852032A1 (en) * 1995-07-20 1998-07-08 Dallas Semiconductor Corporation Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface
DE19711478A1 (en) * 1997-03-19 1998-10-01 Siemens Ag Integrated circuit and method for testing the integrated circuit
FR2767624B1 (en) * 1997-08-21 2002-05-10 Activcard ELECTRONIC PORTABLE DEVICE FOR SECURE COMMUNICATION SYSTEM, AND METHOD FOR INITIALIZING ITS PARAMETERS
DE19804784A1 (en) * 1998-02-06 1999-08-12 Philips Patentverwaltung Chip card with integrated circuit
WO2001009932A1 (en) 1999-07-30 2001-02-08 Nippon Sheet Glass Co., Ltd. Method of dicing semiconductor wafer into chips, and structure of groove formed in dicing area
DE10251839A1 (en) * 2002-11-07 2004-05-19 Robert Bosch Gmbh Motor vehicle microcontroller control method, involves checking re-writable area with check program and triggering RESET if checked area is manipulated or counter overflows
FR2851668A1 (en) 2003-02-24 2004-08-27 St Microelectronics Sa Operation mode selection device for integrated circuit, has control unit inactivating selection signal when number of data words stored in programmable memory similar to data words stored in ROM is greater than preset threshold
JP2008146381A (en) * 2006-12-11 2008-06-26 Ricoh Co Ltd Built-in computer equipment
US8365983B2 (en) * 2009-11-20 2013-02-05 Intel Corporation Radio-frequency reconfigurations of microelectronic systems in commercial packages
CN102592683B (en) * 2012-02-23 2014-12-10 苏州华芯微电子股份有限公司 Method for entering chip test mode and related device

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4650975A (en) * 1984-08-30 1987-03-17 Casio Computer Co., Ltd. IC card and an identification system thereof
US4777355A (en) * 1986-12-24 1988-10-11 Mitsubishi Denki Kabushiki Kaisha IC card and system for checking the functionality thereof
US4816656A (en) * 1986-01-14 1989-03-28 Casio Computer Co., Ltd. IC card system
EP0411255A2 (en) * 1989-08-04 1991-02-06 Motorola, Inc. Memory system
US5016212A (en) * 1988-06-30 1991-05-14 Mitsubishi Denki Kabushiki Kaisha IC card having system ROM selection inhibit
US5019970A (en) * 1988-06-30 1991-05-28 Mitsubishi Denki Kabushiki Kaisha IC card
US5039850A (en) * 1990-06-15 1991-08-13 Mitsubishi Denki Kabushiki Kaisha IC card
US5062075A (en) * 1986-11-07 1991-10-29 Oki Electric Industry Co., Ltd. Microcomputer having security memory using test and destruction routines
US5126541A (en) * 1988-08-26 1992-06-30 Hitachi Maxell, Ltd. Integrated circuit card
US5206938A (en) * 1989-05-09 1993-04-27 Mitsubishi Denki Kabushiki Kaisha Ic card with memory area protection based on address line restriction
US5286962A (en) * 1990-12-14 1994-02-15 Mitsubishi Denki Kabushiki Kaisha IC card for prevention of fraudulent use
US5293610A (en) * 1989-08-04 1994-03-08 Motorola, Inc. Memory system having two-level security system for enhanced protection against unauthorized access

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4650975A (en) * 1984-08-30 1987-03-17 Casio Computer Co., Ltd. IC card and an identification system thereof
US4816656A (en) * 1986-01-14 1989-03-28 Casio Computer Co., Ltd. IC card system
US5062075A (en) * 1986-11-07 1991-10-29 Oki Electric Industry Co., Ltd. Microcomputer having security memory using test and destruction routines
US4777355A (en) * 1986-12-24 1988-10-11 Mitsubishi Denki Kabushiki Kaisha IC card and system for checking the functionality thereof
US5016212A (en) * 1988-06-30 1991-05-14 Mitsubishi Denki Kabushiki Kaisha IC card having system ROM selection inhibit
US5019970A (en) * 1988-06-30 1991-05-28 Mitsubishi Denki Kabushiki Kaisha IC card
US5126541A (en) * 1988-08-26 1992-06-30 Hitachi Maxell, Ltd. Integrated circuit card
US5206938A (en) * 1989-05-09 1993-04-27 Mitsubishi Denki Kabushiki Kaisha Ic card with memory area protection based on address line restriction
EP0411255A2 (en) * 1989-08-04 1991-02-06 Motorola, Inc. Memory system
US5293610A (en) * 1989-08-04 1994-03-08 Motorola, Inc. Memory system having two-level security system for enhanced protection against unauthorized access
US5039850A (en) * 1990-06-15 1991-08-13 Mitsubishi Denki Kabushiki Kaisha IC card
US5286962A (en) * 1990-12-14 1994-02-15 Mitsubishi Denki Kabushiki Kaisha IC card for prevention of fraudulent use

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Volker Timm, Elektronik, vol. 37, No. 22, 28, Oct. 1988, Munchen de, pp. 204 208. *
Volker Timm, Elektronik, vol. 37, No. 22, 28, Oct. 1988, Munchen de, pp. 204-208.

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6230291B1 (en) * 1997-08-28 2001-05-08 Nec Corporation Microcomputer including burn-in test circuit and burn-in test method thereof including mode switching device
US6587901B2 (en) * 2000-11-17 2003-07-01 Hitachi, Ltd. Information processing system, portable electronic equipment and information processing apparatus
US20030140261A1 (en) * 2002-01-24 2003-07-24 Minoru Takasaki Control apparatus
US20040111655A1 (en) * 2002-12-06 2004-06-10 Mitsuhiro Watanabe Microcomputer and test method therefore
US7415730B2 (en) * 2002-12-06 2008-08-19 Oki Electric Industry Co., Ltd. Microcomputer and test method therefore
US20040138810A1 (en) * 2003-01-10 2004-07-15 Yoshihiko Sugawara Map search system
US7225076B2 (en) * 2003-01-10 2007-05-29 Denso Corporation Map search system
US20040168072A1 (en) * 2003-02-24 2004-08-26 Yannick Teglia Method and device for selecting the operating mode of an integrated circuit
US7325181B2 (en) * 2003-02-24 2008-01-29 Stmicroelectronics S.A. Method and device for selecting the operating mode of an integrated circuit
US20100138915A1 (en) * 2008-12-02 2010-06-03 Antonino La Malfa Password Protected Built-In Test Mode For Memories
US8844023B2 (en) * 2008-12-02 2014-09-23 Micron Technology, Inc. Password protected built-in test mode for memories

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