US5604909A - Apparatus for processing instructions in a computing system - Google Patents
Apparatus for processing instructions in a computing system Download PDFInfo
- Publication number
- US5604909A US5604909A US08/168,744 US16874493A US5604909A US 5604909 A US5604909 A US 5604909A US 16874493 A US16874493 A US 16874493A US 5604909 A US5604909 A US 5604909A
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- United States
- Prior art keywords
- instruction
- circuit
- instructions
- storing
- queue
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- Expired - Lifetime
Links
- 238000012545 processing Methods 0.000 title claims description 12
- 238000004891 communication Methods 0.000 claims description 71
- 230000002401 inhibitory effect Effects 0.000 claims 2
- 230000000737 periodic effect Effects 0.000 claims 1
- 239000000872 buffer Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 13
- 230000004044 response Effects 0.000 description 4
- 238000012937 correction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
TABLE 1 ______________________________________ STATE [1:0] Q0MXSEL Q1MXSEL Q2MXSEL Q3MXSEL ______________________________________ 0 STATE STATE STATE STATE[4:2] [4:2] [4:2] [4:2] 1 STATE STATE STATE STATE [4:2] [4:2] - 1 [4:2] [4:2] 2 STATE STATE STATE STATE[4:2] [4:2] - 1 [4:2] - 1 [4:2] 3 STATE STATE STATE STATE[4:2] [4:2] - 1 [4:2] - 1 [4:2] - 1 ______________________________________
Claims (19)
Priority Applications (13)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/168,744 US5604909A (en) | 1993-12-15 | 1993-12-15 | Apparatus for processing instructions in a computing system |
EP03003266A EP1320031A3 (en) | 1993-12-15 | 1994-12-15 | Apparatus for branch prediction |
EP95902965A EP0690373B1 (en) | 1993-12-15 | 1994-12-15 | Apparatus for processing instructions in a computing system |
DE69433621T DE69433621T2 (en) | 1993-12-15 | 1994-12-15 | DEVICE FOR PROCESSING COMMANDS IN A COMPUTER SYSTEM |
CNB021407622A CN1267819C (en) | 1993-12-15 | 1994-12-15 | Computer system internal instruction processing device |
CN94191180A CN1104680C (en) | 1993-12-15 | 1994-12-15 | Apparatus for processing instruction in computer system |
PCT/JP1994/002112 WO1995016954A1 (en) | 1993-12-15 | 1994-12-15 | Apparatus for processing instruction in computer system |
JP7516669A JP2815237B2 (en) | 1993-12-15 | 1994-12-15 | A device that processes instructions inside a computer system |
KR1019950703432A KR100212204B1 (en) | 1993-12-15 | 1994-12-15 | Apparatus for processing instruction in computer system |
US08/781,851 US5954815A (en) | 1993-12-15 | 1997-01-10 | Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address |
HK98114187A HK1013153A1 (en) | 1993-12-15 | 1998-12-21 | Apparatus for processing instructions in a computing system. |
US09/363,635 US6247124B1 (en) | 1993-12-15 | 1999-07-30 | Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions |
US09/863,898 US6691221B2 (en) | 1993-12-15 | 2001-05-24 | Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/168,744 US5604909A (en) | 1993-12-15 | 1993-12-15 | Apparatus for processing instructions in a computing system |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US47694295A Division | 1993-12-15 | 1995-06-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5604909A true US5604909A (en) | 1997-02-18 |
Family
ID=22612755
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/168,744 Expired - Lifetime US5604909A (en) | 1993-12-15 | 1993-12-15 | Apparatus for processing instructions in a computing system |
US08/781,851 Expired - Lifetime US5954815A (en) | 1993-12-15 | 1997-01-10 | Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address |
US09/363,635 Expired - Lifetime US6247124B1 (en) | 1993-12-15 | 1999-07-30 | Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions |
US09/863,898 Expired - Fee Related US6691221B2 (en) | 1993-12-15 | 2001-05-24 | Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/781,851 Expired - Lifetime US5954815A (en) | 1993-12-15 | 1997-01-10 | Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address |
US09/363,635 Expired - Lifetime US6247124B1 (en) | 1993-12-15 | 1999-07-30 | Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions |
US09/863,898 Expired - Fee Related US6691221B2 (en) | 1993-12-15 | 2001-05-24 | Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution |
Country Status (8)
Country | Link |
---|---|
US (4) | US5604909A (en) |
EP (2) | EP1320031A3 (en) |
JP (1) | JP2815237B2 (en) |
KR (1) | KR100212204B1 (en) |
CN (2) | CN1267819C (en) |
DE (1) | DE69433621T2 (en) |
HK (1) | HK1013153A1 (en) |
WO (1) | WO1995016954A1 (en) |
Cited By (40)
Publication number | Priority date | Publication date | Assignee | Title |
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US5859992A (en) * | 1997-03-12 | 1999-01-12 | Advanced Micro Devices, Inc. | Instruction alignment using a dispatch list and a latch list |
US5935238A (en) * | 1997-06-19 | 1999-08-10 | Sun Microsystems, Inc. | Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles |
US5938756A (en) * | 1994-04-29 | 1999-08-17 | Sun Microsystems, Inc. | Central processing unit with integrated graphics functions |
US5964869A (en) * | 1997-06-19 | 1999-10-12 | Sun Microsystems, Inc. | Instruction fetch mechanism with simultaneous prediction of control-flow instructions |
US6266755B1 (en) | 1994-10-14 | 2001-07-24 | Mips Technologies, Inc. | Translation lookaside buffer with virtual address conflict prevention |
US6343354B1 (en) * | 1996-06-07 | 2002-01-29 | Motorola Inc. | Method and apparatus for compression, decompression, and execution of program code |
US6412061B1 (en) * | 1994-05-23 | 2002-06-25 | Cirrus Logic, Inc. | Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection |
US20020083303A1 (en) * | 2000-09-01 | 2002-06-27 | Raimund Leitner | Program-controlled unit |
US20020156992A1 (en) * | 2001-04-18 | 2002-10-24 | Fujitsu Limited | Information processing device and computer system |
US6484228B2 (en) | 2000-04-19 | 2002-11-19 | Motorola, Inc. | Method and apparatus for data compression and decompression for a data processor system |
US6571328B2 (en) | 2000-04-07 | 2003-05-27 | Nintendo Co., Ltd. | Method and apparatus for obtaining a scalar value directly from a vector register |
US6591361B1 (en) | 1999-12-28 | 2003-07-08 | International Business Machines Corporation | Method and apparatus for converting data into different ordinal types |
US6594728B1 (en) | 1994-10-14 | 2003-07-15 | Mips Technologies, Inc. | Cache memory with dual-way arrays and multiplexed parallel output |
US6647467B1 (en) * | 1997-08-01 | 2003-11-11 | Micron Technology, Inc. | Method and apparatus for high performance branching in pipelined microsystems |
US6681296B2 (en) | 2000-04-07 | 2004-01-20 | Nintendo Co., Ltd. | Method and apparatus for software management of on-chip cache |
US6701424B1 (en) | 2000-04-07 | 2004-03-02 | Nintendo Co., Ltd. | Method and apparatus for efficient loading and storing of vectors |
US20040111594A1 (en) * | 2002-12-05 | 2004-06-10 | International Business Machines Corporation | Multithreading recycle and dispatch mechanism |
US20050001768A1 (en) * | 2003-05-29 | 2005-01-06 | Masami Sekiguchi | Surface mount antenna, and an antenna element mounting method |
US20050102483A1 (en) * | 2002-10-22 | 2005-05-12 | Kinter Ryan C. | Apparatus and method for discovering a scratch pad memory configuration |
US7035998B1 (en) | 2000-11-03 | 2006-04-25 | Mips Technologies, Inc. | Clustering stream and/or instruction queues for multi-streaming processors |
US20060230258A1 (en) * | 2005-02-28 | 2006-10-12 | Infineon Technologies Ag | Multi-thread processor and method for operating such a processor |
US20060242365A1 (en) * | 2005-04-20 | 2006-10-26 | Abid Ali | Method and apparatus for suppressing duplicative prefetches for branch target cache lines |
US7139898B1 (en) * | 2000-11-03 | 2006-11-21 | Mips Technologies, Inc. | Fetch and dispatch disassociation apparatus for multistreaming processors |
US20070101110A1 (en) * | 2005-10-31 | 2007-05-03 | Mips Technologies, Inc. | Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
US20070101111A1 (en) * | 2005-10-31 | 2007-05-03 | Mips Technologies, Inc. | Processor core and method for managing program counter redirection in an out-of-order processor pipeline |
US20070204135A1 (en) * | 2006-02-28 | 2007-08-30 | Mips Technologies, Inc. | Distributive scoreboard scheduling in an out-of order processor |
US20080016326A1 (en) * | 2006-07-14 | 2008-01-17 | Mips Technologies, Inc. | Latest producer tracking in an out-of-order processor, and applications thereof |
US20080046653A1 (en) * | 2006-08-18 | 2008-02-21 | Mips Technologies, Inc. | Methods for reducing data cache access power in a processor, and applications thereof |
US20080059771A1 (en) * | 2006-09-06 | 2008-03-06 | Mips Technologies, Inc. | Out-of-order processor having an in-order coprocessor, and applications thereof |
US20080059765A1 (en) * | 2006-09-06 | 2008-03-06 | Mips Technologies, Inc. | Coprocessor interface unit for a processor, and applications thereof |
US20080082721A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
US20080082794A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Load/store unit for a processor, and applications thereof |
US7370178B1 (en) | 2006-07-14 | 2008-05-06 | Mips Technologies, Inc. | Method for latest producer tracking in an out-of-order processor, and applications thereof |
US20080275464A1 (en) * | 2005-03-29 | 2008-11-06 | Boston Scientific Scimed, Inc. | Articulating retrieval device |
US7650465B2 (en) | 2006-08-18 | 2010-01-19 | Mips Technologies, Inc. | Micro tag array having way selection bits for reducing data cache access power |
US8078846B2 (en) | 2006-09-29 | 2011-12-13 | Mips Technologies, Inc. | Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated |
US20110320771A1 (en) * | 2010-06-28 | 2011-12-29 | International Business Machines Corporation | Instruction unit with instruction buffer pipeline bypass |
US20120069029A1 (en) * | 2010-09-20 | 2012-03-22 | Qualcomm Incorporated | Inter-processor communication techniques in a multiple-processor computing platform |
US9851975B2 (en) | 2006-02-28 | 2017-12-26 | Arm Finance Overseas Limited | Compact linked-list-based multi-threaded instruction graduation buffer |
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US6185676B1 (en) * | 1997-09-30 | 2001-02-06 | Intel Corporation | Method and apparatus for performing early branch prediction in a microprocessor |
US6243805B1 (en) * | 1998-08-11 | 2001-06-05 | Advanced Micro Devices, Inc. | Programming paradigm and microprocessor architecture for exact branch targeting |
US6289442B1 (en) * | 1998-10-05 | 2001-09-11 | Advanced Micro Devices, Inc. | Circuit and method for tagging and invalidating speculatively executed instructions |
US6442674B1 (en) * | 1998-12-30 | 2002-08-27 | Intel Corporation | Method and system for bypassing a fill buffer located along a first instruction path |
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US6546478B1 (en) | 1999-10-14 | 2003-04-08 | Advanced Micro Devices, Inc. | Line predictor entry with location pointers and control information for corresponding instructions in a cache line |
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US7281120B2 (en) * | 2004-03-26 | 2007-10-09 | International Business Machines Corporation | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor |
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US7426631B2 (en) * | 2005-02-02 | 2008-09-16 | International Business Machines Corporation | Methods and systems for storing branch information in an address table of a processor |
US20070198812A1 (en) * | 2005-09-27 | 2007-08-23 | Ibm Corporation | Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system |
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US10216520B2 (en) * | 2014-10-06 | 2019-02-26 | Via Technologies, Inc. | Compressing instruction queue for a microprocessor |
JP7004905B2 (en) * | 2018-03-26 | 2022-01-21 | 富士通株式会社 | Arithmetic processing unit and control method of arithmetic processing unit |
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US5954815A (en) | 1999-09-21 |
US20030033505A1 (en) | 2003-02-13 |
KR100212204B1 (en) | 1999-08-02 |
EP1320031A3 (en) | 2008-12-17 |
EP0690373A4 (en) | 1997-05-14 |
HK1013153A1 (en) | 1999-08-13 |
JP2815237B2 (en) | 1998-10-27 |
CN1492319A (en) | 2004-04-28 |
DE69433621D1 (en) | 2005-01-27 |
EP1320031A2 (en) | 2003-06-18 |
EP0690373B1 (en) | 2004-03-17 |
WO1995016954A1 (en) | 1995-06-22 |
EP0690373A1 (en) | 1996-01-03 |
US6691221B2 (en) | 2004-02-10 |
KR960701400A (en) | 1996-02-24 |
US6247124B1 (en) | 2001-06-12 |
CN1267819C (en) | 2006-08-02 |
CN1104680C (en) | 2003-04-02 |
DE69433621T2 (en) | 2005-05-12 |
CN1117765A (en) | 1996-02-28 |
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