US5670387A - Process for forming semiconductor-on-insulator device - Google Patents
Process for forming semiconductor-on-insulator device Download PDFInfo
- Publication number
- US5670387A US5670387A US08/368,673 US36867395A US5670387A US 5670387 A US5670387 A US 5670387A US 36867395 A US36867395 A US 36867395A US 5670387 A US5670387 A US 5670387A
- Authority
- US
- United States
- Prior art keywords
- forming
- insulating layer
- interconnects
- substrate
- interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 34
- 239000012212 insulator Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910052762 osmium Inorganic materials 0.000 claims description 3
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 7
- 230000004927 fusion Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- -1 RuO2 Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910019599 ReO2 Inorganic materials 0.000 description 1
- 229910002785 ReO3 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- YSZJKUDBYALHQE-UHFFFAOYSA-N rhenium trioxide Chemical compound O=[Re](=O)=O YSZJKUDBYALHQE-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (24)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/368,673 US5670387A (en) | 1995-01-03 | 1995-01-03 | Process for forming semiconductor-on-insulator device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/368,673 US5670387A (en) | 1995-01-03 | 1995-01-03 | Process for forming semiconductor-on-insulator device |
Publications (1)
Publication Number | Publication Date |
---|---|
US5670387A true US5670387A (en) | 1997-09-23 |
Family
ID=23452257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/368,673 Expired - Fee Related US5670387A (en) | 1995-01-03 | 1995-01-03 | Process for forming semiconductor-on-insulator device |
Country Status (1)
Country | Link |
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US (1) | US5670387A (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0981165A1 (en) * | 1998-08-20 | 2000-02-23 | Lucent Technologies Inc. | Thin film transistors |
US6194256B1 (en) | 1998-06-29 | 2001-02-27 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating CMOS device |
US6291858B1 (en) | 2000-01-03 | 2001-09-18 | International Business Machines Corporation | Multistack 3-dimensional high density semiconductor device and method for fabrication |
WO2001078141A2 (en) * | 2000-04-11 | 2001-10-18 | Micron Technology, Inc. | USE OF AlN AS COPPER PASSIVATION LAYER AND THERMAL CONDUCTOR |
US6326247B1 (en) | 2000-06-09 | 2001-12-04 | Advanced Micro Devices, Inc. | Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer |
EP1167281A2 (en) * | 2000-06-22 | 2002-01-02 | Samsung Electronics Co. Ltd. | Chip scale surface-mountable packaging method for electronic and MEMS devices |
US6358820B1 (en) * | 2000-04-17 | 2002-03-19 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
US6492209B1 (en) | 2000-06-30 | 2002-12-10 | Advanced Micro Devices, Inc. | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer |
US20030032262A1 (en) * | 2000-08-29 | 2003-02-13 | Dennison Charles H. | Silicon on insulator DRAM process utilizing both fully and partially depleted devices |
US20030047810A1 (en) * | 2001-09-10 | 2003-03-13 | Mitsubishi Denki Kabushiki Kaisha | Electronic device having multilayer interconnection structure |
US6544837B1 (en) | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
US20030067052A1 (en) * | 1999-06-30 | 2003-04-10 | Kabushiki Kaisha Toshiba | Integrated circuit device and method of manufacturing the same |
US20030139006A1 (en) * | 2000-04-28 | 2003-07-24 | Hartner Walter | Method for producing capacitor structures |
US20030203601A1 (en) * | 2000-06-22 | 2003-10-30 | Murata Manufacturing Co., Ltd. | Method for manufacturing semiconductor thin film, and magnetoelectric conversion element provided with semiconductor thin film thereby manufactured |
US20040016969A1 (en) * | 2002-07-29 | 2004-01-29 | Mark Bohr | Silicon on isulator (SOI) transistor and methods of fabrication |
FR2848724A1 (en) * | 2002-12-13 | 2004-06-18 | St Microelectronics Sa | Production of connections buried in substrate of integrated circuit gives diminished access resistance to electrode of transistor |
US6759282B2 (en) | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US20070122975A1 (en) * | 2005-11-28 | 2007-05-31 | Stmicroelectronics Crolles 2 Sas | MOS transistor manufacturing |
US7238591B1 (en) * | 2001-06-18 | 2007-07-03 | Advanced Micro Devices, Inc. | Heat removal in SOI devices using a buried oxide layer/conductive layer combination |
US20070202639A1 (en) * | 2004-12-14 | 2007-08-30 | International Business Machines Corporation | Dual stressed soi substrates |
Citations (15)
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US4376286A (en) * | 1978-10-13 | 1983-03-08 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US4385937A (en) * | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
US4490182A (en) * | 1980-10-07 | 1984-12-25 | Itt Industries, Inc. | Semiconductor processing technique for oxygen doping of silicon |
US4593302A (en) * | 1980-08-18 | 1986-06-03 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4704785A (en) * | 1986-08-01 | 1987-11-10 | Texas Instruments Incorporated | Process for making a buried conductor by fusing two wafers |
US4837177A (en) * | 1987-12-28 | 1989-06-06 | Motorola Inc. | Method of making bipolar semiconductor device having a conductive recombination layer |
US5025304A (en) * | 1988-11-29 | 1991-06-18 | Mcnc | High density semiconductor structure and method of making the same |
US5091330A (en) * | 1990-12-28 | 1992-02-25 | Motorola, Inc. | Method of fabricating a dielectric isolated area |
US5141889A (en) * | 1990-11-30 | 1992-08-25 | Motorola, Inc. | Method of making enhanced insulated gate bipolar transistor |
US5323059A (en) * | 1991-05-06 | 1994-06-21 | Motorola, Inc. | Vertical current flow semiconductor device utilizing wafer bonding |
US5346848A (en) * | 1993-06-01 | 1994-09-13 | Motorola, Inc. | Method of bonding silicon and III-V semiconductor materials |
US5387555A (en) * | 1992-09-03 | 1995-02-07 | Harris Corporation | Bonded wafer processing with metal silicidation |
US5449638A (en) * | 1994-06-06 | 1995-09-12 | United Microelectronics Corporation | Process on thickness control for silicon-on-insulator technology |
US5496764A (en) * | 1994-07-05 | 1996-03-05 | Motorola, Inc. | Process for forming a semiconductor region adjacent to an insulating layer |
US5499124A (en) * | 1990-12-31 | 1996-03-12 | Vu; Duy-Phach | Polysilicon transistors formed on an insulation layer which is adjacent to a liquid crystal material |
-
1995
- 1995-01-03 US US08/368,673 patent/US5670387A/en not_active Expired - Fee Related
Patent Citations (17)
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US4376286B1 (en) * | 1978-10-13 | 1993-07-20 | Int Rectifier Corp | |
US4376286A (en) * | 1978-10-13 | 1983-03-08 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US4385937A (en) * | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
US4593302A (en) * | 1980-08-18 | 1986-06-03 | International Rectifier Corporation | Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide |
US4593302B1 (en) * | 1980-08-18 | 1998-02-03 | Int Rectifier Corp | Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide |
US4490182A (en) * | 1980-10-07 | 1984-12-25 | Itt Industries, Inc. | Semiconductor processing technique for oxygen doping of silicon |
US4704785A (en) * | 1986-08-01 | 1987-11-10 | Texas Instruments Incorporated | Process for making a buried conductor by fusing two wafers |
US4837177A (en) * | 1987-12-28 | 1989-06-06 | Motorola Inc. | Method of making bipolar semiconductor device having a conductive recombination layer |
US5025304A (en) * | 1988-11-29 | 1991-06-18 | Mcnc | High density semiconductor structure and method of making the same |
US5141889A (en) * | 1990-11-30 | 1992-08-25 | Motorola, Inc. | Method of making enhanced insulated gate bipolar transistor |
US5091330A (en) * | 1990-12-28 | 1992-02-25 | Motorola, Inc. | Method of fabricating a dielectric isolated area |
US5499124A (en) * | 1990-12-31 | 1996-03-12 | Vu; Duy-Phach | Polysilicon transistors formed on an insulation layer which is adjacent to a liquid crystal material |
US5323059A (en) * | 1991-05-06 | 1994-06-21 | Motorola, Inc. | Vertical current flow semiconductor device utilizing wafer bonding |
US5387555A (en) * | 1992-09-03 | 1995-02-07 | Harris Corporation | Bonded wafer processing with metal silicidation |
US5346848A (en) * | 1993-06-01 | 1994-09-13 | Motorola, Inc. | Method of bonding silicon and III-V semiconductor materials |
US5449638A (en) * | 1994-06-06 | 1995-09-12 | United Microelectronics Corporation | Process on thickness control for silicon-on-insulator technology |
US5496764A (en) * | 1994-07-05 | 1996-03-05 | Motorola, Inc. | Process for forming a semiconductor region adjacent to an insulating layer |
Non-Patent Citations (2)
Title |
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Wolf; Silicon Processing for the VLSI ERA, vol. 2: Process Integration; Lattice Press; pp. 70 72 (1990), Month Unknown. * |
Wolf; Silicon Processing for the VLSI ERA, vol. 2: Process Integration; Lattice Press; pp. 70-72 (1990), Month Unknown. |
Cited By (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6194256B1 (en) | 1998-06-29 | 2001-02-27 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating CMOS device |
EP0981165A1 (en) * | 1998-08-20 | 2000-02-23 | Lucent Technologies Inc. | Thin film transistors |
US6933205B2 (en) * | 1999-06-30 | 2005-08-23 | Kabushiki Kaisha Toshiba | Integrated circuit device and method of manufacturing the same |
US20030067052A1 (en) * | 1999-06-30 | 2003-04-10 | Kabushiki Kaisha Toshiba | Integrated circuit device and method of manufacturing the same |
US6451634B2 (en) * | 2000-01-03 | 2002-09-17 | International Business Machines Corporation | Method of fabricating a multistack 3-dimensional high density semiconductor device |
US6291858B1 (en) | 2000-01-03 | 2001-09-18 | International Business Machines Corporation | Multistack 3-dimensional high density semiconductor device and method for fabrication |
US6590258B2 (en) | 2000-03-17 | 2003-07-08 | International Business Machines Corporation | SIO stacked DRAM logic |
US6544837B1 (en) | 2000-03-17 | 2003-04-08 | International Business Machines Corporation | SOI stacked DRAM logic |
US20020175362A1 (en) * | 2000-04-11 | 2002-11-28 | Mcteer Allen | Use of ALN as copper passivation layer and thermal conductor |
US20070042596A1 (en) * | 2000-04-11 | 2007-02-22 | Mcteer Allen | Method of forming an interconnect structure for a semiconductor device |
US7061111B2 (en) | 2000-04-11 | 2006-06-13 | Micron Technology, Inc. | Interconnect structure for use in an integrated circuit |
GB2378040A (en) * | 2000-04-11 | 2003-01-29 | Micron Technology Inc | Use of AIN as copper passivation layer and thermal conductor |
GB2378040B (en) * | 2000-04-11 | 2004-10-13 | Micron Technology Inc | Use of AIN as copper passivation layer and thermal conductor |
US7205223B2 (en) | 2000-04-11 | 2007-04-17 | Micron Technology, Inc. | Method of forming an interconnect structure for a semiconductor device |
US20070164442A1 (en) * | 2000-04-11 | 2007-07-19 | Micron Technology, Inc. | Use of AIN as cooper passivation layer and thermal conductor |
US7679193B2 (en) | 2000-04-11 | 2010-03-16 | Micron Technology, Inc. | Use of AIN as cooper passivation layer and thermal conductor |
WO2001078141A3 (en) * | 2000-04-11 | 2002-06-06 | Micron Technology Inc | USE OF AlN AS COPPER PASSIVATION LAYER AND THERMAL CONDUCTOR |
WO2001078141A2 (en) * | 2000-04-11 | 2001-10-18 | Micron Technology, Inc. | USE OF AlN AS COPPER PASSIVATION LAYER AND THERMAL CONDUCTOR |
US6358820B1 (en) * | 2000-04-17 | 2002-03-19 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
US20030139006A1 (en) * | 2000-04-28 | 2003-07-24 | Hartner Walter | Method for producing capacitor structures |
US6326247B1 (en) | 2000-06-09 | 2001-12-04 | Advanced Micro Devices, Inc. | Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer |
EP1167281A2 (en) * | 2000-06-22 | 2002-01-02 | Samsung Electronics Co. Ltd. | Chip scale surface-mountable packaging method for electronic and MEMS devices |
US20030203601A1 (en) * | 2000-06-22 | 2003-10-30 | Murata Manufacturing Co., Ltd. | Method for manufacturing semiconductor thin film, and magnetoelectric conversion element provided with semiconductor thin film thereby manufactured |
EP1167281A3 (en) * | 2000-06-22 | 2003-03-19 | Samsung Electronics Co. Ltd. | Chip scale surface-mountable packaging method for electronic and MEMS devices |
US6492209B1 (en) | 2000-06-30 | 2002-12-10 | Advanced Micro Devices, Inc. | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer |
US6537891B1 (en) | 2000-08-29 | 2003-03-25 | Micron Technology, Inc. | Silicon on insulator DRAM process utilizing both fully and partially depleted devices |
US20030032262A1 (en) * | 2000-08-29 | 2003-02-13 | Dennison Charles H. | Silicon on insulator DRAM process utilizing both fully and partially depleted devices |
US6818496B2 (en) | 2000-08-29 | 2004-11-16 | Micron Technology, Inc, | Silicon on insulator DRAM process utilizing both fully and partially depleted devices |
US6759282B2 (en) | 2001-06-12 | 2004-07-06 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US20050214988A1 (en) * | 2001-06-12 | 2005-09-29 | Campbell John E | Method and structure for buried circuits and devices |
US20050029592A1 (en) * | 2001-06-12 | 2005-02-10 | Campbell John E. | Method and structure for buried circuits and devices |
US7141853B2 (en) | 2001-06-12 | 2006-11-28 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US7491588B2 (en) | 2001-06-12 | 2009-02-17 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US7320918B2 (en) | 2001-06-12 | 2008-01-22 | International Business Machines Corporation | Method and structure for buried circuits and devices |
US20070128784A1 (en) * | 2001-06-12 | 2007-06-07 | Campbell John E | Method and structure for buried circuits and devices |
US7238591B1 (en) * | 2001-06-18 | 2007-07-03 | Advanced Micro Devices, Inc. | Heat removal in SOI devices using a buried oxide layer/conductive layer combination |
US20030047810A1 (en) * | 2001-09-10 | 2003-03-13 | Mitsubishi Denki Kabushiki Kaisha | Electronic device having multilayer interconnection structure |
US6919238B2 (en) * | 2002-07-29 | 2005-07-19 | Intel Corporation | Silicon on insulator (SOI) transistor and methods of fabrication |
US20040016969A1 (en) * | 2002-07-29 | 2004-01-29 | Mark Bohr | Silicon on isulator (SOI) transistor and methods of fabrication |
US20040145058A1 (en) * | 2002-12-13 | 2004-07-29 | Michel Marty | Buried connections in an integrated circuit substrate |
FR2848724A1 (en) * | 2002-12-13 | 2004-06-18 | St Microelectronics Sa | Production of connections buried in substrate of integrated circuit gives diminished access resistance to electrode of transistor |
US20070202639A1 (en) * | 2004-12-14 | 2007-08-30 | International Business Machines Corporation | Dual stressed soi substrates |
US7312134B2 (en) * | 2004-12-14 | 2007-12-25 | International Business Machines Corporation | Dual stressed SOI substrates |
FR2894069A1 (en) * | 2005-11-28 | 2007-06-01 | St Microelectronics Crolles 2 | Metal oxide semiconductor transistor manufacture for random access static memory, by forming vias contacting a gate and source and drain regions on other side of channel region with respect to the gate |
US20070122975A1 (en) * | 2005-11-28 | 2007-05-31 | Stmicroelectronics Crolles 2 Sas | MOS transistor manufacturing |
US7556995B2 (en) | 2005-11-28 | 2009-07-07 | Stmicroelectronics Crolles 2 Sas | MOS transistor manufacturing |
US20090224295A1 (en) * | 2005-11-28 | 2009-09-10 | Stmicroelectronics (Crolles) 2 Sas | Mos transistor manufacturing |
US7915110B2 (en) | 2005-11-28 | 2011-03-29 | Stmicroelectronics (Crolles 2) Sas | MOS transistor manufacturing |
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