US5691550A

US5691550A - Semiconductor device and method of manufacturing the same

Info

Publication number: US5691550A
Application number: US08/430,287
Authority: US
Inventors: Yusuke Kohyama
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1992-03-30
Filing date: 1995-04-28
Publication date: 1997-11-25
Anticipated expiration: 2014-11-25
Also published as: EP0563879B1; EP0563879A1; JP2904635B2; JPH0629485A; KR930020588A; DE69331534T2; DE69331534D1; KR0178800B1; US5959324A

Abstract

A semiconductor device includes a first N-type region formed in a P-type silicon substrate, trenches formed in the substrate, second N-type regions each formed from at least the bottom of a corresponding one of the trenches into the substrate, these second N-type regions contacting each other to constitute a wiring layer and being also in contact with the first N-type region, and an electrode for applying a predetermined potential to the second N-type regions via the first N-type region. Since a potential is supplied to the wiring layer formed in the substrate via the first N-type region, no special design, such as formation of a terminal trench, is required. A potential can be easily supplied to the wiring layer formed in the semiconductor substrate, and the device can be easily fabricated.

Description

This application is a continuation of Ser. No. 08/038,278 filed Mar. 29, 1993 now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device with an internal wiring layer and a method of fabricating the same.

2. Description of the Related Art

Conventional examples of a semiconductor device with a wiring layer in a semiconductor substrate are a dynamic RAM cell disclosed in "A 4.2 μm² Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate-Wiring" T. Kaga et al., International Electron Devices Meeting Technical Digest, 1987, pp. 332 to 335 and a dynamic RAM cell disclosed in "Semiconductor Memory Having Trench Capacitor Formed with Sheath Electrode" U.S. Pat. No. 4,918,502 to T. Kaga et al.

Each DRAM cell disclosed in the above literature has an N-type diffusion layer formed by diffusion into a P-type substrate from the bottom of each trench formed in the P-type substrate. These N-type diffusion layers are electrically connected with each other by contacting each other to thereby constitute a wiring layer inside the substrate. This wiring layer in the above DRAM cell functions as a wire for applying a potential to the plate electrode of a capacitor. In this DRAM cell, however, the wiring layer is formed inside the substrate. Therefore, applying a potential to this wiring layer requires a specific design: one of trenches is caused to serve as an exclusive terminal for the potential supply. For this reason, in the above cell, one trench is caused to serve as a terminal (to be referred to as a "terminal trench" hereinafter) as follows. An oxide film is formed on the side walls of a trench in order to constitute a so-called "sheath capacitor." In the terminal trench, this oxide film is removed by photolithography and an N-type diffusion layer is formed on the entire surfaces of the trench. This N-type diffusion layer is formed in contact with N-type diffusion layers formed by diffusion from the bottoms of the other trenches to together serve as a wiring layer. A potential is supplied to these N-type diffusion layers serving as a wiring layer from the diffusion layer formed on the entire surfaces of the terminal trench. The device of this type is described in, e.g., U.S. Pat. No. 4,918,502 with reference to FIGS. 10D to 10N.

In a semiconductor device having a wiring layer inside a semiconductor substrate, it is not easy to apply a potential to the wiring layer. To supply a potential, therefore, a special design such as formation of a terminal trench 1 as shown in FIGS. 1 and 2 is used. This requires an additional photolithography step or the like, and the result is complexity in the whole fabrication process. Especially in formation of the terminal trench 1, a resist 5 must be removed from the terminal trench 1 in order to selectively remove an oxide film 6 on the side surfaces of the trench 1. In this case, if misalignment of patterns occurs as indicated by a resist 5' in FIG. 1, a disconnected portion 8a is formed between an N-type diffusion layer 8 around the terminal trench 1 and an N-type diffusion layer 7 at the bottom of a trench 2, preventing these diffusion 10 layers from making contact with each other. In addition, it is highly probable that the resist 5 is not completely removed but left behind in the terminal trench 1. If the resist 5 remains in the terminal trench 1, the oxide film 6 is not completely removed, and an unremoved portion 6a remains on the wall surface of the terminal trench 1, as shown in FIG. 2. This residual oxide film 6a acts as a diffusion mask to cause, e.g., a diffusion error 8b. The diffusion error 8b introduces problems such as a disconnection in the N-type diffusion layer 8 or an increase in contact resistance between the wiring layer and the terminal. In addition, if the resist remains in the terminal trench, harmful impurities (such as heavy metals) contained in the resist may diffuse into the device to contaminate it. Note that reference numeral 3 denotes an element isolating SiO₂ film; 4, an Si₃ N₄ film; and 10, a P-type semiconductor substrate.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the above situation and has its object to provide a semiconductor device with a structure, in which a potential can be easily supplied to a wiring layer formed in a semiconductor substrate, and which can be easily fabricated, and a method of fabricating the same.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type formed in the semiconductor substrate; a plurality of trenches formed adjacent to each other in the semiconductor substrate, an end of the plurality of trenches being formed at a predetermined position with respect to the first semiconductor region; and a plurality of second semiconductor regions of the second conductivity type each formed from at least the bottom of a corresponding one of the plurality of trenches into the semiconductor substrate, the second semiconductor regions contacting each other to constitute a wiring layer and being also in contact with the first semiconductor region.

According to another aspect of the present invention, there is provided a dynamic RAM comprising: a semiconductor substrate of a first conductivity type; a deep well-like first semiconductor region of a second conductivity type formed in the semiconductor substrate; a plurality of trenches of a predetermined depth formed adjacent to each other with predetermined intervals therebetween, one end of the plurality of trenches being formed at a predetermined position with respect to the first semiconductor region; a plurality of second semiconductor regions of the second conductivity type each formed from at least the bottom of a corresponding one of the plurality of trenches into the semiconductor substrate, the plurality of second semiconductor regions contacting each other and being also in contact with the first semiconductor region; a plurality of capacitors formed inside the plurality of trenches, one end of one electrode of the capacitors being connected to the second semiconductor regions; cell transistors each having source/drain regions of the second conductivity type and a gate electrode connected to a word line, one of the source/drain regions being connected to the other electrode of the capacitors; and a bit line electrically connected to the other region of the source/drain regions of the cell transistor.

According to still another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of: forming a well-like first semiconductor region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a plurality of trenches adjacent to each other in the semiconductor substrate such that an end portion of the plurality of trenches is formed at a predetermined position with respect to the first semiconductor region; doping an impurity of the second conductivity type from bottom portions of the plurality of trenches into the semiconductor substrate; and diffusing the impurity to form a plurality of second semiconductor regions of the second conductivity type in the semiconductor substrate such that the plurality of second semiconductor regions are electrically connected to each other and also connected to the first semiconductor region.

According to still another aspect of the present invention, there is provided a method of fabricating a dynamic RAM, comprising the steps of: forming a deep well-like first semiconductor region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a shallow well-like second semiconductor region of the first conductivity type in the semiconductor substrate; forming a plurality of trenches adjacent to each other with predetermined intervals therebetween such that one end portion of the plurality of trenches is formed at a predetermined position with respect to the first semiconductor region; doping an impurity of the second conductivity type from bottom portions of the plurality of trenches into the semiconductor substrate to form a plurality of regions doped with the impurity of the second conductivity; diffusing the impurity of the impurity-doped regions by annealing to form a plurality of impurity-diffused layers such that the plurality of impurity-diffused layers contact each other and are also in contact with the first semiconductor region; forming capacitors in the trenches; forming a cell transistor a gate electrode of which is connected to the second semiconductor region; forming bit lines connected to one of source/drain regions of the cell transistor; and forming insulating interlayers on the entire surface and forming an electrode layer for supplying a potential to the plurality of impurity-diffused layers.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the Specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a schematic sectional view for explaining a drawback of a conventional semiconductor device;

FIG. 2 is a schematic sectional view for explaining another drawback of a conventional semiconductor device;

FIG. 3 is a sectional view showing the arrangement of a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing the arrangement of a semiconductor device according to the second embodiment of the present invention;

FIGS. 5A to 5C are sectional views for explaining the arrangement of a semiconductor device according to the third embodiment of the present invention; and

FIGS. 6A-I to 6G-III are sectional views for explaining a method of fabricating the semiconductor device according to the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of a semiconductor device and a method of fabricating the same according to the present invention will be described below with reference to the accompanying drawings.

FIG. 3 is a sectional view showing the arrangement of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 3, trenches 12₁ to 12_N are formed in, e.g., a P-type silicon substrate 10. In the substrate 10, N-type diffusion layers 14₁ to 14_N are formed from the bottoms of the trenches 12₁ to 12_N, respectively, by ion implantation or diffusion of an impurity. The N-type diffusion layers 14₁ to 14_N are electrically connected to each other by contacting each other, thereby constituting a buried wiring layer 16 formed inside the substrate 10. In addition, a well-like N-type region 18 is formed in the substrate 10 by ion implantation or by diffusing an impurity from the surface of the substrate 10. This N-type region 18 serves as a potential extracting electrode. This N-type region 18 is electrically connected to the wiring layer 16 and is also electrically connected to an electrode layer 20. Although not shown, an element such as a capacitor having an electrode electrically connected to the wiring layer 16 is formed in each of the trenches 12₁ to 12_N. According to the semiconductor device with the above arrangement, a potential is supplied from a power supply to the wiring layer 16 via the electrode layer 20 and the N-type region 18. This makes potential supply to the wiring layer 16 feasible without forming any special structure, such as a terminal trench, unlike in conventional structures. In addition, the N-type region 18 can be formed not through a complicated step, such as removal of a resist from a trench, but by ion implantation or diffusion of an impurity from the surface of the substrate 10, so the formation of this region is easy. This can reduce occurrence of errors in fabrication and consequently can prevent a reduction in yield of devices. Furthermore, the N-type region 18 can be formed simultaneously with formation of an N-type well region (not shown) or an N-type collector extracting region (not shown) used in a vertical bipolar transistor. This simultaneous formation of the N-type region 18 and the N-type well region or the N-type collector extracting region can suppress an increase in the number of fabrication steps.

FIG. 4 is a sectional view showing the arrangement of a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 4, at least one trench 12₀ is formed in a well-like N-type region 18 by the same fabrication steps as for other trenches 12₁ to 12_N. According to the semiconductor device with this arrangement, even if mask misalignment occurs in the formation of the trenches 12₀ to 12_N, contact between the N-type region 18 and a wiring layer 16 can be maintained because an N-type diffusion layer 14₀ at the bottom of the trench 12₀ exists in the N-type region 18. This ensures electrical connection between the N-type region 18 and the wiring layer 16 at any instant.

FIGS. 5A to 5C are sectional views for explaining the arrangement of a semiconductor device according to the third embodiment of the present invention. In the third embodiment, a semiconductor device according to the present invention is applied to a dynamic RAM with a sheath capacitor and a peripheral circuit constituted by a CMOS circuit. FIG. 5A is a sectional view showing the device according to the third embodiment, FIG. 5B is an enlarged view showing a portion near a buried wiring layer connecting portion b in FIG. 5A, and FIG. 5C is an enlarged view showing a portion near a sheath capacitor portion c in FIG. 5A. N-

type wells

18₁ and 18₂, an N-type well 22, and a P-type well 24₁ are formed in a P-type silicon substrate 10, and a P-type well 24₂ is formed in this N-type well 18₂. In a memory array formation portion of the N-type well 18₁ and a P-type well 24₁, a memory cell having a cell transistor, that includes an electrode layer 88₁ for supplying a potential from a first potential source (V_bb), and sheath capacitors supplied with a potential from an electrode layer 20 via the extracting electrode layer 18₁ and a buried wiring layer 16 are formed. A peripheral circuit PMOS having an electrode layer 88₂ for supplying a potential from a second potential source (V_cc) is formed in the N-type well 22. A peripheral circuit NMOS having an electrode 88₃ for supplying a potential from a third potential source (V_ss) is formed in the P-type well 24₂. As shown in FIG. 5B, the buried wiring layer 16 is constituted by N-type impurity-diffused layers 14₀ to 14_N formed in contact with each other at the bottoms of trenches 12₀ to 12_N, respectively. A portion each of the diffusion layers 14₀ to 14_N is formed in the extracting electrode layer 18₁. As shown in FIG. 5C, the sheath capacitors are constituted by a plate electrode 38, a storage node electrode 42, and a 10 dielectric film 40 formed between them, all formed in the trenches 12₀ to 12_N.

FIGS. 6A-I to 6G-III are sectional views for explaining a method of fabricating the semiconductor device according to the third embodiment of the present invention. FIGS. 6A-II and 6A-III respectively illustrate an enlarged view of a portion near a buried wiring layer connecting portion b in FIG. 6A-I, and an enlarged view of a portion near a sheath capacitor portion c in FIG. 6A-I. Similarly, FIGS. 6B-II through 6G-II and 6B-III through 6G-III illustrate similar portions b and c of the structure shown in FIGS. 6B-I through 6G-I respectively. First, as shown in FIG. 6A-I, deep N-

type well regions

18₁ and 18₂ are formed in a P-type silicon substrate 10 by, e.g., ion implantation and diffusion. Subsequently, an N-type well 22 and P-

type wells

24₁ and 24₂ are formed in the substrate 10 by, e.g., ion implantation and diffusion. A field oxide film 26 is formed on the substrate 10 by, e.g., a LOCOS process. FIG. 6A-II is an enlarged view showing a portion near a buried wiring layer connecting portion b, and FIG. 6A-III is an enlarged view showing a portion near a sheath capacitor portion c. This will be the same in the following description.

As shown in FIGS. 6B-I to 6B-III, a thin silicon oxide (SiO₂) film 28 is formed on the substrate 10 by using, e.g., a thermal oxidation process or a CVD process. Subsequently, a silicon nitride (SiN_x) film 30 is formed on the oxide film 28 by, e.g., the CVD process. A plurality of trenches 12₀ to 12_N about 3 μm in depth are formed adjacent to each other with predetermined intervals between them in the substrate 10 by, e.g., photolithography and RIE. The trenches 12₀ to 12_N are formed particularly in a memory cell array formation portion of the substrate 10, i.e., a region where the P-type well 24₁ is formed. The trenches 12₀ to 12_N are so formed as to reach the substrate 10 through the edge of the field oxide film 26 and the P-type well 24_l, and at least one trench 12₀ is formed in the deep N-type well 181. Subsequently, a silicon oxide (SiO₂) film 32 with a thickness of about 50 nm is formed on the entire upper surface of the substrate 10 by using, e.g., the CVD process. The silicon oxide film 32 is then etched back by RIE to remain on only the side walls of the trenches 12₀ to 12_N. The results are cylindrical portions consisting of the silicon oxide film 32 about 50 nm thick. Subsequently, an N-type impurity, such as phosphorus (P), is doped at a dose of about 1×10¹⁶ cm^-2 by, e.g., ion implantation. Consequently, N-type impurity-implanted regions 34₀ to 34_N are formed in portions of the substrate 10 exposed to the bottoms of the trenches 12₀ to 12_N, respectively. This ion implantation step is performed by using the nitride film 30 and the side-wall insulating film 32 as masks.

As shown in FIGS. 6C-I to 6C-III, a phosphorus-doped N-type polysilicon film 30 is formed on the entire upper surface of the substrate 10 including the side and bottom surfaces of the trenches 12₀ to 12_N by using, e.g., the CVD process. Subsequently, annealing is performed to activate the phosphorus present in the impurity-implanted regions 34₀ to 34_N, forming N-type diffusion layers 14₀ to 14_N. These diffusion layers 14₀ to 14_N are so diffused into the substrate 10 as to contact each other, thereby constituting a buried wiring layer 16. The wiring layer 16 is also formed in contact with the deep N-type well 18₁ and is consequently electrically connected with the N-type well 18₁. Subsequently, a photoresist is coated on the entire upper surface of the substrate 10. The photoresist is then exposed to the middle levels of the trenches 12₀ to 12_N by full-surface exposure, and the exposed portion of the photoresist is removed. The result is a photoresist layer 36 buried to the middle levels of the trenches 12₀ to 12_N. Subsequently, the polysilicon film 38 is removed by using the photoresist layer 36 as a mask. As a result, as shown in FIGS. 6C-II and 6C-III in an enlarged scale, polysilicon films 38₀ to 38_N formed to the middle levels of the trenches 12₀ to 12_N are obtained. The polysilicon films 38₀ to 38_N are electrically connected to the wiring layer 16 to serve as the plate electrodes of sheath capacitors.

As shown in FIGS. 6D-I to 6D-III, the photoresist 0layer 36 formed on the bottoms of the trenches 12₀ to 12_N is removed. Thereafter, a stacked insulating film 40 consisting of an oxide film (SiO₂) and a nitride film (SiN_x) and having a thickness of about 5 nm, as a thickness of an oxide film, is formed on the polysilicon films 38₀ to 38_N by using, e.g., the CVD process or a thermal oxidation/thermal nitriding process. This stacked insulating film 40 serves as the dielectric film of a sheath capacitor. Subsequently, a phosphorus-doped N-type polysilicon film 42 is formed on the entire upper surface of the substrate 10 by, e.g., the CVD process. This polysilicon film is then etched back to remain to the middle levels of the trenches 12₀ to 12_N. Consequently, polysilicon films 42₀ to 42_N are formed. These polysilicon films 42₀ to 42_N serve as the storage-node electrodes of sheath capacitors. Subsequently, a photoresist 44 is coated on the entire upper surface of the substrate 10. Windows 46₁ and 46₂ are formed in portions of the photoresist 44, which serve as storage-node connecting portions. As shown in FIG. 6D-III, the sheath (silicon dioxide film) (SiO₂) 32 and the stacked insulating film 40 are partially removed by RIE by using the photoresist 44 and the polysilicon films 42_N-1 and 42_N as masks. The results are storage-node connecting portions 48₁ and 48₂ in which the P-type well 24₁ is exposed to the side surfaces of the

trenches

12_N-1 and 12_N.

As shown in FIGS. 6E-I to 6E-III, after the photoresist 44 is removed, an N-type impurity, such as phosphorus (P) or arsenic (As), is doped from the connecting portions 48₁ and 48₂ into the well 24₁ by the use of, e.g., ion implantation. As a result, N-type regions 50₁ and 50₂ are formed in the P-type well 24₁. Subsequently, a phosphorus-doped N-type polysilicon film 52 is formed on the entire upper surface of the substrate 10 by using, e.g., the CVD process. This polysilicon film is then etched back to remain to the middle levels of the trenches 12₀ to 12_N, thereby forming polysilicon films 52₀ to 52_N. The N-type regions 50₁ and 50₂ and the polysilicon films 42_N-1 and 42_N are electrically connected with each other via the

polysilicon films

52_N-1 and 52_N, respectively. Note that the N-type regions 50₁ and 50₂ may also be formed by diffusion of an impurity from the

polysilicon films

52_N-1 and 52_N, respectively.

As shown in FIGS. 6F-I to 6F-III, the surface regions of the polysilicon films 52₀ to 52_N are oxidized by, e.g., thermal oxidation by using the nitride film 30 as a mask, thereby forming silicon oxide (SiO₂) films 54₀ to 54_N. Consequently, the sheath-like oxide films 32 and 54₀ to 54_N are formed on the inner side walls and top of the trenches 12₀ to 12_N. The obtained capacitors are sheath capacitors formed inside the trenches 12₀ to 12_N covered with the sheath-like oxide films 32 and 54₀ to 54_N. In the third embodiment of the present invention, therefore, the capacitors of the same arrangement are formed inside the individual trenches, and no terminal trench with a specific internal arrangement exists.

As shown in FIGS. 6G-I to 6G-III, the oxide film 28, the nitride film 30, and exposed portions of the stacked insulating film 40 are removed. Subsequently, the surfaces of element formation regions of, e.g., the N-type well 22 and the P-

type wells

24₁ and 24₂ are subjected to, e.g., thermal oxidation to form gate oxide (SiO₂) films 58₁, 56, and 58₂. A conductive layer consisting of, e.g., N-type polysilicon or a silicide is formed on the entire upper surface of the substrate 10 by using, e.g., the CVD process and patterned to form word lines 60₁ to 60₃ on the memory cell array region and gates 62₁ and 62₂ on the peripheral circuit region. Subsequently, an N-type impurity, such as phosphorus or arsenic, is ion-implanted into the P-

type wells

24₁ and 24₂ by using a resist (not shown) or the like as a mask, thereby forming N-type source/drain regions 70₁, 70₂ and 70₃ of a cell transistor, and N-type source and drain regions 72₁ and 72₂ of an N-channel MOSFET as a peripheral circuit and N-

type contact regions

76₁ and 76₂. The N-type source/drain regions 70₁ and 70₂ are formed in contact with the N-type regions 50₁ and 50₂, respectively, and are thereby electrically connected with each other. After the resist is removed, a new resist (not shown) or the like is formed, and a P-type impurity, such as boron, is ion-implanted into the N-type well 22 by using this new resist as a mask. The results are P-type source and drain regions 74₁ and 74₂ of a p-channel MOSFET as a peripheral circuit and P-

type contact regions

78₁ and 78₂.

Subsequently, as shown in FIGS. 5A to 5C, an insulating interlayer 80 consisting of, e.g., a silicon oxide (SiO₂) film is formed on the substrate 10 by using the CVD process or the like. Contact holes reaching the N-type source/drain region 70₃ and the like are then formed in the insulating interlayer 80. A conductive layer consisting of, e.g., a silicide or an aluminum alloy is formed on the insulating interlayer 80 by, e.g., the CVD process or sputtering and patterned to form a wiring layer 82 such as bit lines. Subsequently, an insulating interlayer 84 consisting of, e.g., a silicon oxide (SiO₂) film is formed on the insulating interlayer 80 so as to cover the wiring layer 82 by using, e.g., the CVD process. Contact holes reaching the N-

type contact regions

76₁ and 76₂, the P-

type contact regions

78₁ and 78₂, and the like are formed in the insulating

interlayers

80 and 84. A conductive layer consisting of, e.g., an aluminum alloy is formed on the insulating interlayer 84 by sputtering or the like and patterned to form an electrode layer 20 for supplying a potential to the wiring layer 16, several different wiring layers 86₁ to 86₃, and electrode layers 88₁ to 88₃ for supplying a potential to the individual wells. The device according to the third embodiment of the present invention is fabricated through the above steps.

According to the dynamic RAM having the sheath capacitors with the above arrangement, a predetermined potential, such as a half-VCC-level potential, can be supplied to the wiring layer 16 via the N-type well 18₁. In addition, it is possible to omit the step of forming a terminal trench, which is a problem in formation of conventional devices of this type, from the fabrication steps of the present invention. This makes unnecessary the photolithography step of removing an oxide film from the side surfaces of a terminal trench, eliminating the problem of a residual oxide film. This can solve problems, such as an increase in contact resistance between a wiring layer and a terminal. Furthermore, the above fabrication steps can reduce the probability of a resist remaining in a trench compared to the fabrication steps for conventional devices and can also minimize a problem of contamination due to impurities.

The dynamic DRAM described in the above third embodiment can also be operated to achieve the effects equivalent to those of the dynamic DRAM introduced in, e.g., "Process Technologies for A High Speed 16M DRAM with Trench Type Cell" S. Yoshikawa et al., Symposium on VLSI Technology Digest of Technical Papers, 1989, pp. 67 and 68. That is, in the dynamic RAM described in the third embodiment, the deep N-type well 18₂ is formed in the P-type silicon substrate 10. Therefore, this dynamic DRAM can also be operated in the same fashion as a dynamic RAM with a triple-well structure by supplying a potential Vbb to the electrode layer 88₁, a potential vcc (power supply voltage) to the electrode layer 88₂, a potential vss to the electrode layer 88₃, and a potential Vcc/2 (plate potential) to the electrode layer 20. This consequently improves the circuit performance.

According to the present invention as has been described above, there are provided a semiconductor device with a structure, in which a potential can be easily supplied to a wiring layer formed in a semiconductor substrate, and which can be easily formed, and a method of fabricating the same.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims

What is claimed is:

1. A dynamic random access memory, comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a major surface of said semiconductor substrate, said first well region having a first width between the two edges of said first well region and half way between the top and bottom surfaces of said first well region;

a first trench formed in a major surface of the first well region, said first trench entirely formed within said first well region, wherein sidewalls of said first trench are in contact with an insulating film;

a plurality of second trenches formed in said major surface of the semiconductor substrate, wherein sidewalls of each of said second trenches are provided with an insulating film;

at least one third trench formed in said major surface of the semiconductor substrate, said third trench located between said first trench and said second trenches, wherein sidewalls of said third trench are provided with an insulating film;

semiconductor regions formed at the bottom of said first trench, said second trenches and said third trench respectively, and within said first well region and said semiconductor substrate, said semiconductor regions each having a width between the two edges of one of said semiconductors region and half way between the top and bottom surfaces of said one of said semiconductor regions less than said first width, and said semiconductor regions contacting each other to form a wiring layer;

capacitors respectively formed in said first trench, said second trenches and said third trench, wherein each of said capacitors has a first electrode and a second electrode insulated from each other, and wherein each of said first electrodes is connected to said wiring layer;

cell transistors formed in said major surface of said semiconductor substrate, each cell transistor having a gate electrode and source/drain regions of the second conductivity type, wherein a first source/drain region of each of said cell transistors is respectively connected to the second electrode of only those of said capacitors formed in said second trenches; and

a bit line electrically connected to a second source/drain region of each of said cell transistors.

2. A device according to claim 1, further comprising an electrode, electrically connected to said first well region, for applying a predetermined potential to said semiconductor regions via said first well region.

3. A DRAM according to claim 1, wherein each of said capacitors comprise:

a side wall insulating film formed on only side walls of each of said first, second, and third trenches;

a first conductive film of the second conductivity type formed on a bottom of each of said first, second, and third trenches and said side wall insulating films extend to a first predetermined depth in said first, second, and third trenches, said first conduction film serving as said first electrode;

a first insulating film formed on said first conductive dielectric film; and

a second conductive film of the second conductivity type formed on said first insulating film to a second predetermined depth in each of said first,second, third trenches and serving as said second electrode.

4. A DRAM according to claim 1, wherein said cell transistors are formed in a second well region of the first conductivity type formed in said semiconductor substrate.

5. A DRAM according to claim 1, further comprising:

a first peripheral circuit MOS transistor with a channel of the first conductivity type formed in a second well region of the second conductivity type in said semiconductor substrate and having a gate electrode and source/drain regions of the first conductivity type; and

a second peripheral circuit MOS transistor with a channel of the second conductivity type formed in a third well region of the first conductivity type electrically isolated from said semiconductor substrate and having a gate electrode and source/drain regions of the second conductivity type.

6. A DRAM according to claim 5, further comprising:

insulating interlayers formed on the upper surfaces of said capacitors, said cell transistors, and said first and second peripheral circuit MOS transistors;

a first electrode layer for supplying a first predetermined potential to said major surface of said semiconductor substrate near one of said cell transistors,

a second electrode layer for supplying a second predetermined potential to said second well region;

a third electrode layer for supplying a third predetermined potential to said third well region; and

a fourth electrode layer for supplying a fourth predetermined potential to said plurality of semiconductor regions via said first well region.

7. A dynamic random access memory comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a major surface of said semiconductor substrate, said first well region having a first width between the two edges of said first well region and half way between the top and bottom surfaces of said well region and a first depth;

at least one third trench formed in said major surface of the semiconductor substrate, said third trench located between said first well region and said second trenches, wherein sidewalls of said third trench are provided with an insulating film;

a plurality of semiconductor regions of the second conductivity type respectively formed at the bottoms of said first trench, said second trenches and said third trench, said plurality of semiconductor regions each having a width between the two edges of one of said semiconductor regions and half way between the top and bottom surfaces of said one of said semiconductor regions less than said first width, wherein said plurality of semiconductor regions contact each other to form a wiring layer, wherein a portion of one of said plurality of semiconductor regions formed at the bottom of said first trench is within said first well region, and wherein a number of said plurality of semiconductor regions formed at the bottoms of said second trenches are within said semiconductor substrate;

a plurality of capacitors each having first and second electrodes insulated from each other, each of said capacitors respectively formed in said first trench, said second trenches and said third trench, wherein each of said first electrodes is connected to said wiring layer;

cell transistors each having source/drain regions of the second conductivity type and a gate electrode connected to a word line, one of said source/drain regions of each of said cell transistors being connected to said second electrode of only those of said capacitors formed in said second trenches;

a second well region of the first conductivity type formed in said semiconductor substrate and having a second depth less than said first depth, said cell transistors being formed in said second well region;

a bit line electrically connected to the other of said source/drain regions of each of said cell transistors;

a third well region of the second conductivity type formed in said semiconductor substrate;

a first peripheral circuit MOS transistor with a channel of the first conductivity type formed in said third well region and having a gate electrode, and source/drain regions of the first conductivity type;

a fourth well region of the second conductivity type formed in said semiconductor substrate and having said first depth;

a fifth well region of the first conductivity type formed in said fourth well region and having said second depth; and

a second peripheral circuit MOS transistor with a channel of the second conductivity type formed in said fifth well region and having a gate electrode, and source/drain regions of the second conductivity type.

8. A dynamic random access memory, comprising:

a semiconductor substrate of a first conductivity type;

a plurality of second trenches formed in said major surface of the semiconductor substrate, wherein sidewalls of each of aid second trenches are provided with an insulating film;

a third trench formed in said major surface of the semiconductor substrate, said third trench located between said first well region and said second trenches, wherein sidewalls of said third trench are provided with an insulating film;

semiconductor regions formed at the bottoms of said first trench, said second trenches and said third trench respectively, said semiconductor regions each having a width between the two edges of one of said semiconductor regions and half way between the top and bottom surfaces of said one of said semiconductor regions less than said first width, and said semiconductor regions contacting each other to form a wiring layer;

cell transistors formed in said major surface of said semiconductor substrate, each cell transistor having a gate electrode and source/drain regions of the second conductivity type, a first source/drain region of each of said cell transistors connected respectively to one of said second electrodes of only those of said capacitors formed in said second trenches;

a bit line electrically connected to a second source/drain region of each of said cell transistors; and

an electrode, electrically connected to said first well region, for supplying a predetermined potential to said wiring layer via said first well region.