US5796670A - Nonvolatile dynamic random access memory device - Google Patents
Nonvolatile dynamic random access memory device Download PDFInfo
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- US5796670A US5796670A US08/745,101 US74510196A US5796670A US 5796670 A US5796670 A US 5796670A US 74510196 A US74510196 A US 74510196A US 5796670 A US5796670 A US 5796670A
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- polysilicon
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
Definitions
- the present invention relates generally to semiconductor memory devices, and more particularly, to a nonvolatile dynamic random access memory device.
- Nonvolatile memory devices There are essentially two types of data memory devices used in computers today, “Nonvolatile” and “Volatile”.
- Common nonvolatile memory devices include well known Read Only Memory (ROM) devices that include EPROM (erasable programmable ROM) devices, EEPROM (electrically erasable programmable ROM) devices, Flash EEPROM devices, and magnetic tape data storage devices, such as well known hard disk drives.
- ROM Read Only Memory
- EPROM erasable programmable ROM
- EEPROM electrically erasable programmable ROM
- Flash EEPROM electrically erasable programmable ROM
- magnetic tape data storage devices such as well known hard disk drives.
- Volatile memory devices include Dynamic Random Access Memory (DRAM) chips and Static Random Access Memory (SRAM) devices.
- DRAM Dynamic Random Access Memory
- SRAM Static Random Access Memory
- RAM devices in the prior art have been used for temporary data storage, such as during data manipulation, since writing data into, and reading data out of, the device is performed quickly and easily.
- a disadvantage of these devices is that they require the constant application of power, such as in the form of a data refresh signal, to refresh and maintain data stored in the memory cells of the chip. Once power supplied to the device is interrupted, the data stored in the memory cells of the chip is lost.
- Flash EEPROMs are emerging as a preferable means for data storage. These devices are somewhat rugged, they do not have the moving components of hard disk drives, and they have relatively low power consumption.
- One such Flash EEPROM device is disclosed in U.S. Pat. No. 5,373,465, to Chen et al.
- the disclosed flash EEPROM requires a 5 volt external source to effect Fowler-Nordheim tunneling during both program and erase modes of the device. Properties of dielectric layers between a floating gate and a control gate, and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate.
- An on-device voltage multiplier is used to convert the external 5 volt DC signal to a high voltage of approximately 20 to 30 volts.
- U.S. Pat. No. 5,418,752 to Harari et al. discloses a system of flash EEPROM memory chips that serve as a unitary nonvolatile memory means, similar to a memory provided by a hard disk drive.
- the disclosed system enables any combinations of flash sections to be erased together and to de-select selected sectors during the erase operation.
- the system also provides the ability to automatically remap and replace defective cells with substitute cells, upon the detection of defective cells.
- U.S. Pat. No. 4,855,955, to Cioaca is directed to a three transistor high endurance EEPROM cell that comprises two floating gate MOS transistors connected in series with a select transistor.
- a plurality of such memory cells may be connected together as a byte, and may be placed in an array, with the gates of the select transistors connected together.
- a word line signal is provided to drive the gates of the select transistors and to drive the gates of two sense line byte select transistors. The word line signal enables the sense line signals to appear on only the gates of the memory cell floating gate transistor of the selected byte.
- Nonvolatile semiconductor memory device is disclosed in U.S. Pat. No. 5,202,850, to Jenq, which is directed to a single transistor nonvolatile electrically alterable semiconductor memory device with a re-crystallized floating gate.
- the device comprises a semiconductor substrate having a first conductivity type. Source and drain regions are defined in the substrate, with a channel region therebetween.
- An electrically conductive, re-crystallized floating gate is disposed over a first insulating layer that is disposed over the source and drain regions.
- the floating gate extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith.
- a second insulating layer has a top wall portion immediately adjacent to the floating gate and has a thickness that permits Fowler-Nordheim tunneling of charges therethrough.
- An electrically conductive control gate has a first section that is over the first insulating layer and immediately adjacent to the side wall portion of the second insulating layer, and a second portion. The first portion further extends over a portion of the channel region and over the source region. The second section is disposed over the top wall portion of the second insulating layer to minimize capacitive coupling with the floating gate.
- a method for forming a dual thickness dielectric floating gate memory cell is disclosed in U.S. Pat. No. 5,324,676, to Guterman.
- the disclosed method is used to fabricate an integrated circuit device having first and second conducting layers, with the first layer having a shape that enhances field emission tunneling off of the surface thereof, and a dual thickness dielectric layer that separates the conducting layers.
- first and second conducting layers with the first layer having a shape that enhances field emission tunneling off of the surface thereof, and a dual thickness dielectric layer that separates the conducting layers.
- EEPROM and Flash EEPROM devices are inherent disadvantages of EEPROM and Flash EEPROM devices. These operations are performed by applying a substantial voltage, usually greater than 20 volts, to the memory cells thereof, causing stress to the device. Thus, there is a finite number of read and write operations that the device can endure, before the device is rendered unreliable. Further, since a substantial voltage must be applied to the device to perform the desired operation, EEPROMs and Flash EEPROMs are noticeably slower than RAM devices when performing read or write data operations.
- each memory cell of the invention comprises a select transistor having its gate coupled a word line input of the array.
- the transistor has either its source or drain, depending upon voltage level, coupled to a sense amplifier via a bitline connection(VBIT) of its memory cell array.
- VBIT bitline connection
- the data access capacitor is coupled in series to a novel, nonvolatile data storage capacitor that is coupled to a reference voltage source (V REF )
- V REF reference voltage source
- the nonvolatile data storage capacitor comprises a floating layer of polysilicon that is interposed between a plate layer of polysilicon comprising the reference voltage source (V REF ), and a node polysilicon layer comprising the data access capacitor.
- V REF reference voltage source
- a charge of electrons, indicative of data, that is stored on the access capacitor is transferred to the data storage capacitor, before power to the device is removed. Therefore, data stored on the data storage capacitor in each of the memory cells of the present invention is not lost when power is removed from the device.
- the data is then accessed as if the it is stored in a memory cell of a conventional DRAM device, with access speeds equivalent thereto. Data is thus accessed and manipulated substantially faster than known nonvolatile memory chips, such as EEPROM's and Flash EEPROM's.
- the structure of the invented memory cells enables a number of previously volatile random access memory devices to be portable, without losing the data stored therein.
- the cells of the present invention provide a DRAM device with known RAM device data access speed features, such as static column and fast page modes, for example.
- each memory cell includes a thin tunneling oxide region that is interposed between a node polysilicon layer and the floating layer of polysilicon.
- the tunneling oxide region preferably has a thickness that permits transfer of electrons from the node polysilicon to the floating polysilicon using known methods, such as Fowler-Nordheim tunneling or hot electron injection.
- an insulating oxide layer is interposed between the floating polysilicon and the reference voltage source (V REF ), a plate polysilicon layer, for reducing leakage current from the storage capacitor to the reference voltage source V REF . This enhances the storage capacitor's ability to retain data thereon.
- volatile data data that is stored on the data access capacitor
- nonvolatile data data that is stored on the storage capacitor
- the program procedure comprises first activating a word line of the memory cell containing the data.
- the word line is activated for activating the select transistor of each memory cell of a memory cell array word line.
- a sense amplifier coupled to the select transistor via the bitline (V BIT ) will either electronically ground V BIT , or force V BIT to a voltage level equivalent to the supply voltage level (V cc ), depending upon the value, sensed by the amplifier.
- a high voltage less than 20 volts DC, and preferably ranging from approximately 10 to 15 volts DC for example, is applied to V REF to induce Fowler-Nordheim electron tunneling of electrons from the node polysilicon layer of the transistor (access capacitor), to the floating layer of polysilicon (storage capacitor).
- V REF voltage
- the lower than prior art high voltage level of approximately 10 to 15 volts enables electron tunneling without causing stress to a DRAM device embodying the present invention.
- the layer of insulating oxide between the floating polysilicon and plate polysilicon aids with maintaining the charge on the floating polysilicon.
- V BIT V cc
- Nonvolatile data data that is stored on the storage capacitor
- volatile data data that is stored on the access capacitor
- a data restore procedure power is first reapplied to the device.
- word line of the memory cell array containing the data is activated for activating the select transistor of each memory cell thereof
- the gate region and node polysilicon of the transistor are then electronically grounded.
- the word line is deactivated by the sense amplifier and a high negative voltage, again ranging from approximately -10 to -15 VDC to prevent stress to the memory cells and device, is applied to the plate polysilicon V REF .
- the charge of electrons stored on the floating polysilicon layer tunnel through the tunneling regions of the tunneling oxide to the node polysilicon, for storing the data thereon and complete the data restore procedure.
- the charge of electrons stored on the node poly or data access capacitor, indicative of data, is now available using access method equivalent to known DRAM devices.
- FIG. 1 is a schematic view showing a memory cell of a prior art DRAM device
- FIG. 2 is a schematic view showing a memory cell of a preferred embodiment of a nonvolatile random access memory device of the present invention
- FIG. 3 is a schematic view showing the equivalent capacitance of the memory cell of the nonvolatile random access memory device of the present invention.
- FIG. 4 is a cross sectional view showing the memory cell of the preferred embodiment of the present invention.
- a memory cell 10 of a prior art random access memory device such as a dynamic random access memory (DRAM) device.
- DRAM dynamic random access memory
- the memory cell 10 comprises a single transistor 12, known as the select transistor, to provide a device that is relatively inexpensive, has high data storage capabilities, and low power consumption.
- the transistor 12 has its gate 14 coupled a word line connection 16 of an array of the device.
- Either a source 18 or drain 20 of the transistor 12 is coupled to a sense amplifier via a bitline connection V BIT , depending upon the voltage level of the connection V BIT .
- the remaining one of the source 18 and drain 20 is connected to a data access capacitor 22, which is coupled to a reference voltage source V REF .
- data is read into and written out of the access capacitor 22, by first activating the word line connection 16 to activate the transistor 12.
- the V BIT connection is then activated for reading data into and writing data out of the access capacitor 22.
- Data is stored in the data access capacitor 22 as long as power is supplied to the device and as long as the data is refreshed, as is well known in the art.
- FIG. 2 and FIG. 3 of the drawings there is schematically shown, generally at 30, a preferred embodiment of a nonvolatile memory cell for a random access memory device, such as a DRAM device.
- the memory cell 30 of the present invention is preferably integrated into a DRAM device of conventional configuration and operation, so as to facilitate direct substitution of the improved nonvolatile DRAM device of the present invention, for prior art DRAM devices.
- nonvolatile random access memory devices utilizing the memory cells of the present invention may be used in a number of different applications where data nonvolatility combined with fast data access speeds are desirous features.
- the invented nonvolatile random access memory cell 30 comprises the select transistor 12 having its gate 14 coupled the word line connection 16 of the device. Either the source 18 or drain 20 of the transistor 12 is coupled to a sense amplifier of the memory cell array containing the cell 30, via the bitline connection V BIT , depending upon the voltage level of V BIT . The remaining one of the source 18 and drain 20 is connected to the data access capacitor 22.
- the invented memory cell 30 comprises the data access capacitor 22 coupled in series to a nonvolatile data storage capacitor 32 that is coupled to the reference voltage source V REF .
- the nonvolatile data storage capacitor 32 comprises a floating portion of polysilicon (to be thoroughly discussed hereinafter) that is positioned adjacent to the access capacitor 22. Data that is stored in the access capacitor 22 is transferred to the storage capacitor 32, to convert the data from a volatile state to a nonvolatile state.
- FIG. 4 of the drawings there is shown a cross sectional view of the memory cell 30 of the preferred embodiment of the present invention.
- the memory cell 30 is formed on a silicon substrate 34 as is well known in the art.
- Field oxide regions 36 are grown on the substrate 34 to define the transistor 12 therebetween.
- the gate region 14 is formed on the substrate 34 as is known.
- a pair of diffusion regions that provide the combined source/drain regions 18/20 are formed by implanting impurity ions into the substrate 34 using known techniques.
- An oxide 38 is then disposed over the substrate 34.
- a node polysilicon layer 40 is then formed over the oxide 38.
- the node polysilicon 40 has a curvilinear configuration with a portion 42 thereof extending through the oxide 38 and contacting a source/drain region 18/20.
- the node polysilicon 40 functions as the data access capacitor 22, which temporarily retains a charge of electrons indicative of data thereon for facile access of the data as is known with prior art DRAM devices.
- a portion 44 of a conductive material is disposed adjacent to the gate 14 and contacting the other source/drain region 18/20 for coupling the transistor 12 to the bitline connection V BIT of the device.
- the bitline connection V BIT is activated for accessing data on the node polysilicon 40.
- a tunneling oxide 46 is disposed over the node polysilicon 40.
- the tunneling oxide 46 is etched, using known methods, above ends 48 of the node polysilicon 40, so that the oxide 46 is ultra thin to provide tunneling regions 50 therethrough.
- the tunneling regions 50 of the oxide 46 range in thickness from approximately 70 ⁇ to 100 ⁇ (Angstroms).
- the floating layer of polysilicon 32 is formed over the tunneling oxide 46 and extends adjacently to the node polysilicon 40.
- the floating polysilicon 32 has end portions 52 that extend partially about the ends 48 of the node polysilicon 40.
- the end portions 52 of the floating polysilicon 32 and ends 48 of the node polysilicon 40 are configured to facilitate electron transfer through the tunneling regions 50 therebetween.
- a charge of electrons are transferred between the node polysilicon 40 and floating polysilicon 32, using such methods as Fowler-Nordheim tunneling or hot electron injection, for example.
- the floating polysilicon layer 32 provides a nonvolatile data storage capacitor for retaining a charge of electrons, indicative of data thereon, after power to the device is removed.
- an insulating oxide 54 is disposed over the floating polysilicon 32.
- the insulating oxide 54 is provided to inhibit leakage of a charge of electrons stored on the floating polysilicon 32 to a plate polysilicon layer 56, for retaining the data on the floating polysilicon 32.
- the insulating oxide 54 preferably comprises an oxide-nitride-oxide compound and is substantially thick, to aid with retaining the charge of electrons on the floating polysilicon 32.
- the plate layer of polysilicon 56 provides the reference voltage source V REF .
- the plate polysilicon 56 is formed over the insulating oxide 54 and extends adjacently to the floating polysilicon 32 and terminates above the transistor's gate 14.
- a supply voltage of approximately 5 volts DC is applied to a device, such as a DRAM device, embodying the invented memory cells 30 for activating the device.
- a device such as a DRAM device, embodying the invented memory cells 30 for activating the device.
- the word line 16 of a memory cell 30 is activated, for activating its transistor 12.
- Data can then be stored onto and read from the node polysilicon 40 (or data access capacitor 22), as is well known in the art. Data that is stored on the node polysilicon 40 is in the volatile state, since when the device is deactivated, any charge on the node polysilicon 40 dissipates and the data is lost.
- a programming procedure is used to transfer the data from the node polysilicon 40 to the floating polysilicon 32, to convert the data to the nonvolatile state.
- the programming procedure comprises first activating the word line 16 of a memory cell 30, for activating its transistor 12.
- the bitline connection V BIT is then sensed for determining an initial voltage level thereon.
- the initial voltage level on V BIT indicates if data is stored on the node polysilicon 40.
- Known methods such as Fowler-Nordheim electron tunneling or hot electron injection, may be used to facilitate the electrons tunneling from the node polysilicon 40 to the floating polysilicon 32.
- the voltage level used in the present invention is sufficient to cause electron tunneling between the node polysilicon 40 and the floating polysilicon 32, without causing stress to the device embodying the invented memory cells 30.
- the data is considered to be in the nonvolatile state. After the data is in the nonvolatile state, power can be removed from the device without loss of the data.
- the initial voltage level on the bitline connection V BIT is substantially zero volts, then electron tunneling occurs from the node polysilicon 40 to the floating polysilicon 32 for storing data thereon and convert the data from the volatile state to the nonvolatile state.
- the initial voltage level on the bitline connection V BIT is substantially equivalent to the supply voltage level, then electron tunneling does not from the node polysilicon 40 to the floating polysilicon 32 and a charge is not stored on the floating polysilicon 32, and the data is converted from the volatile state to the nonvolatile state.
- the high voltage potential is removed from the plate polysilicon 56.
- the word line 16 of the memory cell 30 is deactivated for deactivating the transistor 12 thereof.
- the supply voltage is then removed from the device, to deactivate the device.
- the data on the node polysilicon 40 is stored on the floating polysilicon 32, with the data being retained after deactivation of the device for providing nonvolatile data storage.
- the device is now portable, so that a DRAM device embodying the invented memory cells 30 may be removed from a circuit board, transported to a second circuit board, for example, coupled to the second circuit board and reactivated to read the data therefrom.
- the data should first be converted to the volatile state, or stored on the node polysilicon 40.
- the data is converted, or restored, to the volatile state by first reapplying the supply voltage to the device for activation thereof.
- the word line 16 of a memory cell 30 is then activated for electronically grounding the node polysilicon 40 and the gate 14 of the transistor 12.
- the word line 16 is then deactivated.
- a high negative voltage potential preferably ranging from approximately -10 to -15 volts DC, is then applied to the plate polysilicon 56.
- the negative voltage potential induces electrons, indicative of data, stored on the floating polysilicon 32 to tunnel to the node polysilicon 40 to store the data thereon, for restoring the data to the volatile state.
- the high voltage potential is then removed from the plate polysilicon 56 to complete the data restore procedure.
- nonvolatile memory cell for a random access memory device.
- the invented memory cells are similar in configuration to the memory cells of known DRAM devices, so that DRAM devices embodying the invented memory cells may replace existing DRAM devices.
- the floating polysilicon provides nonvolatile storage of data previously stored on the node polysilicon.
- the voltage level used in the programming and restore procedures of the present invention is sufficient to cause electron tunneling between the node polysilicon and the floating polysilicon, without causing stress to devices embodying the invented memory cells.
- data is accessed and manipulated substantially faster than known nonvolatile memory devices. Therefore, nonvolatile random access memory devices utilizing the memory cells of the present invention, may be used in a number of different applications where data nonvolatility combined with fast data access speeds are desirous features.
Abstract
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US08/745,101 US5796670A (en) | 1996-11-07 | 1996-11-07 | Nonvolatile dynamic random access memory device |
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US08/745,101 US5796670A (en) | 1996-11-07 | 1996-11-07 | Nonvolatile dynamic random access memory device |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US6141248A (en) * | 1999-07-29 | 2000-10-31 | Micron Technology, Inc. | DRAM and SRAM memory cells with repressed memory |
US6249460B1 (en) * | 2000-02-28 | 2001-06-19 | Micron Technology, Inc. | Dynamic flash memory cells with ultrathin tunnel oxides |
US6266289B1 (en) | 1999-03-09 | 2001-07-24 | Amphora | Method of toroid write and read, memory cell and memory device for realizing the same |
US6384448B1 (en) | 2000-02-28 | 2002-05-07 | Micron Technology, Inc. | P-channel dynamic flash memory cells with ultrathin tunnel oxides |
US20040213034A1 (en) * | 2003-04-23 | 2004-10-28 | Chieng-Chung Chen | Memory pumping circuit |
US6864139B2 (en) | 2000-02-29 | 2005-03-08 | Micron Technology, Inc. | Static NVRAM with ultra thin tunnel oxides |
US20080131088A1 (en) * | 2006-11-30 | 2008-06-05 | Mitac Technology Corp. | Image capture method and audio-video recording method of multi-media electronic device |
US20100277966A1 (en) * | 2007-07-03 | 2010-11-04 | Gregor Schatzberger | Memory Array and Storage Method |
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US20040213034A1 (en) * | 2003-04-23 | 2004-10-28 | Chieng-Chung Chen | Memory pumping circuit |
US7336521B2 (en) * | 2003-04-23 | 2008-02-26 | Winbond Electronics Corp. | Memory pumping circuit |
US20080131088A1 (en) * | 2006-11-30 | 2008-06-05 | Mitac Technology Corp. | Image capture method and audio-video recording method of multi-media electronic device |
US20100277966A1 (en) * | 2007-07-03 | 2010-11-04 | Gregor Schatzberger | Memory Array and Storage Method |
US8537586B2 (en) | 2007-07-03 | 2013-09-17 | Ams Ag | Memory array and storage method |
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