US5885886A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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US5885886A
US5885886A US08/932,830 US93283097A US5885886A US 5885886 A US5885886 A US 5885886A US 93283097 A US93283097 A US 93283097A US 5885886 A US5885886 A US 5885886A
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Sang Don Lee
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SK Hynix Inc
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LG Semicon Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability.
  • FIGS. 1a to 1d are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
  • active regions and field regions are defined on a P-type semiconductor substrate 1.
  • a field oxide layer 2 is formed on the field regions.
  • a first oxide layer, a polysilicon layer and a second oxide layer are successively formed on the entire surface.
  • the first oxide layer, the polysilicon layer, and the second oxide layer are patterned to form a gate oxide layer 3, a gate electrode 4, and a gate cap insulating layer 5.
  • P-type impurity ions are implanted at a tilt angle of 7°-20° into the semiconductor substrate 1 at both sides of the gate electrode 4, thus forming first halo regions 6.
  • P-type impurity ions are implanted at a tilt angle of 30°-60° into the substrate 1 at both sides of the gate electrode 4, so as to form second halo regions 7.
  • the second halo regions 7 extend further underneath the gate electrode 4 than the first halo regions 6, and have a more shallow depth than the first halo regions 6.
  • lightly-doped N-type impurity ions are implanted into the semiconductor substrate 1 at both sides of the gate electrode 4, thus forming a lightly doped drain (LDD) regions 8.
  • LDD lightly doped drain
  • an oxide layer is formed on the entire surface and then subjected to etch-back, thus forming insulating sidewalls 9 on the both sides of the gate electrode 4.
  • CVD chemical vapor deposition
  • highly-doped N-type impurity ions are implanted into the semiconductor substrate 1.
  • the depth of the first halo regions 6 is similar to that of the source and drain regions 10
  • the depth of the second halo regions 7 is similar to that of the LDD regions 8, thereby improving short channel effects.
  • Such a conventional method for manufacturing a semiconductor device has problems.
  • Ion implantation processes are performed twice to form the different halo regions.
  • the halo regions 6 improve the breakdown voltage characteristics and the halo regions 7 improve short channel effects and adjust the threshold voltage. Consequently, the first and second halo regions overlap each other.
  • the present invention is directed to a manufacturing method of a semiconductor device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
  • An object of the invention is to provide a method for manufacturing a semiconductor device exhibiting improved short channel effects, an increased breakdown voltage and improved current driving ability.
  • a method for manufacturing a semiconductor device includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode.
  • the method also includes forming source and drain regions of the second conductivity-type in the substrate.
  • the amorphous regions of the present invention are formed by ion implantation of the inactive ions while the first and second impurity regions and the source and drain regions are formed by ion implantation of active ions.
  • Inactive ions are ions which, after implantation into the first conductivity-type substrate, assume an atomic or molecular state in which they act neither as acceptors nor donors. Conversely, active ions act as acceptors or donors after implantation.
  • FIGS. 1a to 1d are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
  • FIGS. 2a to 2e are cross-sectional views showing a method for manufacturing a semiconductor device according to a preferred embodiment of the invention.
  • FIGS. 2a to 2e there is provided a manufacturing method of a semiconductor device.
  • field regions and active regions are defined on a semiconductor substrate 21, e.g., P-type monocrystalline silicon. Then a field oxide layer 22 is formed on the field regions.
  • a first oxide layer, a conductive (e.g., polysilicon) layer, and an insulating layer are successively formed.
  • the insulating layer is an oxide layer, a nitride layer, a doped oxide layer, or double layers of an oxide and a nitride.
  • the first oxide layer, the polysilicon layer, and the insulating layer are patterned to form a gate insulating (e.g., oxide) layer 23, a gate electrode 24, and a gate cap insulating layer 25.
  • one or more of the following inactive ions such as germanium ions, silicon ions, nitrogen ions, fluorine ions, and argon ions are implanted at a tilt angle into the substrate 21.
  • the ions are inactive in the sense that they assume an atomic or molecular states that do not act as either donors or as acceptors in the lattice.
  • the ions extend a predetermined distance under the gate electrode 24. Portions of the monocrystalline silicon substrate 21 become amorphous silicon regions 26.
  • the tilt angle is 0°-60°
  • the ion implantation energy is 5-500 KeV
  • the dosage of the impurity ions is 1 ⁇ 10 12 ions/cm 2 -1 ⁇ 10 16 ions/cm 2 .
  • P-type active ions are implanted at a tilt angle of 0°-60° into the substrate 21, thus forming halo regions 27.
  • the ions are active in the sense that, after they are implanted, the act as either acceptors or donors.
  • the amorphous silicon regions 26 act as a gathering center where ions (that alter the substrate 21 to form the halo regions 27) accumulate. Also, the amorphous silicon regions 26 serve to prevent ions from diffusing as rapidly during annealing as would be the case if the region 26 were monocrystalline silicon.
  • the doping concentration of the halo regions 27 is increased, e.g., by a factor or about 1.2 or 1.3, due to the previous formation of the amorphous silicon regions 26.
  • lightly doped N-type ions are implanted into the exposed semiconductor substrate 21 at both sides of the gate electrode 24, thus forming lightly doped drain (LDD) regions 28.
  • LDD lightly doped drain
  • an insulating layer is formed, e.g., by a chemical vapor deposition (CVD) method and then is subjected to an etch-back process, thereby forming insulating sidewalls against both sides of the gate electrode 24.
  • CVD chemical vapor deposition
  • etch-back process thereby forming insulating sidewalls against both sides of the gate electrode 24.
  • highly doped N-type ions are implanted into the P-type semiconductor substrate 21, thus forming the source and drain regions 30.
  • the implanted ions are activated by annealing, which causes the halo regions to expand.
  • This expansion is indicated in FIG. 2e by the dashed line 27 being depicted outside of the amorphous region indicated by the line 26. This is in contrast to FIGS. 2c-2d, where the dashed line 27 is depicted inside the line 26.
  • the exemplary embodiments of the present invention can be applied, e.g., to MOS devices and to diodes of different conductivity-types.
  • one or more ions such as argon ions, germanium ions, silicon ions, fluorine ions, and nitrogen ions (which will be subsequently be inactive, neither acting as acceptors nor as donors) are implanted into a P-type conductivity monocrystalline silicon substrate, thus forming amorphous silicon regions.
  • An ion implantation energy of 5-500 KeV and a dosage of 1 ⁇ 10 12 ions/cm 2 -1 ⁇ 10 16 ions/cm 2 is used to form the amorphous regions.
  • the P-type ions are implanted at a tilt angle of 0°-60° to form the halo regions. These halo regions are formed near the amorphous regions.
  • the amorphous regions act as ion-gathering centers where ions gather for the formation of the halo regions.
  • N-type impurity regions which have a junction with the P-type impurity regions in the halo regions of the substrate.
  • an N+/P junction is achieved, thereby enabling the characteristics of reverse breakdown voltage, leakage current and forward current to be adjusted.
  • the substrate can be monocrystalline N-type silicon
  • the first ion-implantations can use inactive ions
  • the second ion-implantations can use N-type impurity ions to form the halo regions
  • the third ion-implantation can use lightly doped P-type impurity ions to form the LDD regions
  • the fourth ion-implantation can use highly doped P-type impurity ions to form the source and drain regions.
  • the manufacturing method of a semiconductor device of the invention has the following advantages.
  • amorphous silicon regions act as gathering centers of impurity ions used in the subsequent formation of halo regions.
  • impurity ions of the halo regions cannot be diffused as rapidly as in a monocrystalline silicon substrate, thereby maintaining a high concentration of impurity ions at the halo regions. Therefore, it is possible to produce a semiconductor device exhibiting improved breakdown voltage characteristics.

Abstract

A method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability is disclosed. The method includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions of the first conductivity-type into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode. The method also includes forming source and drain regions of the second conductivity-type in the substrate. The amorphous regions are formed by ion implantation of the inactive ions while the first and second impurity regions and the source and drain regions are formed by ion implantation of active ions. Inactive ions are ions which, after implantation into the amorphous regions, assume an atomic or molecular state in which they act neither as acceptors nor donors. Conversely, active ions act as acceptors or donors after implantation.

Description

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability.
BACKGROUND OF THE INVENTION
A conventional method for manufacturing a semiconductor device will be discussed with reference to the attached drawings.
FIGS. 1a to 1d are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
As shown in FIG. 1a, active regions and field regions are defined on a P-type semiconductor substrate 1. A field oxide layer 2 is formed on the field regions. Subsequently, a first oxide layer, a polysilicon layer and a second oxide layer are successively formed on the entire surface. Utilizing a mask, the first oxide layer, the polysilicon layer, and the second oxide layer are patterned to form a gate oxide layer 3, a gate electrode 4, and a gate cap insulating layer 5. P-type impurity ions are implanted at a tilt angle of 7°-20° into the semiconductor substrate 1 at both sides of the gate electrode 4, thus forming first halo regions 6.
Referring to FIG. 1b, P-type impurity ions are implanted at a tilt angle of 30°-60° into the substrate 1 at both sides of the gate electrode 4, so as to form second halo regions 7. In this case, the second halo regions 7 extend further underneath the gate electrode 4 than the first halo regions 6, and have a more shallow depth than the first halo regions 6.
Referring to FIG. 1c, lightly-doped N-type impurity ions are implanted into the semiconductor substrate 1 at both sides of the gate electrode 4, thus forming a lightly doped drain (LDD) regions 8.
Referring to FIG. 1d, utilizing a chemical vapor deposition (CVD) method, an oxide layer is formed on the entire surface and then subjected to etch-back, thus forming insulating sidewalls 9 on the both sides of the gate electrode 4. With the gate electrode 4 and the gate insulating sidewalls 9 serving as masks, highly-doped N-type impurity ions are implanted into the semiconductor substrate 1. This produces source and drain regions 10 in the P-type conductivity-type substrate 1 on both sides of the insulating sidewalls 9. In this case, the depth of the first halo regions 6 is similar to that of the source and drain regions 10, and the depth of the second halo regions 7 is similar to that of the LDD regions 8, thereby improving short channel effects. Thus, the conventional manufacturing of a semiconductor device is completed.
Such a conventional method for manufacturing a semiconductor device has problems.
Ion implantation processes are performed twice to form the different halo regions. The halo regions 6 improve the breakdown voltage characteristics and the halo regions 7 improve short channel effects and adjust the threshold voltage. Consequently, the first and second halo regions overlap each other.
As channel lengths get shortened in highly integrated devices, increasingly high concentrations in the first halo region 6 are required to adjust a breakdown voltage. Consequently, the portions where the first and second halo regions overlap have an even higher doping concentration. As a result, it is hard to adjust threshold voltage using the portions having an overlap-increased, high doping concentration, which causes difficulties in carrying out a successful ion implantation process.
SUMMARY OF THE INVENTION
Therefore, the present invention is directed to a manufacturing method of a semiconductor device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a method for manufacturing a semiconductor device exhibiting improved short channel effects, an increased breakdown voltage and improved current driving ability.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for manufacturing a semiconductor device is provided and includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode. The method also includes forming source and drain regions of the second conductivity-type in the substrate.
The amorphous regions of the present invention are formed by ion implantation of the inactive ions while the first and second impurity regions and the source and drain regions are formed by ion implantation of active ions. Inactive ions are ions which, after implantation into the first conductivity-type substrate, assume an atomic or molecular state in which they act neither as acceptors nor donors. Conversely, active ions act as acceptors or donors after implantation.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
These and various other objects, features, and advantages of the present invention will be readily understood with reference to the following detailed description read in conjunction with the accompanying drawings, which depict exemplary embodiments and do not limit the claims, and in which:
FIGS. 1a to 1d are cross-sectional views showing a conventional method for manufacturing a semiconductor device; and
FIGS. 2a to 2e are cross-sectional views showing a method for manufacturing a semiconductor device according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
Referring to FIGS. 2a to 2e, there is provided a manufacturing method of a semiconductor device.
Referring to FIG. 2a, field regions and active regions are defined on a semiconductor substrate 21, e.g., P-type monocrystalline silicon. Then a field oxide layer 22 is formed on the field regions.
Subsequently, a first oxide layer, a conductive (e.g., polysilicon) layer, and an insulating layer are successively formed. The insulating layer is an oxide layer, a nitride layer, a doped oxide layer, or double layers of an oxide and a nitride. Utilizing a mask, the first oxide layer, the polysilicon layer, and the insulating layer are patterned to form a gate insulating (e.g., oxide) layer 23, a gate electrode 24, and a gate cap insulating layer 25.
Referring to FIG. 2b, using the gate electrode 24 as a mask, one or more of the following inactive ions, such as germanium ions, silicon ions, nitrogen ions, fluorine ions, and argon ions are implanted at a tilt angle into the substrate 21.
The ions are inactive in the sense that they assume an atomic or molecular states that do not act as either donors or as acceptors in the lattice.
In the exemplary embodiments, the ions extend a predetermined distance under the gate electrode 24. Portions of the monocrystalline silicon substrate 21 become amorphous silicon regions 26. In this exemplary embodiment, the tilt angle is 0°-60°, the ion implantation energy is 5-500 KeV and the dosage of the impurity ions is 1×1012 ions/cm2 -1×1016 ions/cm2.
Referring to FIG. 2c, with the gate electrode 24 serving as a mask, P-type active ions are implanted at a tilt angle of 0°-60° into the substrate 21, thus forming halo regions 27. The ions are active in the sense that, after they are implanted, the act as either acceptors or donors.
The amorphous silicon regions 26 act as a gathering center where ions (that alter the substrate 21 to form the halo regions 27) accumulate. Also, the amorphous silicon regions 26 serve to prevent ions from diffusing as rapidly during annealing as would be the case if the region 26 were monocrystalline silicon. The doping concentration of the halo regions 27 is increased, e.g., by a factor or about 1.2 or 1.3, due to the previous formation of the amorphous silicon regions 26.
Referring to FIG. 2d, with the gate electrode 24 serving as a mask, lightly doped N-type ions are implanted into the exposed semiconductor substrate 21 at both sides of the gate electrode 24, thus forming lightly doped drain (LDD) regions 28.
Referring to FIG. 2e, an insulating layer is formed, e.g., by a chemical vapor deposition (CVD) method and then is subjected to an etch-back process, thereby forming insulating sidewalls against both sides of the gate electrode 24. Next, with the gate electrode 24 and the insulating sidewalls 29 serving as masks, highly doped N-type ions are implanted into the P-type semiconductor substrate 21, thus forming the source and drain regions 30.
Thereafter, the implanted ions are activated by annealing, which causes the halo regions to expand. This expansion is indicated in FIG. 2e by the dashed line 27 being depicted outside of the amorphous region indicated by the line 26. This is in contrast to FIGS. 2c-2d, where the dashed line 27 is depicted inside the line 26.
Then, an interlayer insulating layer is formed, a contact pattern is formed, and a wiring process is performed. This completes the semiconductor device of the invention.
The exemplary embodiments of the present invention can be applied, e.g., to MOS devices and to diodes of different conductivity-types. To explain how to apply the invention to them, one or more ions such as argon ions, germanium ions, silicon ions, fluorine ions, and nitrogen ions (which will be subsequently be inactive, neither acting as acceptors nor as donors) are implanted into a P-type conductivity monocrystalline silicon substrate, thus forming amorphous silicon regions. An ion implantation energy of 5-500 KeV and a dosage of 1×1012 ions/cm2 -1×1016 ions/cm2 is used to form the amorphous regions. Then, the P-type ions are implanted at a tilt angle of 0°-60° to form the halo regions. These halo regions are formed near the amorphous regions. The amorphous regions act as ion-gathering centers where ions gather for the formation of the halo regions.
Subsequently, there are formed N-type impurity regions which have a junction with the P-type impurity regions in the halo regions of the substrate. As a result, an N+/P junction is achieved, thereby enabling the characteristics of reverse breakdown voltage, leakage current and forward current to be adjusted.
Alternatively, the substrate can be monocrystalline N-type silicon, the first ion-implantations can use inactive ions, the second ion-implantations can use N-type impurity ions to form the halo regions, the third ion-implantation can use lightly doped P-type impurity ions to form the LDD regions, and the fourth ion-implantation can use highly doped P-type impurity ions to form the source and drain regions.
The manufacturing method of a semiconductor device of the invention has the following advantages.
First, amorphous silicon regions act as gathering centers of impurity ions used in the subsequent formation of halo regions. As a result, impurity ions of the halo regions cannot be diffused as rapidly as in a monocrystalline silicon substrate, thereby maintaining a high concentration of impurity ions at the halo regions. Therefore, it is possible to produce a semiconductor device exhibiting improved breakdown voltage characteristics.
Second, since the impurity ions implanted into the semiconductor substrate are diffused only slightly into the channel regions, reverse short channel effects are improved and a threshold voltage is easily adjusted.
Third, since doping concentrations can be kept low in all regions except the halo regions, current driving ability is improved.
It will be apparent to those skilled in the art that various modifications and variations can be made in the manufacturing method of a semiconductor device of the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention cover the modifications and variations of this invention as would be obvious to one of ordinary skill in the art and that these modifications and variations be included within the scope of the appended claims and their equivalents.

Claims (30)

What is claimed is:
1. A method for manufacturing a semiconductor device, the method comprising the steps of:
providing a first conductivity-type substrate;
introducing inactive ions into said substrate, so as to form amorphous regions;
forming first impurity regions of said first-conductivity-type within said amorphous regions;
forming second impurity regions of a second conductivity-type in said amorphous regions of said substrate; and
annealing said substrate such that said first impurity regions are expanded in said substrate beyond said amorphous regions.
2. The method as claimed in claim 1, wherein said inactive ions are ions which, after implantation into said amorphous regions, act neither as acceptors nor as donors.
3. The method as claimed in claim 1, wherein said step of introducing includes using one or more of argon ions, germanium ions, silicon ions, fluorine ions, and nitrogen ions as said inactive ions.
4. The method as in claim 1, wherein said step of providing said substrate includes using monocrystalline silicon as material for said substrate and said step of introducing includes ion implanting said inactive ions to form amorphous silicon regions.
5. The method as claimed in claim 4, wherein said step of ion implanting said inactive ions includes using an ion implantation energy of 5-500 KeV and a dosage of 1×1012 ions/cm2 -1×1016 ions/cm2.
6. The method as claimed in claim 4, wherein said step of ion implanting includes using two or more kinds of inactive ions and aiming said inactive ions at different tilt angles.
7. The method as in claim 1, further comprising:
forming source and drain regions of said second conductivity-type in said substrate.
8. The method as in claim 7, wherein said step of forming source and drain regions includes ion implanting highly doped second conductivity-type active ions into said substrate.
9. The method as in claim 1, wherein said first conductivity-type is P-type and said second conductivity-type is N-type.
10. The method as in claim 1, wherein said step of forming said first impurity regions includes ion implanting said first-conductivity-type active ions near said amorphous regions.
11. The method as in claim 10, wherein said step of forming second impurity regions includes ion implanting second conductivity-type active ions into said amorphous regions.
12. The method as claimed in claim 11, wherein said inactive ions are implanted at a tilt angle of 0°-60°, and active ions to form said first impurity regions are implanted at a tilt angle of 0°-60°.
13. The method as in claim 11, wherein said first conductivity-type is P-type and said second conductivity-type is N-type.
14. The method as in claim 1, wherein said step of forming second impurity regions includes ion implanting second conductivity-type active ions into said amorphous regions.
15. A method for manufacturing a semiconductor device, the method comprising the steps of:
providing a substrate of a first conductivity-type;
forming a gate insulating layer on said substrate;
forming a gate electrode on said gate insulating layer;
forming a gate cap insulating layer on said gate electrode;
introducing inactive ions into said first conductivity-type semiconductor substrate at both sides of said gate electrode, so as to form amorphous regions;
forming first impurity regions of said first conductivity-type within said amorphous regions;
forming second impurity regions of a second conductivity-type in said substrate at said both sides of said gate electrode; and
annealing said substrate such that said first impurity regions are expanded in said substrate beyond said amorphous regions.
16. The method as claimed in claim 15, wherein inactive ions are ions which, after implantation into said first conductivity-type substrate, act neither as acceptors nor as donors.
17. The method as claimed in claim 15, wherein said step of introducing includes using one or more of argon ions, germanium ions, silicon ions, fluorine ions, and nitrogen ions as said inactive ions.
18. The method as claimed in claim 17, wherein said step of introducing includes ion implanting two or more kinds of inactive ions and aiming said inactive ions at the same angle.
19. The method as claimed in claim 17, wherein said step of introducing includes ion implanting two or more kinds of inactive ions and aiming said inactive ions at different tilt angles.
20. The method as claimed in claim 15, wherein said step of introducing includes ion implanting said inactive ions at a tilt angle of 0°-60°, and said step of forming said first impurity regions includes ion implanting active ions at a tilt angle of 0°-60°.
21. The method as in claim 20, wherein said step of forming second impurity regions includes ion implanting second conductivity-type active ions into said amorphous regions.
22. The method as claimed in claim 15, wherein said step of introducing includes ion implanting said inactive ions at an energy of 5-500 KeV and a dosage of 1×1012 ions/cm2 -1×1016 ions/cm2.
23. The method as in claim 15, wherein said step of providing a substrate includes using monocrystalline silicon as material for said substrate and said step of introducing includes ion implanting said inactive ions to form amorphous silicon regions.
24. The method as claimed in claim 23, wherein said step of ion implanting includes using two or more kinds of inactive ions and aiming said inactive ions at different tilt angles.
25. The method as in claim 15, further comprising:
forming source and drain regions of said second conductivity-type in said substrate.
26. The method as in claim 25, wherein said step of forming source and drain regions includes ion implanting highly doped second conductivity-type active ions into said substrate.
27. The method as in claim 15, wherein said first conductivity-type is P-type and said second conductivity-type is N-type.
28. The method as in claim 15, wherein said step of forming said first impurity regions includes ion implanting said first-conductivity-type active ions near said amorphous regions.
29. The method as in claim 28, wherein said step of forming second impurity regions includes ion implanting second conductivity-type active ions into said amorphous regions.
30. The method as in claim 29, wherein said first conductivity-type is P-type and said second conductivity-type is N-type.
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CN108695258B (en) * 2017-04-11 2020-11-03 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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KR100232206B1 (en) 1999-12-01

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