US5896404A - Programmable burst length DRAM - Google Patents
Programmable burst length DRAM Download PDFInfo
- Publication number
- US5896404A US5896404A US08/833,371 US83337197A US5896404A US 5896404 A US5896404 A US 5896404A US 83337197 A US83337197 A US 83337197A US 5896404 A US5896404 A US 5896404A
- Authority
- US
- United States
- Prior art keywords
- groups
- ecc
- dram
- mode
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1052—Bypassing or disabling error detection or correction
Definitions
- the Present invention is related to application Ser. No. 08/833,367 (Attorney Reference No. BU9-97-028) entitled “Reconfigurable I/O DRAM” to Bertin et al., assigned to the assignee of the present invention and filed concurrently herewith.
- the present invention generally relates to high performance Dynamic Random Access Memories (DRAMs) and, in particular, to high bandwidth DRAMs that may be used in Error Checking applications.
- DRAMs Dynamic Random Access Memories
- Multimedia applications demand several times more bandwidth for main memory or frame-buffer memory than computational intensive tasks; tasks such as spread sheet analysis programs or other Input/Output (I/O) intensive applications such as word processing or printing.
- tasks such as spread sheet analysis programs or other Input/Output (I/O) intensive applications such as word processing or printing.
- I/O Input/Output
- Extended Data Out (EDO) and Synchronous DRAMs (SDRAMs) were developed to improve bandwidth.
- EDO RAMs still do not match processor performance and, therefore, still limit system performance. Consequently, as faster microprocessors are developed for multimedia processing and high performance systems, faster memory architecture is being developed to bridge the memory/processor performance gap, e.g., wide I/O DRAMs.
- ECC Error Checking Code
- Parity is preferred for narrow data words, i.e., eight or sixteen bits because it requires only one extra bit per byte. However, parity only indicates that one or more bits in the byte/word is in error.
- SEC/DED codes are more reliable than parity, but for short data words (one or two bytes) require several check bits per word, and are, therefore, seldom used in such applications. SEC/DED is more efficient for a wider data word, i.e., sixty-four bits or greater, because for a wider word (several bytes), the check bit/byte ratio may be reduced to less than one.
- ECC Error Correction Code
- a memory system requires adding logic and extra memory chips for the six or more check bits.
- This extra memory may be in the form of extra memory chips or, special memory chips with nine or eighteen data I/O.
- the present invention is a high bandwidth Dynamic Random Access Memory (DRAM) with a programmable burst length of eight or nine.
- the DRAM array is divided into two or more banks, with sub-array cells arranged in addressable rows and columns.
- the DRAM is programmed for an eight location burst, the entire address space is available for data storage.
- the DRAM is programmed for a nine bit burst, part of each sub-array is reallocated as the ninth bit with the DRAM's address space reduced by one-eighth. Eight locations are in seven-eighths of the sub-array and the ninth location is from the remaining one eighth sub-array.
- all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight locations are data storage locations; In ECC mode, seven-eights of the page is data storage, the remaining one eighth, is assigned to check bit storage.
- FIG. 1 is a block diagram of a typical seventy-two Megabit (Mb) high bandwidth memory chip 100;
- FIG. 2 is a schematic of a preferred embodiment DRAM chip
- FIG. 3 is a block diagram of a page register as in the preferred embodiment chip of FIG. 2;
- FIG. 4 is a schematic of Burst Logic for controlling a burst transfer in a preferred embodiment DRAM.
- FIG. 1 is a block diagram of a typical 72 Mb high bandwidth memory chip 100 adapted for by nine ( ⁇ 9) operation.
- the memory array of this 72 Mb chip includes four 18 Mb banks 102, 104, 106 and 108. Each bank 102, 104, 106 and 108 is buffered by a page register 110, 112, 114, or 116, respectively. Data to/from the page registers 110, 112, 114 and 116 is transferred on a seventy-two bit data bus 118 from drivers 120 or to buffers 122. Buffers 122 pass data from the seventy-two bit data bus 118 to an 8:1 multiplexer (mux) 124.
- Mux multiplexer
- One byte (9 bits) is selected by mux 124 and passed off chip 100 on I/Os 126.
- Data In from I/Os 126 is received by demultiplexer (demux) 128.
- Demux 128 places any received data at the appropriate nine inputs to drivers 120 in response to a previously received address.
- Address input enable 130 places all I/O drivers in their high impedance state, so that an address may be received on the I/Os 126.
- FIG. 2 is a schematic of a preferred embodiment high bandwidth/performance DRAM according to the present invention.
- the chip 140 In its normal mode of operation (Normal mode) the chip 140 is programmed for a burst length of eight.
- ECC mode the chip 140 is programmed for a burst length of nine, where the chip's address space is reduced by one-eighth.
- the chip 140 is a 64 Mb array of four 16 Mb sub-arrays 142, 144, 146 and 148. It is understood that although the present invention is described in terms of a 64 Mb chip, the organization and density are for example only and, not intended as a limitation.
- the chip may be, for example, 256 Mb, one Gigabit (Gb) or larger with its array in correspondingly larger sub-arrays or in more sub-arrays. It is also understood that the selection of a burst length of eight or nine locations for chip 140 is by way of example only.
- the Normal mode burst length may be any multiple of two, for example, sixteen, with ECC mode increasing the burst one or more additional locations.
- elements of chip 140 in FIG. 2 that are identical or, substantially identical, to corresponding elements of the chip 100 in FIG. 1 with substantially identical operation are labeled identically.
- data is transferred to/from the page registers 154, 156, 158 or 160 as a 16 Kb block (one page) of data from a corresponding sub-array 142, 144, 146 or 148.
- One selected page register 154, 156, 158, 160 transfers sixty-four bits of data to/from Seventy-Two Bit Bus 118. Eight bits of Seventy-Two Bit Bus 118 are ignored ("don't care"). This sixty-four bits at the Seventy-Two Bit Bus 118 is transferred off chip as eight locations in a burst transfer.
- the page registers 154, 156, 158 and 160 are reconfigured to transfer seventy-two bits of data to/from seventy-two bit bus 118.
- data passes to/from seventy-two bit data bus 118 from drivers 120 or to buffers 122.
- this seventy-two bits is transferred in a burst of nine eight bit locations, eight locations from one sub-page and the ninth from another sub-page.
- Selecting Normal mode or ECC mode in the Mode Select Circuit 150 selects the number of burst locations in the Burst Logic 152 (described in detail herein below) and also affects operation of the page registers 154, 156, 158 and 160.
- the mode set by metal mask programmability wirebond Mode Select Logic 150 includes a "power on reset" state to insure that the DRAM enters Normal mode on memory power up and remains in Normal mode unless directed otherwise.
- FIG. 3 is a block diagram of a preferred embodiment page register 160, typical of page registers 154, 156, 158 and 160 in FIG. 2.
- Page register 160 includes a page decoder 162 for selecting one of eight 2 Kb registers or, sub-page arrays 164. Each sub-page array 164 is organized as thirty-two 64-bit segments.
- chip I/O organization is set in Mode Select block 170 by programming a fuse, setting a bit in a mode register or, any equivalent method. Alternatively, the mode may be set permanently by metal mask programming or by wire bond selection.
- the selection input to Mode Select Block 170 is connected at input 172.
- Page Decode 162 selects one of the eight sub-page arrays 164.
- Logic Decode 166 selects one of the thirty-two segments in the selected sub-page array 164. The selected segment is passed to/from multiplexer (mux) 168.
- Mux 168 is essentially two banks of gatable transceivers (not shown), a sixty-four bit bank and an eight bit bank. In normal mode the eight bit bank is disabled, i.e., gated off. So, the selected sixty-four bit segment is coupled to/from seventy-two bit bus 118 by mux 168. As described above, in normal mode eight bits of the data path between seventy-two bit data bus 118 and data I/O's 126 are ignored.
- sub-page array 164 is pre-designated as the check bit portion of the array. Any sub-page array 164 or any number of sub-page arrays 164 may be designated as check bit array(s).
- Mode Select block 170 isolates and enables sub-page decode 176 of logic decode 166 and enables 1:8 Decoder 178.
- Sub-page decode 176 selects one sixty-four bit segment and 1:8 Decode 178 selects one byte of the selected segment.
- the eight bit bank of mux 168 is enabled in ECC mode. So, the selected byte is passed to/from mux 168 in parallel with the selected sixty-four bit data segment. Mux 168 merges/selects the selected byte, i.e., the check bits, with the selected data segment. The resulting seventy-two bit segment (sixty-four data bits and eight check bits) are coupled to/from seventy-two bit bus 118. Data transfers between the seventy-two bit bus 118 and the eight Data I/Os 126 as controlled by the Burst Logic 152.
- FIG. 4 is a schematic of Burst Logic 152 in FIG. 2.
- the Burst Logic 152 includes a Clock buffer 180 and a Selectable Counter 182 that may be selected as a modulo eight counter or a modulo nine counter.
- Reset Command 184 resets the Selectable Counter 182 and forces the "Rest Condition".
- Mode Select line 186 from Mode Select logic 150 sets the Selectable Counter 182 as a modulo eight counter.
- Mode Select line 186 sets the Selectable Counter 182 as a modulo nine counter.
- the counter's four bit output 188 is passed both to 9:1 output mux 124 and 9:1 input mux 128, gating data to/from I/Os 126 as fast as the Selectable Counter 182 is toggled. Burst rate is set by clock 190 as gated by Strobe 192 and Terminate 194 in Clock Buffer 180.
- the preferred embodiment provides a flexible DRAM that may be used for applications where error checking is required or for in simple unchecked memory applications.
Abstract
Description
Claims (9)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/833,371 US5896404A (en) | 1997-04-04 | 1997-04-04 | Programmable burst length DRAM |
ARP980101456A AR012214A1 (en) | 1997-04-04 | 1998-03-31 | ACCESSORY FOR USE IN A CONTAINER TO DISPATCH LIQUIDS AND CONTAINER SET USING THE ACCESSORY |
JP08835198A JP3714580B2 (en) | 1997-04-04 | 1998-04-01 | Dynamic random access memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/833,371 US5896404A (en) | 1997-04-04 | 1997-04-04 | Programmable burst length DRAM |
Publications (1)
Publication Number | Publication Date |
---|---|
US5896404A true US5896404A (en) | 1999-04-20 |
Family
ID=25264247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/833,371 Expired - Lifetime US5896404A (en) | 1997-04-04 | 1997-04-04 | Programmable burst length DRAM |
Country Status (3)
Country | Link |
---|---|
US (1) | US5896404A (en) |
JP (1) | JP3714580B2 (en) |
AR (1) | AR012214A1 (en) |
Cited By (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6526537B2 (en) * | 1997-09-29 | 2003-02-25 | Nec Corporation | Storage for generating ECC and adding ECC to data |
US20030117882A1 (en) * | 2001-12-21 | 2003-06-26 | Kim Tae Yun | Semiconductor memory device |
US6662333B1 (en) * | 2000-02-04 | 2003-12-09 | Hewlett-Packard Development Company, L.P. | Shared error correction for memory design |
US20040010637A1 (en) * | 2002-07-10 | 2004-01-15 | Johnson Christopher S. | User defined burst length |
US20040083334A1 (en) * | 2002-10-28 | 2004-04-29 | Sandisk Corporation | Method and apparatus for managing the integrity of data in non-volatile memory system |
US20040165468A1 (en) * | 2002-02-11 | 2004-08-26 | Micron Technology, Inc. | User selectable banks for dram |
US6889307B1 (en) | 2001-11-16 | 2005-05-03 | Matrix Semiconductor, Inc. | Integrated circuit incorporating dual organization memory array |
US20050249010A1 (en) * | 2004-05-06 | 2005-11-10 | Klein Dean A | Memory controller method and system compensating for memory cell data losses |
US6965537B1 (en) | 2004-08-31 | 2005-11-15 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
US20050289444A1 (en) * | 2004-06-25 | 2005-12-29 | Klein Dean A | Low power cost-effective ECC memory system and method |
US20060010339A1 (en) * | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
US20060013052A1 (en) * | 2004-07-15 | 2006-01-19 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
DE102004055046A1 (en) * | 2004-11-15 | 2006-05-24 | Infineon Technologies Ag | Semiconductor storage/memory system e.g. for transmission of write and read data signals, has interface circuits set up for transmission of burst lengths of write data |
US20060200723A1 (en) * | 2005-03-03 | 2006-09-07 | International Business Machines Corporation | Method and apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory |
US7131033B1 (en) | 2002-06-21 | 2006-10-31 | Cypress Semiconductor Corp. | Substrate configurable JTAG ID scheme |
WO2007100694A2 (en) * | 2006-02-27 | 2007-09-07 | Intel Corporation | Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode |
EP1837881A1 (en) | 2006-03-24 | 2007-09-26 | Fujitsu Ltd. | Redundancy-function-equipped semiconductor memory device from ECC memory |
EP1875477A2 (en) * | 2005-03-24 | 2008-01-09 | Freescale Semiconductor, Inc. | Memory having a portion that can be switched between use as data and use as error correction code (ecc) |
US20080092016A1 (en) * | 2006-10-11 | 2008-04-17 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US20080109705A1 (en) * | 2006-10-18 | 2008-05-08 | Pawlowski J Thomas | Memory system and method using ECC with flag bit to identify modified data |
US20090063787A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity |
US20090063784A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System for Enhancing the Memory Bandwidth Available Through a Memory Module |
US20090063731A1 (en) * | 2007-09-05 | 2009-03-05 | Gower Kevin C | Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel |
US20090063730A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel |
US20090063922A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module |
US20090063923A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System and Method for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel |
US20090063761A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | Buffered Memory Module Supporting Two Independent Memory Channels |
US20090193200A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Support a Full Asynchronous Interface within a Memory Hub Device |
US20090193315A1 (en) * | 2008-01-24 | 2009-07-30 | Gower Kevin C | System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel |
US20090193201A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Increase the Overall Bandwidth of a Memory Channel By Allowing the Memory Channel to Operate at a Frequency Independent from a Memory Device Frequency |
US20090193203A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency |
US20090190427A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Enable a Memory Hub Device to Manage Thermal Conditions at a Memory Device Level Transparent to a Memory Controller |
US20090193290A1 (en) * | 2008-01-24 | 2009-07-30 | Arimilli Ravi K | System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem |
US7818640B1 (en) | 2004-10-22 | 2010-10-19 | Cypress Semiconductor Corporation | Test system having a master/slave JTAG controller |
US7861014B2 (en) | 2007-08-31 | 2010-12-28 | International Business Machines Corporation | System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel |
US20110004709A1 (en) * | 2007-09-05 | 2011-01-06 | Gower Kevin C | Method for Enhancing the Memory Bandwidth Available Through a Memory Module |
US20110016278A1 (en) * | 2008-03-31 | 2011-01-20 | Frederick Ware | Independent Threading of Memory Devices Disposed on Memory Modules |
US7899983B2 (en) | 2007-08-31 | 2011-03-01 | International Business Machines Corporation | Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module |
US7930469B2 (en) | 2008-01-24 | 2011-04-19 | International Business Machines Corporation | System to provide memory system power reduction without reducing overall memory system performance |
CN103198020A (en) * | 2013-03-18 | 2013-07-10 | 山东华芯半导体有限公司 | Method for prolonging service life of flash memory |
US8910017B2 (en) | 2012-07-02 | 2014-12-09 | Sandisk Technologies Inc. | Flash memory with random partition |
US9997233B1 (en) | 2015-10-08 | 2018-06-12 | Rambus Inc. | Memory module with dynamic stripe width |
US10565050B2 (en) | 2017-08-10 | 2020-02-18 | Samsung Electronics Co., Ltd. | Memory controller, memory system and application processor comprising the memory controller |
US10606692B2 (en) * | 2017-12-20 | 2020-03-31 | International Business Machines Corporation | Error correction potency improvement via added burst beats in a dram access cycle |
US10884852B2 (en) | 2018-02-13 | 2021-01-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4627411B2 (en) * | 2003-05-20 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | Memory device and memory error correction method |
US7774684B2 (en) * | 2006-06-30 | 2010-08-10 | Intel Corporation | Reliability, availability, and serviceability in a memory device |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4527251A (en) * | 1982-12-17 | 1985-07-02 | Honeywell Information Systems Inc. | Remap method and apparatus for a memory system which uses partially good memory devices |
US4612640A (en) * | 1984-02-21 | 1986-09-16 | Seeq Technology, Inc. | Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array |
US5014187A (en) * | 1987-08-20 | 1991-05-07 | International Business Machines Corp. | Adapting device for accommodating different memory and bus formats |
US5109521A (en) * | 1986-09-08 | 1992-04-28 | Compaq Computer Corporation | System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory |
US5261064A (en) * | 1989-10-03 | 1993-11-09 | Advanced Micro Devices, Inc. | Burst access memory |
US5278964A (en) * | 1990-10-12 | 1994-01-11 | Intel Corporation | Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache |
US5293593A (en) * | 1990-10-11 | 1994-03-08 | Hewlett-Packard Company | Method and apparatus for the mapping of physically non-contiguous memory fragments to be linearly addressable |
US5386540A (en) * | 1991-09-18 | 1995-01-31 | Ncr Corporation | Method and apparatus for transferring data within a computer using a burst sequence which includes modified bytes and a minimum number of unmodified bytes |
US5410512A (en) * | 1992-05-22 | 1995-04-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5537573A (en) * | 1993-05-28 | 1996-07-16 | Rambus, Inc. | Cache system and method for prefetching of data |
US5638334A (en) * | 1990-04-18 | 1997-06-10 | Rambus Inc. | Integrated circuit I/O using a high performance bus interface |
-
1997
- 1997-04-04 US US08/833,371 patent/US5896404A/en not_active Expired - Lifetime
-
1998
- 1998-03-31 AR ARP980101456A patent/AR012214A1/en not_active Application Discontinuation
- 1998-04-01 JP JP08835198A patent/JP3714580B2/en not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4527251A (en) * | 1982-12-17 | 1985-07-02 | Honeywell Information Systems Inc. | Remap method and apparatus for a memory system which uses partially good memory devices |
US4612640A (en) * | 1984-02-21 | 1986-09-16 | Seeq Technology, Inc. | Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array |
US5109521A (en) * | 1986-09-08 | 1992-04-28 | Compaq Computer Corporation | System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory |
US5014187A (en) * | 1987-08-20 | 1991-05-07 | International Business Machines Corp. | Adapting device for accommodating different memory and bus formats |
US5261064A (en) * | 1989-10-03 | 1993-11-09 | Advanced Micro Devices, Inc. | Burst access memory |
US5638334A (en) * | 1990-04-18 | 1997-06-10 | Rambus Inc. | Integrated circuit I/O using a high performance bus interface |
US5293593A (en) * | 1990-10-11 | 1994-03-08 | Hewlett-Packard Company | Method and apparatus for the mapping of physically non-contiguous memory fragments to be linearly addressable |
US5278964A (en) * | 1990-10-12 | 1994-01-11 | Intel Corporation | Microprocessor system including a cache controller which remaps cache address bits to confine page data to a particular block of cache |
US5386540A (en) * | 1991-09-18 | 1995-01-31 | Ncr Corporation | Method and apparatus for transferring data within a computer using a burst sequence which includes modified bytes and a minimum number of unmodified bytes |
US5410512A (en) * | 1992-05-22 | 1995-04-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5537573A (en) * | 1993-05-28 | 1996-07-16 | Rambus, Inc. | Cache system and method for prefetching of data |
Cited By (130)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU757596B2 (en) * | 1997-09-29 | 2003-02-27 | Nec Corporation | Storage |
US6526537B2 (en) * | 1997-09-29 | 2003-02-25 | Nec Corporation | Storage for generating ECC and adding ECC to data |
US6662333B1 (en) * | 2000-02-04 | 2003-12-09 | Hewlett-Packard Development Company, L.P. | Shared error correction for memory design |
US6889307B1 (en) | 2001-11-16 | 2005-05-03 | Matrix Semiconductor, Inc. | Integrated circuit incorporating dual organization memory array |
DE10249652A1 (en) * | 2001-12-21 | 2003-07-03 | Hynix Semiconductor Inc | Semiconductor memory device |
US20030117882A1 (en) * | 2001-12-21 | 2003-06-26 | Kim Tae Yun | Semiconductor memory device |
US6771558B2 (en) | 2001-12-21 | 2004-08-03 | Hynix Semiconductor Inc. | Semiconductor memory device |
US20070242551A1 (en) * | 2002-02-11 | 2007-10-18 | Micron Technology, Inc. | User selectable banks for DRAM |
US20040165468A1 (en) * | 2002-02-11 | 2004-08-26 | Micron Technology, Inc. | User selectable banks for dram |
US7995420B2 (en) | 2002-02-11 | 2011-08-09 | Round Rock Research, Llc | User selectable banks for DRAM |
US7636271B2 (en) * | 2002-02-11 | 2009-12-22 | Micron Technology, Inc. | User selectable banks for DRAM |
US7203122B2 (en) * | 2002-02-11 | 2007-04-10 | Micron Technology, Inc. | User selectable banks for DRAM |
US20100097878A1 (en) * | 2002-02-11 | 2010-04-22 | Micron Technology, Inc. | User selectable banks for dram |
US7131033B1 (en) | 2002-06-21 | 2006-10-31 | Cypress Semiconductor Corp. | Substrate configurable JTAG ID scheme |
US8156262B2 (en) | 2002-07-10 | 2012-04-10 | Round Rock Research, Llc | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction |
US7984207B2 (en) | 2002-07-10 | 2011-07-19 | Round Rock Research, Llc | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction |
US20040010637A1 (en) * | 2002-07-10 | 2004-01-15 | Johnson Christopher S. | User defined burst length |
US7603493B2 (en) | 2002-07-10 | 2009-10-13 | Micron Technology, Inc. | Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction |
US20060090056A1 (en) * | 2002-07-10 | 2006-04-27 | Johnson Christopher S | Dynamically setting burst length and type |
US20090307446A1 (en) * | 2002-07-10 | 2009-12-10 | Johnson Christopher S | Dynamically setting burst length of a double data rate memory device |
US8019913B2 (en) | 2002-07-10 | 2011-09-13 | Round Rock Research, Llc | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction |
US8281052B2 (en) | 2002-07-10 | 2012-10-02 | Round Rock Research, Llc | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction |
US7149824B2 (en) | 2002-07-10 | 2006-12-12 | Micron Technology, Inc. | Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction |
US20040083334A1 (en) * | 2002-10-28 | 2004-04-29 | Sandisk Corporation | Method and apparatus for managing the integrity of data in non-volatile memory system |
US8689077B2 (en) | 2004-05-06 | 2014-04-01 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US20090024884A1 (en) * | 2004-05-06 | 2009-01-22 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US7428687B2 (en) | 2004-05-06 | 2008-09-23 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US7836374B2 (en) | 2004-05-06 | 2010-11-16 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US7447974B2 (en) | 2004-05-06 | 2008-11-04 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US7099221B2 (en) | 2004-05-06 | 2006-08-29 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US7447973B2 (en) | 2004-05-06 | 2008-11-04 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US9064600B2 (en) | 2004-05-06 | 2015-06-23 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US20050249010A1 (en) * | 2004-05-06 | 2005-11-10 | Klein Dean A | Memory controller method and system compensating for memory cell data losses |
US20060056259A1 (en) * | 2004-05-06 | 2006-03-16 | Klein Dean A | Memory controller method and system compensating for memory cell data losses |
US20060069856A1 (en) * | 2004-05-06 | 2006-03-30 | Klein Dean A | Memory controller method and system compensating for memory cell data losses |
US20060056260A1 (en) * | 2004-05-06 | 2006-03-16 | Klein Dean A | Memory controller method and system compensating for memory cell data losses |
US20060206769A1 (en) * | 2004-06-24 | 2006-09-14 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
US7461320B2 (en) | 2004-06-24 | 2008-12-02 | Micron Technology, Inc. | Memory system and method having selective ECC during low power refresh |
US20060010339A1 (en) * | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
US7526713B2 (en) | 2004-06-25 | 2009-04-28 | Micron Technology, Inc. | Low power cost-effective ECC memory system and method |
US7340668B2 (en) | 2004-06-25 | 2008-03-04 | Micron Technology, Inc. | Low power cost-effective ECC memory system and method |
US20050289444A1 (en) * | 2004-06-25 | 2005-12-29 | Klein Dean A | Low power cost-effective ECC memory system and method |
US20060218469A1 (en) * | 2004-06-25 | 2006-09-28 | Klein Dean A | Low power cost-effective ECC memory system and method |
US7558142B2 (en) | 2004-07-15 | 2009-07-07 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US7623392B2 (en) | 2004-07-15 | 2009-11-24 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US7116602B2 (en) | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US7898892B2 (en) | 2004-07-15 | 2011-03-01 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US7272066B2 (en) | 2004-07-15 | 2007-09-18 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US20080002503A1 (en) * | 2004-07-15 | 2008-01-03 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
US20060158950A1 (en) * | 2004-07-15 | 2006-07-20 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
US20060152989A1 (en) * | 2004-07-15 | 2006-07-13 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
US8279683B2 (en) | 2004-07-15 | 2012-10-02 | Micron Technology, Inc. | Digit line comparison circuits |
US7277345B2 (en) | 2004-07-15 | 2007-10-02 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US8446783B2 (en) | 2004-07-15 | 2013-05-21 | Micron Technology, Inc. | Digit line comparison circuits |
US7280386B2 (en) | 2004-07-15 | 2007-10-09 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US20060013052A1 (en) * | 2004-07-15 | 2006-01-19 | Klein Dean A | Method and system for controlling refresh to avoid memory cell data losses |
US20060044913A1 (en) * | 2004-08-31 | 2006-03-02 | Klein Dean A | Memory system and method using ECC to achieve low power refresh |
US6965537B1 (en) | 2004-08-31 | 2005-11-15 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
US7184352B2 (en) | 2004-08-31 | 2007-02-27 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
US7818640B1 (en) | 2004-10-22 | 2010-10-19 | Cypress Semiconductor Corporation | Test system having a master/slave JTAG controller |
DE102004055046B8 (en) * | 2004-11-15 | 2009-01-22 | Qimonda Ag | A semiconductor memory system and method for transmitting write and read data signals in a semiconductor memory system |
DE102004055046B4 (en) * | 2004-11-15 | 2008-10-09 | Qimonda Ag | A semiconductor memory system and method for transmitting write and read data signals in a semiconductor memory system |
DE102004055046A1 (en) * | 2004-11-15 | 2006-05-24 | Infineon Technologies Ag | Semiconductor storage/memory system e.g. for transmission of write and read data signals, has interface circuits set up for transmission of burst lengths of write data |
US7451380B2 (en) * | 2005-03-03 | 2008-11-11 | International Business Machines Corporation | Method for implementing enhanced vertical ECC storage in a dynamic random access memory |
US20080294841A1 (en) * | 2005-03-03 | 2008-11-27 | International Business Machines Corporation | Apparatus for implementing enhanced vertical ecc storage in a dynamic random access memory |
US7783957B2 (en) | 2005-03-03 | 2010-08-24 | International Business Machines Corporation | Apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory |
US20060200723A1 (en) * | 2005-03-03 | 2006-09-07 | International Business Machines Corporation | Method and apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory |
EP1875477A2 (en) * | 2005-03-24 | 2008-01-09 | Freescale Semiconductor, Inc. | Memory having a portion that can be switched between use as data and use as error correction code (ecc) |
EP1875477A4 (en) * | 2005-03-24 | 2008-12-17 | Freescale Semiconductor Inc | Memory having a portion that can be switched between use as data and use as error correction code (ecc) |
WO2007100694A2 (en) * | 2006-02-27 | 2007-09-07 | Intel Corporation | Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode |
WO2007100694A3 (en) * | 2006-02-27 | 2007-11-01 | Intel Corp | Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode |
US20070220401A1 (en) * | 2006-02-27 | 2007-09-20 | Intel Corporation | Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode |
US7734985B2 (en) | 2006-02-27 | 2010-06-08 | Intel Corporation | Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode |
EP1837881A1 (en) | 2006-03-24 | 2007-09-26 | Fujitsu Ltd. | Redundancy-function-equipped semiconductor memory device from ECC memory |
US20070255981A1 (en) * | 2006-03-24 | 2007-11-01 | Fujitsu Limited | Redundancy-function-equipped semiconductor memory device made from ECC memory |
US20080092016A1 (en) * | 2006-10-11 | 2008-04-17 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US8832522B2 (en) | 2006-10-11 | 2014-09-09 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US20110138251A1 (en) * | 2006-10-11 | 2011-06-09 | Pawlowski J Thomas | Memory system and method using partial ecc to achieve low power refresh and fast access to data |
US9286161B2 (en) | 2006-10-11 | 2016-03-15 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US8359517B2 (en) | 2006-10-11 | 2013-01-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US7894289B2 (en) | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US8601341B2 (en) | 2006-10-18 | 2013-12-03 | Micron Technologies, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US8413007B2 (en) | 2006-10-18 | 2013-04-02 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US8880974B2 (en) | 2006-10-18 | 2014-11-04 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US20080109705A1 (en) * | 2006-10-18 | 2008-05-08 | Pawlowski J Thomas | Memory system and method using ECC with flag bit to identify modified data |
US7900120B2 (en) | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US7865674B2 (en) | 2007-08-31 | 2011-01-04 | International Business Machines Corporation | System for enhancing the memory bandwidth available through a memory module |
US20090063730A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel |
US20090063787A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity |
US7861014B2 (en) | 2007-08-31 | 2010-12-28 | International Business Machines Corporation | System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel |
US7899983B2 (en) | 2007-08-31 | 2011-03-01 | International Business Machines Corporation | Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module |
US7840748B2 (en) | 2007-08-31 | 2010-11-23 | International Business Machines Corporation | Buffered memory module with multiple memory device data interface ports supporting double the memory capacity |
US7818497B2 (en) | 2007-08-31 | 2010-10-19 | International Business Machines Corporation | Buffered memory module supporting two independent memory channels |
US20090063784A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System for Enhancing the Memory Bandwidth Available Through a Memory Module |
US8082482B2 (en) | 2007-08-31 | 2011-12-20 | International Business Machines Corporation | System for performing error correction operations in a memory hub device of a memory module |
US8086936B2 (en) | 2007-08-31 | 2011-12-27 | International Business Machines Corporation | Performing error correction at a memory device level that is transparent to a memory channel |
US20090063922A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module |
US20090063923A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | System and Method for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel |
US20090063761A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | Buffered Memory Module Supporting Two Independent Memory Channels |
US7584308B2 (en) | 2007-08-31 | 2009-09-01 | International Business Machines Corporation | System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel |
US7558887B2 (en) | 2007-09-05 | 2009-07-07 | International Business Machines Corporation | Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel |
US8019919B2 (en) | 2007-09-05 | 2011-09-13 | International Business Machines Corporation | Method for enhancing the memory bandwidth available through a memory module |
US20110004709A1 (en) * | 2007-09-05 | 2011-01-06 | Gower Kevin C | Method for Enhancing the Memory Bandwidth Available Through a Memory Module |
US20090063731A1 (en) * | 2007-09-05 | 2009-03-05 | Gower Kevin C | Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel |
US20090193201A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Increase the Overall Bandwidth of a Memory Channel By Allowing the Memory Channel to Operate at a Frequency Independent from a Memory Device Frequency |
US7770077B2 (en) | 2008-01-24 | 2010-08-03 | International Business Machines Corporation | Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem |
US20090193203A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency |
US20090190427A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Enable a Memory Hub Device to Manage Thermal Conditions at a Memory Device Level Transparent to a Memory Controller |
US20090193315A1 (en) * | 2008-01-24 | 2009-07-30 | Gower Kevin C | System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel |
US20090193200A1 (en) * | 2008-01-24 | 2009-07-30 | Brittain Mark A | System to Support a Full Asynchronous Interface within a Memory Hub Device |
US20090193290A1 (en) * | 2008-01-24 | 2009-07-30 | Arimilli Ravi K | System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem |
US7925825B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to support a full asynchronous interface within a memory hub device |
US8140936B2 (en) | 2008-01-24 | 2012-03-20 | International Business Machines Corporation | System for a combined error correction code and cyclic redundancy check code for a memory channel |
US7930470B2 (en) | 2008-01-24 | 2011-04-19 | International Business Machines Corporation | System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller |
US7930469B2 (en) | 2008-01-24 | 2011-04-19 | International Business Machines Corporation | System to provide memory system power reduction without reducing overall memory system performance |
US7925824B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency |
US7925826B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency |
US20110016278A1 (en) * | 2008-03-31 | 2011-01-20 | Frederick Ware | Independent Threading of Memory Devices Disposed on Memory Modules |
US8910017B2 (en) | 2012-07-02 | 2014-12-09 | Sandisk Technologies Inc. | Flash memory with random partition |
CN103198020A (en) * | 2013-03-18 | 2013-07-10 | 山东华芯半导体有限公司 | Method for prolonging service life of flash memory |
CN103198020B (en) * | 2013-03-18 | 2016-05-25 | 山东华芯半导体有限公司 | A kind of flash memory method in service life that improves |
US9997233B1 (en) | 2015-10-08 | 2018-06-12 | Rambus Inc. | Memory module with dynamic stripe width |
US10734064B1 (en) | 2015-10-08 | 2020-08-04 | Rambus Inc. | Controlling a dynamic-stripe-width memory module |
US11264085B1 (en) | 2015-10-08 | 2022-03-01 | Rambus Inc. | Memory component for deployment in a dynamic stripe width memory system |
US11862236B1 (en) | 2015-10-08 | 2024-01-02 | Rambus Inc. | Memory component for deployment in a dynamic stripe width memory system |
US10565050B2 (en) | 2017-08-10 | 2020-02-18 | Samsung Electronics Co., Ltd. | Memory controller, memory system and application processor comprising the memory controller |
US11061763B2 (en) | 2017-08-10 | 2021-07-13 | Samsung Electronics Co., Ltd. | Memory controller, memory system and application processor comprising the memory controller |
US10606692B2 (en) * | 2017-12-20 | 2020-03-31 | International Business Machines Corporation | Error correction potency improvement via added burst beats in a dram access cycle |
US10884852B2 (en) | 2018-02-13 | 2021-01-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices |
US11216339B2 (en) | 2018-02-13 | 2022-01-04 | Samsung Electronics Co., Ltd. | Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices |
Also Published As
Publication number | Publication date |
---|---|
AR012214A1 (en) | 2000-09-27 |
JP3714580B2 (en) | 2005-11-09 |
JPH10283797A (en) | 1998-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5896404A (en) | Programmable burst length DRAM | |
US6070262A (en) | Reconfigurable I/O DRAM | |
US5519664A (en) | Dynamic random access memory persistent page implemented as processor register sets | |
EP0263924B1 (en) | On-chip bit reordering structure | |
KR101428844B1 (en) | Multi-mode memory device and method | |
AU640813B2 (en) | A data processing system including a memory controller for direct or interleave memory accessing | |
US5421000A (en) | Memory subsystem having a static row memory and a dynamic RAM | |
US4654781A (en) | Byte addressable memory for variable length instructions and data | |
US6178517B1 (en) | High bandwidth DRAM with low operating power modes | |
EP0245882A2 (en) | Data processing system including dynamic random access memory controller with multiple independent control channels | |
US8341328B2 (en) | Method and system for local memory addressing in single instruction, multiple data computer system | |
JPS6259820B2 (en) | ||
WO1988009970A1 (en) | Set associative memory | |
US6041422A (en) | Fault tolerant memory system | |
KR20070086686A (en) | Micro-threaded memory | |
US5412613A (en) | Memory device having asymmetrical CAS to data input/output mapping and applications thereof | |
US5617555A (en) | Burst random access memory employing sequenced banks of local tri-state drivers | |
US5150328A (en) | Memory organization with arrays having an alternate data port facility | |
US4796222A (en) | Memory structure for nonsequential storage of block bytes in multi-bit chips | |
US5301292A (en) | Page mode comparator decode logic for variable size DRAM types and different interleave options | |
US4992979A (en) | Memory structure for nonsequential storage of block bytes in multi bit chips | |
US5969997A (en) | Narrow data width DRAM with low latency page-hit operations | |
EP1356471A1 (en) | Combined content addressable memories | |
US5630098A (en) | System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks | |
US6138214A (en) | Synchronous dynamic random access memory architecture for sequential burst mode |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KELLOGG, MARK W.;DELL, TIMOTHY J.;HEDBERG, ERIK L.;AND OTHERS;REEL/FRAME:008525/0393 Effective date: 19970404 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |