US5976935A - Method of fabricating an electrically erasable and programmable read-only memory (EEPROM) with improved quality for the tunneling oxide layer therein - Google Patents

Method of fabricating an electrically erasable and programmable read-only memory (EEPROM) with improved quality for the tunneling oxide layer therein Download PDF

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US5976935A
US5976935A US09/149,587 US14958798A US5976935A US 5976935 A US5976935 A US 5976935A US 14958798 A US14958798 A US 14958798A US 5976935 A US5976935 A US 5976935A
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oxide layer
layer
tunneling
substrate
eeprom
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Ying-Jen Lin
Joe Ko
Gary Hong
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

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  • This invention relates to semiconductor fabrication technologies, and more particularly, to a method for fabricating an EEPROM (electrically erasable and programmable read-only memory) device with improved quality for the tunneling oxide layers therein.
  • EEPROM electrically erasable and programmable read-only memory
  • An EEPROM electrically erasable and programmable read-only memory, also abbreviated as E 2 PROM
  • E 2 PROM electrically erasable and programmable read-only memory
  • the EEPROM is more versatile in utilization than other types of ROMs.
  • the data erasure and rewrite operation can be carried out one bit at a time.
  • a conventional single-polysilicon EEPROM device is illustratively depicted in the following with reference to FIGS. 1A-1C.
  • FIG. 1A shows the first step, in which a semiconductor substrate 10 is prepared.
  • a field oxide layer 11 is then formed in a selected area.
  • a first oxide layer 12 is subsequently formed over the entire top surface of the substrate 10 and the field oxide layer 11.
  • the first oxide layer 12 is then selectively removed so as to form a tunneling window 13, exposing a selected area on the substrate 10.
  • a second oxide layer 14 is formed over the entire top surface of the wafer, including the entire first oxide layer 12 and filling the tunneling window 13.
  • FIG. 1B shows the subsequent step, in which a polysilicon layer 15 and a tungsten silicide (WSi) layer 16 are successively formed over the entire top surface of the wafer through, for example, two respective chemical-vapor deposition (CVD) processes.
  • the polysilicon layer 15 and the WSi layer 16 are then selectively removed, allowing the remaining portions of these two layers 15 and 16 that are laid over the tunneling oxide layer 14b on one side of the field oxide layer 11 to serve as a floating gate 17, while the remaining portions of the same over the gate oxide layer 14a on the other side of the field oxide layer 11 serve as a gate 18.
  • FIG. 1C shows the subsequent step, in which a high-voltage ion-implantation (HVI) process is performed on the wafer with the field oxide layer 11, the floating gate 17, and the gate 18 serving as a mask.
  • a heat-treatment process is then performed on the wafer.
  • impurity ions are implanted and driven into the unmasked portions of the substrate 10 to form a pair of source/drain regions 19 in the substrate 10 on both sides of the gate 18.
  • the floating gate 17 is formed from a combination of the WSi layer 16 and the underlying polysilicon layer 15. Since the WSi layer 16 is customarily formed through CVD process, remnant fluorine (F) or chlorine (Cl) atoms can be left in the WSi layer 16. A bad consequence of this can occur when the WSi layer 16 is heated in the subsequent heat-treatment process used to drive ions into the source/drain regions, because stress can occur in the heated WSi and the remnant fluorine or chlorine atoms in the WSi layer 16 can be diffused into the tunneling oxide layer 14b. This turns the tunneling oxide layer 14b into a trapping center. During operation of the EEPROM device, the electric charges caught in the trapping center cause uneven and inconsistent electric fields in the tunneling oxide layer 14b, which easily causes breakdown in the tunneling oxide layer 14b. The reliability of the resultant EEPROM device is thus degraded.
  • a new method for fabricating an EEPROM device includes the following steps:
  • the foregoing method of invention is characterized in that the portion of the WSi layer that is directly laid above the tunneling oxide layer is removed.
  • the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented.
  • the quality of the tunneling oxide layer is thus more controlled, allowing the resultant EEPROM to operate reliably with high performance.
  • FIGS. 1A-1C are schematic sectional diagrams used to depict the steps involved in a conventional method for fabricating an EEPROM device.
  • FIGS. 2A-2E are schematic sectional diagrams used to depict the steps involved in the method according to the invention for fabricating an EEPROM device.
  • FIGS. 2A-2E are schematic sectional diagrams used to depict the steps involved in the method according to the invention for fabricating a single-polysilicon EEPROM device on a semiconductor substrate.
  • the semiconductor substrate is a P-type silicon substrate, but it is to be noted that the semiconductor substrate can also be N-type and selected from various other kinds of semiconductor materials.
  • FIG. 2A shows the first step, in which a semiconductor substrate 20 of a first semiconductor type, such as a P-type silicon substrate, is prepared. A field oxide layer 21 is then formed on a selected area. Subsequently, a first oxide layer 22, such as a layer of silicon dioxide, is formed through CVD process over the entire top surface of the substrate 20 and the field oxide layer 21. The first oxide layer 22 is then selectively removed so as to form a tunneling window 23 to expose a selected area on the substrate 20. Next, a second oxide layer 24, such as a layer of silicon dioxide, is formed through CVD process over the entire top surface of the wafer to a thickness of about 80 ⁇ (angstroms). The second oxide layer 24 covers the entire first oxide layer 22 and fills the tunneling window 23.
  • a first oxide layer 22 such as a layer of silicon dioxide
  • the part of the second oxide layer 24 that fills the tunneling window 23, indicated by the reference numeral 24a, serves as a tunneling oxide layer, all the other parts of the second oxide layer 24 and its underlying first oxide layer 22 serve in combination as a gate oxide layer, here collectively indicated by the reference numeral 25.
  • FIG. 2B shows the subsequent step, in which a polysilicon layer 26 is formed over the entire top surface of the wafer.
  • a layer of tungsten silicide (WSi) 27 is then formed over the entire polysilicon layer 26. Both the polysilicon layer 26 and the WSi layer 27 can be formed through CVD process.
  • a photoresist layer 28 is formed over the entire WSi layer 27, and is then selectively removed to expose the area of the WSi layer 27 directly located above the tunneling oxide layer 24a.
  • FIG. 2C shows the subsequent step, in which the photoresist layer 28 is used as a ask to perform an anisotropic etch-back process on the wafer, whereby the exposed portion of the WSi layer 27 that is unmasked by the photoresist layer 28 is etched away until the top surface of the polysilicon layer 26 is exposed.
  • the photoresist layer 28 is removed.
  • an optional screen oxide layer 29 is formed over the entire wafer, which covers all the exposed surfaces of the WSi layer 27 and the polysilicon layer 26, but still leaving an empty space in the hole left by the removed portion of the WSi layer 27.
  • the adhesion of the WSi layer 27 to the polysilicon layer 26 is poor, and the screen oxide layer 29 can prevent the WSi layer 27 from peeling away from the polysilicon layer 26.
  • the provision of the screen oxide layer 29 is elective.
  • FIG. 2D shows the subsequent step, in which a photolithographic and etching process is performed on the wafer using a photoresist layer 30 as a mask, whereby selected portions of the screen oxide layer 29, the WSi layer 27, and the polysilicon layer 26 are removed.
  • the combination of the remaining portions of the polysilicon layer 26 and WSi layer 27 that lie above the tunneling oxide layer 24a serves as a floating gate 31, while the combination of the remaining portions of the same that are laid on the other side of the field oxide layer 21 serves as a gate 32.
  • HVI high-voltage ion-implantation
  • FIG. 2E shows that after the HVI process is completed, the photoresist layer 30 is first removed, and then a heat-treatment process is performed on the wafer so as to drive those impurity ions in the substrate 20 into the areas 33 (FIG. 2D). Through this process, the areas 33 are formed into a pair of source/drain regions 34.

Abstract

A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87111580, filed Jul. 16, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method for fabricating an EEPROM (electrically erasable and programmable read-only memory) device with improved quality for the tunneling oxide layers therein.
2. Description of Related Art
An EEPROM (electrically erasable and programmable read-only memory, also abbreviated as E2 PROM) is a semiconductor, nonvolatile, programmable read-only memory device whose contents can be electrically erased and then selectively rewritten without having to remove it from its host circuit board. Due to the erasable and programmable feature, the EEPROM is more versatile in utilization than other types of ROMs. In the EEPROM device, the data erasure and rewrite operation can be carried out one bit at a time. A conventional single-polysilicon EEPROM device is illustratively depicted in the following with reference to FIGS. 1A-1C.
FIG. 1A shows the first step, in which a semiconductor substrate 10 is prepared. A field oxide layer 11 is then formed in a selected area. A first oxide layer 12 is subsequently formed over the entire top surface of the substrate 10 and the field oxide layer 11. The first oxide layer 12 is then selectively removed so as to form a tunneling window 13, exposing a selected area on the substrate 10. Next, a second oxide layer 14 is formed over the entire top surface of the wafer, including the entire first oxide layer 12 and filling the tunneling window 13. The part of the second oxide layer 14 that is laid in the tunneling window 13, as indicated by the reference numeral 14b, serves as a tunneling oxide layer; all the other parts of the second oxide layer 14 and its underlying first oxide layer 12 serve in combination as a gate oxide layer, here collectively indicated by the reference numeral 14a.
FIG. 1B shows the subsequent step, in which a polysilicon layer 15 and a tungsten silicide (WSi) layer 16 are successively formed over the entire top surface of the wafer through, for example, two respective chemical-vapor deposition (CVD) processes. The polysilicon layer 15 and the WSi layer 16 are then selectively removed, allowing the remaining portions of these two layers 15 and 16 that are laid over the tunneling oxide layer 14b on one side of the field oxide layer 11 to serve as a floating gate 17, while the remaining portions of the same over the gate oxide layer 14a on the other side of the field oxide layer 11 serve as a gate 18.
FIG. 1C shows the subsequent step, in which a high-voltage ion-implantation (HVI) process is performed on the wafer with the field oxide layer 11, the floating gate 17, and the gate 18 serving as a mask. A heat-treatment process is then performed on the wafer. Through these two processes, impurity ions are implanted and driven into the unmasked portions of the substrate 10 to form a pair of source/drain regions 19 in the substrate 10 on both sides of the gate 18.
In the foregoing method, the floating gate 17 is formed from a combination of the WSi layer 16 and the underlying polysilicon layer 15. Since the WSi layer 16 is customarily formed through CVD process, remnant fluorine (F) or chlorine (Cl) atoms can be left in the WSi layer 16. A bad consequence of this can occur when the WSi layer 16 is heated in the subsequent heat-treatment process used to drive ions into the source/drain regions, because stress can occur in the heated WSi and the remnant fluorine or chlorine atoms in the WSi layer 16 can be diffused into the tunneling oxide layer 14b. This turns the tunneling oxide layer 14b into a trapping center. During operation of the EEPROM device, the electric charges caught in the trapping center cause uneven and inconsistent electric fields in the tunneling oxide layer 14b, which easily causes breakdown in the tunneling oxide layer 14b. The reliability of the resultant EEPROM device is thus degraded.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating an EEPROM device, which can help prevent the tunneling oxide layer from turning into a trapping center in the heat-treatment process so that the quality of the tunneling oxide layer is more carefully controlled.
It is another objective of the present invention to provide a method for fabricating an EEPROM device, which can help improve the quality of the tunneling oxide layer formed in the EEPROM device, and also allow the EEPROM device to operate reliably without being degraded in performance.
In accordance with the foregoing and other objectives of the present invention, a new method for fabricating an EEPROM device is provided. The method of the invention includes the following steps:
(1) preparing a substrate of a first semiconductor type, then forming a field oxide layer on the substrate;
(2) forming a first oxide layer over the substrate, when is then selectively removed to form a tunneling window to expose a selected area on the substrate;
(3) forming a second oxide layer, which covers the first oxide layer and the area of the substrate exposed by the tunneling window, with the part of the second oxide layer that is laid in the tunneling window serving as a tunneling oxide layer, and all the other part of the second oxide layer and the underlying first oxide layer serving as a gate oxide layer;
(4) forming a polysilicon layer, which covers over the entire gate oxide layer and the tunneling oxide layer, and then forming a layer of tungsten silicide over the entire polysilicon layer;
(5) removing a selected portion of the tungsten silicide layer that is laid directly above the tunneling oxide layer;
(6) removing selected portions of the polysilicon layer and the underlying tungsten silicide layer so as to form a floating gate on the tunneling oxide layer and a gate on the gate oxide layer; and
(7) performing an HVI process so as to dope an impurity element of a second semiconductor type into the substrate, and then performing a heat-treatment process so as to form a pair of source/drain regions in the substrate on both sides of the gate.
The foregoing method of invention is characterized in that the portion of the WSi layer that is directly laid above the tunneling oxide layer is removed. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The quality of the tunneling oxide layer is thus more controlled, allowing the resultant EEPROM to operate reliably with high performance.
BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
FIGS. 1A-1C are schematic sectional diagrams used to depict the steps involved in a conventional method for fabricating an EEPROM device; and
FIGS. 2A-2E are schematic sectional diagrams used to depict the steps involved in the method according to the invention for fabricating an EEPROM device.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
FIGS. 2A-2E are schematic sectional diagrams used to depict the steps involved in the method according to the invention for fabricating a single-polysilicon EEPROM device on a semiconductor substrate. In the following preferred embodiment, the semiconductor substrate is a P-type silicon substrate, but it is to be noted that the semiconductor substrate can also be N-type and selected from various other kinds of semiconductor materials.
FIG. 2A shows the first step, in which a semiconductor substrate 20 of a first semiconductor type, such as a P-type silicon substrate, is prepared. A field oxide layer 21 is then formed on a selected area. Subsequently, a first oxide layer 22, such as a layer of silicon dioxide, is formed through CVD process over the entire top surface of the substrate 20 and the field oxide layer 21. The first oxide layer 22 is then selectively removed so as to form a tunneling window 23 to expose a selected area on the substrate 20. Next, a second oxide layer 24, such as a layer of silicon dioxide, is formed through CVD process over the entire top surface of the wafer to a thickness of about 80 Å (angstroms). The second oxide layer 24 covers the entire first oxide layer 22 and fills the tunneling window 23. The part of the second oxide layer 24 that fills the tunneling window 23, indicated by the reference numeral 24a, serves as a tunneling oxide layer, all the other parts of the second oxide layer 24 and its underlying first oxide layer 22 serve in combination as a gate oxide layer, here collectively indicated by the reference numeral 25.
FIG. 2B shows the subsequent step, in which a polysilicon layer 26 is formed over the entire top surface of the wafer. A layer of tungsten silicide (WSi) 27 is then formed over the entire polysilicon layer 26. Both the polysilicon layer 26 and the WSi layer 27 can be formed through CVD process. After this, a photoresist layer 28 is formed over the entire WSi layer 27, and is then selectively removed to expose the area of the WSi layer 27 directly located above the tunneling oxide layer 24a.
FIG. 2C shows the subsequent step, in which the photoresist layer 28 is used as a ask to perform an anisotropic etch-back process on the wafer, whereby the exposed portion of the WSi layer 27 that is unmasked by the photoresist layer 28 is etched away until the top surface of the polysilicon layer 26 is exposed. After this, the photoresist layer 28 is removed. Subsequently, an optional screen oxide layer 29 is formed over the entire wafer, which covers all the exposed surfaces of the WSi layer 27 and the polysilicon layer 26, but still leaving an empty space in the hole left by the removed portion of the WSi layer 27. The adhesion of the WSi layer 27 to the polysilicon layer 26 is poor, and the screen oxide layer 29 can prevent the WSi layer 27 from peeling away from the polysilicon layer 26. The provision of the screen oxide layer 29 is elective.
FIG. 2D shows the subsequent step, in which a photolithographic and etching process is performed on the wafer using a photoresist layer 30 as a mask, whereby selected portions of the screen oxide layer 29, the WSi layer 27, and the polysilicon layer 26 are removed. The combination of the remaining portions of the polysilicon layer 26 and WSi layer 27 that lie above the tunneling oxide layer 24a serves as a floating gate 31, while the combination of the remaining portions of the same that are laid on the other side of the field oxide layer 21 serves as a gate 32. After this, a high-voltage ion-implantation (HVI) process is performed on the wafer so as to dope an impurity element of a second semiconductor type (which is N-type in the case of the substrate 20 being P-type and P-type in the case of the substrate 20 being N-type) into the unmasked areas 33 in the substrate 20 on both sides of the gate 32 (i.e., those areas in the substrate 20 that are unmasked by the photoresist layer 30 and the field oxide layer 21).
FIG. 2E shows that after the HVI process is completed, the photoresist layer 30 is first removed, and then a heat-treatment process is performed on the wafer so as to drive those impurity ions in the substrate 20 into the areas 33 (FIG. 2D). Through this process, the areas 33 are formed into a pair of source/drain regions 34.
The subsequent steps to finish the fabrication of the EEPROM device are all conventional techniques that are not within the spirit of the invention, so description thereof will not be further detailed.
It is a characteristic part of the invention, in contrast to the prior art, that the portion of the WSi layer that is directly laid above the tunneling oxide layer is removed. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.
The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (8)

What is claimed is:
1. A method for fabricating an EEPROM device, comprising:
(1) preparing a substrate of a first semiconductor type, then forming a field oxide layer on the substrate;
(2) forming a first oxide layer over the substrate, which is then selectively removed to form a tunneling window to expose a selected area on the substrate;
(3) forming a second oxide layer, which covers the first oxide layer and the area of the substrate exposed by the tunneling window, with the part of the second oxide layer filling the tunneling window serving as a tunneling oxide layer, and with all the other parts of the second oxide layer and the underlying first oxide layer serving as a gate oxide layer;
(4) forming a polysilicon layer, which covers over the entire gate oxide layer and the tunneling oxide layer, and then forming a layer of tungsten silicide over the entire polysilicon layer;
(5) removing a selected portion of the tungsten silicide layer that is laid directly above the tunneling oxide layer;
(6) removing selected portions of the polysilicon layer and the underlying tungsten silicide layer so as to form a floating gate on the tunneling oxide layer and a gate on the gate oxide layer; and
(7) performing an HVI process so as to dope an impurity element of a second semiconductor type into the substrate, and then performing a heat-treatment process so as to form a pair of source/drain regions in the substrate on both sides of the gate.
2. The method of claim 1, wherein the first semiconductor type is P-type, while the second semiconductor type is N-type.
3. The method of claim 1, wherein the first semiconductor type is N-type, while the second semiconductor type is P-type.
4. The method of claim 1, wherein in the step (2), the first oxide layer is a layer of silicon dioxide.
5. The method of claim 1, wherein in the step (3), the second oxide layer is a layer of silicon dioxide formed through a CVD process.
6. The method of claim 1, wherein in the step (4), the tungsten silicide layer is formed through a CVD process.
7. The method of claim 1, wherein the step (5) further comprises a substep of forming a screen oxide layer, which covers the tungsten silicide layer and the exposed surface of the polysilicon layer.
8. The method of claim 7, wherein the screen oxide layer is a layer of silicon dioxide.
US09/149,587 1998-07-16 1998-09-08 Method of fabricating an electrically erasable and programmable read-only memory (EEPROM) with improved quality for the tunneling oxide layer therein Expired - Lifetime US5976935A (en)

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Cited By (3)

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US6177315B1 (en) * 1999-05-28 2001-01-23 National Semiconductor Corporation Method of fabricating a high density EEPROM array
US6221717B1 (en) * 1998-09-29 2001-04-24 Stmicroelectronics S.R.L. EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell

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US5591658A (en) * 1994-08-30 1997-01-07 National Semiconductor Corporation Method of fabricating integrated circuit chip containing EEPROM and capacitor
US5637520A (en) * 1993-02-11 1997-06-10 Sgs-Thomson Microelectronics S.R.L. Process for fabricating integrated devices including flash-EEPROM memories and transistors
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US5714412A (en) * 1996-12-02 1998-02-03 Taiwan Semiconductor Manufacturing Company, Ltd Multi-level, split-gate, flash memory cell and method of manufacture thereof
US5793081A (en) * 1994-03-25 1998-08-11 Nippon Steel Corporation Nonvolatile semiconductor storage device and method of manufacturing

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US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
US5679970A (en) * 1992-07-03 1997-10-21 Commissariat A L'energie Atomique Triple gate flash-type EEPROM memory and its production process
US5637520A (en) * 1993-02-11 1997-06-10 Sgs-Thomson Microelectronics S.R.L. Process for fabricating integrated devices including flash-EEPROM memories and transistors
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US6221717B1 (en) * 1998-09-29 2001-04-24 Stmicroelectronics S.R.L. EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process
US6177315B1 (en) * 1999-05-28 2001-01-23 National Semiconductor Corporation Method of fabricating a high density EEPROM array
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell

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