US6023097A - Stacked multiple-chip module micro ball grid array packaging - Google Patents

Stacked multiple-chip module micro ball grid array packaging Download PDF

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US6023097A
US6023097A US09/271,214 US27121499A US6023097A US 6023097 A US6023097 A US 6023097A US 27121499 A US27121499 A US 27121499A US 6023097 A US6023097 A US 6023097A
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chips
chip
package
wiring plate
printed wiring
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US09/271,214
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Kuo-Ning Chiang
Wen-Hwa Chen
Kuo-Tai Tseng
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ChipMOS Technologies Bermuda Ltd
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ChipMOS Technologies Inc
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Assigned to CHIPMOS TECHNOLOGIES (BERMUDA) LTD. reassignment CHIPMOS TECHNOLOGIES (BERMUDA) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIPMOS TECHNOLOGIES LTD.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • This invention relates to integrated circuit packaging--in particular to multiple-chip module packaging.
  • MCM Multiple-chip Module
  • a popular packaging technique is the mirco Ball Grid Array ( ⁇ BGA), where the bonding pads of an IC are fed through an insulating substrate via plated through holes to an array of soldering balls for bonding to a printed circuit board. While the ⁇ BGA package has been used for single chip IC, such an approach has not been used for MCM packages.
  • ⁇ BGA mirco Ball Grid Array
  • FIG. 1A shows a conventional single chip using a ⁇ BGA package.
  • An IC chip 10 having bonding pads 12 along the edges connected to a printed wiring plate 14 (printed wiring not shown) with bonding wires 16.
  • the printed wiring plate 14 has vias through which the terminals of the IC are fed to the ball grid array 18 serving as extensions for the IC terminals as shown in FIG. 1C.
  • the IC chip 10 and the printed wiring plate are separated by a resin which serves a cushion to reduce any stress due to difference in thermal expansion of the IC chip 10 and the plated wiring plate 14 and to increase the reliability of the package.
  • the bonding pad arrangement shown in FIGS. 1A, 1B and 1C is not economical for a MCM, because space must be allowed between adjacent IC chips to run interconnections for the chips. When space is allowed between adjacent IC chips, the overall package size of an MCM is increased, as is the cost.
  • An object of this invention is to minimize the package size of a ⁇ BGA MCM package. Another object of this invention is to increase the yield of producing MCM. Still another object of the present invention is to increase the heat dissipation of a MCM. A further object of this invention is to reduce moisture absorption of a MCM package.
  • the adjacent IC chips can share a common printed wiring plate, through which the terminals of the IC chips are fed to an array of soldering ball grids for surface mounting on a printed circuit board.
  • FIG. 1A shows the bonding pads of an IC chip for a conventional ⁇ BGA package
  • FIG. 1B shows another arrangement of bonding pads of IC chip for a conventional ⁇ BGA package
  • FIG. 1C shows a side view of the ⁇ BGA package shown in FIGS. 1A, 1B.
  • FIG. 2A shows the bonding pad arrangement of a four-chip MCM in a ⁇ BGA package
  • FIG. 2B shows the structure of FIG. 2A covered with a feed-through printed wiring plate
  • FIG. 2C shows the side view of the structure shown in FIG. 2B
  • FIG. 2D shows the structure shown in FIG. 2C sealed in resin.
  • FIG. 3 shows the bonding pad arrangement of a stacked three-chip MCM in a ⁇ BGA package.
  • FIG. 4 shows the bonding pad arrangement of a stacked two-chip MCM in a ⁇ BGA package.
  • FIG. 2A shows the bonding pad arrangement of a four IC chip MCM in a BGA package based on the present invention.
  • the four IC chips are 20A, 20B, 20C and 20D.
  • the IC chips 20C and 20D are butted against each other and stacked over the IC chips 20A and 20B, which are also butted against each other.
  • the bonding pads 22A, 22B, 22C and 22D for the four IC chips are aligned along one side of the corresponding IC chips 20A, 20B, 20C and 20D respectively. In so arranged, no space is needed between the butting IC chips, i.e. between chips 20A and 20B, and between chips 20C and 20D, because no space is needed to run interconnections where there is no bonding pad nearby.
  • FIG. 2B shows a printed wiring plate 24 covering the stacked IC chips shown in FIG. 2A.
  • the printed wiring plate is wire bonded to the bonding pads of the IC chips 20A, 20B, 20C and 20D through the bonding wires such as 26A, 26B, 26C and 26C, respectively.
  • FIG. 2C shows the side view of the structure.
  • the printed wiring plate has through holes for connection to the other side of a ball grid array 28.
  • the IC chips such as 20C are separated from the plated wiring plate 24 by a resin cushion 25 to reduce thermal and mechanical stress similar to the cushion 15 shown in FIG. 1C.
  • FIG. 2D shows the structure shown in FIG. 2C is inserted with a heat dissipating plate 27, which can be metal or non-metal.
  • the entire structure is sealed in glue 29 to protect the MCM against shock and moisture.
  • FIG. 3 shows another embodiment of the present invention for a three-chip MCM.
  • the first chip 32A occupies a larger area than two smaller IC chips 30B and 30C which lay over the chip 32A.
  • the two smaller chips are butted against each other.
  • the bonding pads of chips 32B and 32C are placed along one side the respective chips.
  • the bonding pads of the larger chip 32 are placed along two opposite sides not covered by the IC chips 30B and 30C.
  • all the bonding pads lie along the overall edges of the stacked structure, which can then be fed to a ⁇ BGA through a printed wiring plate such as that shown in FIG. 2C.
  • FIG. 4 shows another embodiment of the present invention for a two-chip MCM in a ⁇ BGA A package.
  • an IC chip 40A is larger than a stacked IC chip 40B.
  • the bonding pads 42A of the larger chip 40A are placed vertically at two opposite ends not covered by the smaller IC chip 40B.
  • the bonding pads 42B of the smaller IC chip 40B are placed horizontally along two opposite ends of the IC chip 40B. Thus all the bonding pads of the overall structure are located at the four edges of the overall stacked structure.
  • connection can also be implemented with flip-chip or wire-bonding technique.

Abstract

A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are stacked to save space. The bonding pads for the lower IC chip or chips are placed along the edges where the pads are not masked by the stacking of the upper chip or chips. When there are more than one chip at each level of the stacking, the IC chips at each level are butted with each other to further save space. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be inserted at the bottom of the IC chips away from the stacking surface.

Description

INTRODUCTION
This invention relates to integrated circuit packaging--in particular to multiple-chip module packaging.
As memory capacity of an integrated circuit chip increases from 4M, 16M, 64M, 128M to 256M, the manufacturing difficulty also increases and the manufacturing yield decreases. Another approach in increasing the memory capacity is to increase the packaging technique. For instance, a 128M memory can be obtained by packaging two 64M chips in one package, known as Multiple-chip Module (MCM). In this manner, the yield can be increased and the manufacturing difficulty can be reduced.
As integrated circuit functionality, performance and density continue to increase innovative next generation packaging approaches are in great demand. A popular packaging technique is the mirco Ball Grid Array (μBGA), where the bonding pads of an IC are fed through an insulating substrate via plated through holes to an array of soldering balls for bonding to a printed circuit board. While the μBGA package has been used for single chip IC, such an approach has not been used for MCM packages.
FIG. 1A shows a conventional single chip using a μBGA package. An IC chip 10 having bonding pads 12 along the edges connected to a printed wiring plate 14 (printed wiring not shown) with bonding wires 16. The printed wiring plate 14 has vias through which the terminals of the IC are fed to the ball grid array 18 serving as extensions for the IC terminals as shown in FIG. 1C. The IC chip 10 and the printed wiring plate are separated by a resin which serves a cushion to reduce any stress due to difference in thermal expansion of the IC chip 10 and the plated wiring plate 14 and to increase the reliability of the package.
The bonding pad arrangement shown in FIGS. 1A, 1B and 1C is not economical for a MCM, because space must be allowed between adjacent IC chips to run interconnections for the chips. When space is allowed between adjacent IC chips, the overall package size of an MCM is increased, as is the cost.
SUMMARY
An object of this invention is to minimize the package size of a μBGA MCM package. Another object of this invention is to increase the yield of producing MCM. Still another object of the present invention is to increase the heat dissipation of a MCM. A further object of this invention is to reduce moisture absorption of a MCM package.
These objects are achieved by stacking and butting the IC chips of a MCM and rearranging the design of the bonding pads in the IC chips. The adjacent IC chips can share a common printed wiring plate, through which the terminals of the IC chips are fed to an array of soldering ball grids for surface mounting on a printed circuit board.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows the bonding pads of an IC chip for a conventional μBGA package;
FIG. 1B shows another arrangement of bonding pads of IC chip for a conventional μBGA package;
FIG. 1C shows a side view of the μBGA package shown in FIGS. 1A, 1B.
FIG. 2A shows the bonding pad arrangement of a four-chip MCM in a μBGA package;
FIG. 2B shows the structure of FIG. 2A covered with a feed-through printed wiring plate;
FIG. 2C shows the side view of the structure shown in FIG. 2B;
FIG. 2D shows the structure shown in FIG. 2C sealed in resin.
FIG. 3 shows the bonding pad arrangement of a stacked three-chip MCM in a μBGA package.
FIG. 4 shows the bonding pad arrangement of a stacked two-chip MCM in a μBGA package.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 2A shows the bonding pad arrangement of a four IC chip MCM in a BGA package based on the present invention. The four IC chips are 20A, 20B, 20C and 20D. The IC chips 20C and 20D are butted against each other and stacked over the IC chips 20A and 20B, which are also butted against each other. The bonding pads 22A, 22B, 22C and 22D for the four IC chips are aligned along one side of the corresponding IC chips 20A, 20B, 20C and 20D respectively. In so arranged, no space is needed between the butting IC chips, i.e. between chips 20A and 20B, and between chips 20C and 20D, because no space is needed to run interconnections where there is no bonding pad nearby.
FIG. 2B shows a printed wiring plate 24 covering the stacked IC chips shown in FIG. 2A. The printed wiring plate is wire bonded to the bonding pads of the IC chips 20A, 20B, 20C and 20D through the bonding wires such as 26A, 26B, 26C and 26C, respectively.
FIG. 2C shows the side view of the structure. The printed wiring plate has through holes for connection to the other side of a ball grid array 28. The IC chips such as 20C are separated from the plated wiring plate 24 by a resin cushion 25 to reduce thermal and mechanical stress similar to the cushion 15 shown in FIG. 1C.
FIG. 2D shows the structure shown in FIG. 2C is inserted with a heat dissipating plate 27, which can be metal or non-metal. The entire structure is sealed in glue 29 to protect the MCM against shock and moisture.
FIG. 3 shows another embodiment of the present invention for a three-chip MCM. The first chip 32A occupies a larger area than two smaller IC chips 30B and 30C which lay over the chip 32A. The two smaller chips are butted against each other. As in FIG. 2A, the bonding pads of chips 32B and 32C are placed along one side the respective chips. However, the bonding pads of the larger chip 32 are placed along two opposite sides not covered by the IC chips 30B and 30C. Thus, all the bonding pads lie along the overall edges of the stacked structure, which can then be fed to a μBGA through a printed wiring plate such as that shown in FIG. 2C.
FIG. 4 shows another embodiment of the present invention for a two-chip MCM in a μBGA A package. In this embodiment, an IC chip 40A is larger than a stacked IC chip 40B. The bonding pads 42A of the larger chip 40A are placed vertically at two opposite ends not covered by the smaller IC chip 40B. The bonding pads 42B of the smaller IC chip 40B are placed horizontally along two opposite ends of the IC chip 40B. Thus all the bonding pads of the overall structure are located at the four edges of the overall stacked structure.
While all the embodiments described use lead bond for connecting the IC chips to the common substrate, it should be obvious that the connection can also be implemented with flip-chip or wire-bonding technique.
While the preferred embodiments have been shown and described, it will be apparent to those skilled in the art that various modifications may be made in the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of this invention.

Claims (8)

What is claimed is:
1. A ball grid array (BGA) package for a multiple chip module (MCM), comprising:
at least two integrated circuit (IC) chips stacking over one and another;
bonding pads for said placed along edges of said IC chips not covered by said stacking; and
a printed wiring plate having a first side connected to said bonding pads and having through holes connected to a second side with said BGA.
2. A BGA package as described in claim 1, wherein there are four said IC chips, with two smaller IC chips of said four IC chips butting against each other and stacking over two larger butted IC chips of said four IC chips.
3. A BGA package as described in claim 1, wherein there are three said IC chips, with two smaller IC chips of said three IC chips butting against each other and stacking over a larger IC chip of said three IC chips.
4. A BGA package as described in claim 1, wherein there are two said IC chips with the smaller of said two IC chips stacking over the larger of said two IC chips.
5. A BGA package as described in claim 1, wherein said the IC chips are separated from said printed wiring plate by a cushion.
6. A BGA package as described in claim 5, wherein said cushion is a resin.
7. A BGA package as described in claim 5, wherein said package is sealed in a glue.
8. A BGA package as described in claim 1, further comprising a heat dissipating plate contacting the surface of said IC chips away from the interface where said IC chips are stacked and from the plated wiring plate.
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US6384332B1 (en) * 1999-11-30 2002-05-07 Bombardier Motor Corporation Of America Bladder insert for encapsulant displacement
US6440775B2 (en) 2000-06-19 2002-08-27 Advantest Corporation Method and apparatus for edge connection between elements of an integrated circuit
US6541847B1 (en) 2002-02-04 2003-04-01 International Business Machines Corporation Packaging for multi-processor shared-memory system
US20040195668A1 (en) * 2003-02-06 2004-10-07 Toshihiro Sawamoto Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
US20040217380A1 (en) * 2003-02-25 2004-11-04 Akiyoshi Aoyagi Semiconductor device, electronic device, electronic apparatus, method for manufacturing a semiconductor device, and method for manufacturing an electronic device
US20040222519A1 (en) * 2003-03-18 2004-11-11 Akiyoshi Aoyagi Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
US20040222534A1 (en) * 2003-02-07 2004-11-11 Toshihiro Sawamoto Semiconductor device, electronic device, electronic equipment, method of manufacturing semiconductor device, and method of manufacturing electronic device
US20040222510A1 (en) * 2003-03-24 2004-11-11 Akiyoshi Aoyagi Semiconductor device, semiconductor pack age, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device
US20040222508A1 (en) * 2003-03-18 2004-11-11 Akiyoshi Aoyagi Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
US20040227223A1 (en) * 2003-03-17 2004-11-18 Toshihiro Sawamoto Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing semiconductor device and electronic device
US20040227236A1 (en) * 2003-03-17 2004-11-18 Toshihiro Sawamoto Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing carrier substrate, semiconductor device, and electronic device
US20050110166A1 (en) * 2003-03-18 2005-05-26 Akiyoshi Aoyagi Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
US20050184379A1 (en) * 2003-03-25 2005-08-25 Masakuni Shiozawa Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device
US20070210447A1 (en) * 2006-03-07 2007-09-13 Kinsley Thomas H Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems and methods

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