1. An input/output structure for a programmable logic device that accommodates a plurality of logic signalling standards having differing power requirements, said input/output structure comprising:
- a plurality of input/output terminals;
- a plurality of input/output circuits associated with said plurality of input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic device; and
- a plurality of power bus conductors; wherein:
- when a respective one of said plurality of input/output circuits is operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor provides power compatible with power requirements of said one of said standards in accordance with which said respective circuit is operated.
2. The input/output structure of claim 1 wherein each of said power bus conductors is spatially disposed adjacent a respective subset of said plurality of input/output circuits; wherein:
- when circuits in each respective subset of said plurality of input/output circuits are operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor adjacent each respective subset provides power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.
3. The input/output structure of claim 2 wherein at least two of said power conductors are disposed adjacent each said respective subset, whereby when circuits in said respective subset are operated in accordance with a logic signalling standard requiring a reference voltage, one of said at least two power conductors provides supply voltage and one of said at least two power conductors provides said reference voltage.
4. The input/output structure of claim 2 wherein:
- said plurality of input/output circuits are arranged substantially adjacent one or more edges of said programmable logic device; and
- said power conductors are arranged parallel to said one or more edges.
5. The input/output structure of claim 2 wherein:
- said plurality of input/output circuits are arranged in an array using bump array technology; and
- said power conductors are arranged in banks relative to said array.
6. A programmable logic device that programmably accommodates a plurality of logic signalling standards having differing power requirements, said programmable logic device comprising:
- programmable logic elements;
- an interconnect structure connecting said programmable logic elements;
- a plurality of input/output terminals;
- a plurality of input/output circuits connected to said interconnect structure and to said input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic elements; and
- a plurality of power bus conductors; wherein:
- when a respective one of said plurality of input/output circuits is operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor provides power compatible with power requirements of said one of said standards in accordance with which said respective circuit is operated.
7. The programmable logic device of claim 6 wherein:
- each of said power bus conductors is spatially disposed adjacent a respective subset of said plurality of input/output circuits; and
- when circuits in each respective subset of said plurality of input/output circuits are operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor adjacent each respective subset provides power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.
8. The programmable logic device of claim 7 wherein at least two of said power conductors are disposed adjacent each said respective subset, whereby when circuits in said respective subset are operated in accordance with a logic signalling standard requiring a reference voltage, one of said at least two power conductors provides supply voltage and one of said at least two power conductors provides said reference voltage.
9. The programmable logic device of claim 7 wherein:
- said plurality of input/output circuits are arranged substantially adjacent one or more edges of said programmable logic device; and
- said power conductors are arranged parallel to said one or more edges.
10. The programmable logic device of claim 7 wherein:
- said plurality of input/output circuits are arranged in an array using bump array technology; and
- said power conductors are arranged in banks relative to said array.
11. A method for operating a programmable logic device that programmably accommodates a plurality of logic signalling standards having differing power requirements, said programmable logic device comprising:
- programmable logic elements,
- an interconnect structure connecting said programmable logic elements,
- a plurality of input/output terminals,
- a plurality of input/output circuits connected to said interconnect structure and to said input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic elements, and
- a plurality of power bus conductors; said method comprising:
- when one of said plurality of input/output circuits is operated in accordance with one of said plurality of logic signalling standards, providing, through a respective power bus conductor, power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.
12. The method of claim 11 wherein, when each of said power bus conductors is spatially disposed adjacent a respective subset of said plurality of input/output circuits, and circuits in each respective subset of said plurality of input/output circuits are operated in accordance with one of said plurality of logic signalling standards, said method further comprises providing, through a respective power bus conductor, power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.
13. The method of claim 12 wherein at least two of said power conductors are disposed adjacent each said respective subset, said method further comprising, when circuits in said respective subset are operated in accordance with a logic signalling standard requiring a reference voltage, providing supply voltage through one of said at least two power conductors, and providing said reference voltage through another one of said at least two power conductors.
14. A digital processing system comprising:
- processing circuitry;
- a system memory coupled to said processing circuitry; and
- a programmable logic device as defined in claim 6 coupled to the processing circuitry and the system memory.
15. A printed circuit board on which is mounted a programmable logic device as defined in claim 6.
16. The printed circuit board defined in claim 15 further comprising:
- a board memory mounted on the printed circuit board and coupled to the programmable logic device.
17. The printed circuit board defined in claim 16 further comprising:
- processing circuitry mounted on the printed circuit board and coupled to the board memory.
18. An integrated circuit comprising:
- an integrated circuit programmable logic device that programmably accommodates a plurality of logic signalling standards having differing power requirements, said integrated circuit programmable logic device comprising:
- programmable logic elements;
- an interconnect structure connecting said programmable logic elements;
- a plurality of input/output terminals;
- a plurality of input/output circuits connected to said interconnect structure and to said input/output terminals, each of said input/output circuits programmably accommodating at least some of said plurality of logic signalling standards and being coupled to a respective one of said input/output terminals for buffering input/output signals between said respective one of said input/output terminals and said programmable logic elements; and
- a plurality of power bus conductors, each of said power bus conductors being spatially disposed adjacent a respective subset of said plurality of input/output circuits; wherein:
- when circuits in each respective subset of said plurality of input/output circuits are operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor adjacent each respective subset provides power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.
19. The integrated circuit of claim 18 wherein:
- each of said power bus conductors is spatially disposed adjacent a respective subset of said plurality of input/output circuits; and
- when circuits in each respective subset of said plurality of input/output circuits are operated in accordance with one of said plurality of logic signalling standards, a respective power bus conductor adjacent each respective subset provides power compatible with power requirements of said one of said standards in accordance with which circuits in said respective subset are operated.
20. The integrated circuit of claim 19 wherein at least two of said power conductors are disposed adjacent each said respective subset, whereby when circuits in said respective subset are operated in accordance with a logic signalling standard requiring a reference voltage, one of said at least two power conductors provides supply voltage and one of said at least two power conductors provides said reference voltage.
21. The integrated circuit of claim 19 wherein:
- said plurality of input/output circuits are arranged substantially adjacent one or more edges of said programmable logic device; and
- said power conductors are arranged parallel to said one or more edges.
22. The integrated circuit of claim 19 wherein:
- said plurality of input/output circuits are arranged in an array using bump array technology; and
- said power conductors are arranged in banks relative to said array.
23. A digital processing system comprising:
- processing circuitry;
- a system memory coupled to said processing circuitry; and
- an integrated circuit as defined in claim 18 coupled to the processing circuitry and the system memory.
24. A printed circuit board on which is mounted an integrated circuit as defined in claim 18.
25. The printed circuit board defined in claim 24 further comprising:
- a board memory mounted on the printed circuit board and coupled to the integrated circuit.
26. The printed circuit board defined in claim 25 further comprising:
- processing circuitry mounted on the printed circuit board and coupled to the board memory.
