US6314501B1 - Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory - Google Patents
Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory Download PDFInfo
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- US6314501B1 US6314501B1 US09/215,424 US21542498A US6314501B1 US 6314501 B1 US6314501 B1 US 6314501B1 US 21542498 A US21542498 A US 21542498A US 6314501 B1 US6314501 B1 US 6314501B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
Abstract
Description
TABLE A |
The Configuration Register Values for the |
Window Mapping Shown in Figure 5. |
Shared | |||||
Relocation | Reclamation | Shared BaseOS | BaseMSU | ||
RL OS | RC OS | SBASE OS | SBASEMSU | ||
OSOS | 0.0000.0000H | 0.0000.0000H | 1.4000.0000H | 4.5000.0000H |
#1 | (0 GB) | (0 GB) | (5.000 GB) | (17.250 GB) |
OSOS | 1.4000.0000H | 0.1000.0000H | 1.7000.0000H | 4.5000.0000H |
#2 | (5.000 GB) | (0.250 GB) | (5.750 GB) | (17.250 GB) |
OSOS | 2.A000.0000H | 0.0800.0000H | 1.B800.0000H | 4.5000.0000H |
#3 | (10.500 GB) | (0.125 GB) | (6.87 GB) | (17.250 GB) |
TABLE B |
if OSADR OS ε RANGESHAREDMEMORY |
then MSUADR → OSADR OS + [SBASE MSU − SBASE OS]; |
else if OSADR OS ε RANGEHIGHMEMORY |
then MSUADR → OSADR OS + [RL OS − RC OS]; |
else /* OSADR OS ε RANGELOWMEMORY */ |
MSUADR → OSADR OS + [RL OS]; |
endif; |
TABLE C | |||
Between | MSU_Pair0 | MSU_Pair1 | |
MSU_Pair0 & | Between | Between | |
Option | MSU_Pair1 | MSU0 & MSU1 | MSU2 & MSU3 |
ISS | Interleaved | Stacked | Stacked |
ISI | Interleaved | Stacked | Interleaved |
IIS | Interleaved | Interleaved | Stacked |
III | Interleaved | Interleaved | Interleaved |
SSS | Stacked | Stacked | Stacked |
SSI | Stacked | Stacked | Interleaved |
SIS | Stacked | Interleaved | Stacked |
SII | Stacked | Interleaved | Interleaved |
TABLE D | ||
Bits | Function | Default Value |
[15] | Address Translation Enable | 0 (Default) |
[14] | Memory Address Space Reclamation Enable | 0 |
[13] | PAIR_MODE | 0 |
[12] | PAIR_SEL | 0 |
[11:10] | Reserved | 00 |
[9.0] | Smallest_Pair_Size[9:0] | 000H (Default) |
TABLE E | ||
Bits | Function | Default Value |
[15] | |
0 (Default) |
[14] | Reserved | 0 |
[13] | Pair0_Mode | 0 |
[12] | Pair0_Sel | 0 |
[11:10] | Reserved | 00 |
[9:0] | Pair0_Smallest_MSU_Size[9:0] | 000H (Default) |
TABLE F | ||
Bits | Function | Default Value |
[15] | |
0 (Default) |
[14] | Reserved | 0 |
[13] | Pair1_Mode | 0 |
[12] | Pair1_Sel | 0 |
[11:10] | Reserved | 00 |
[9:0] | Pair1_Smallest_MSU_Size[9:0] | 000H (Default) |
TABLE G | |
Name | Definition |
MSU_Pair0/Pair1 Configuration Registers: |
used to control accesses to a specific MSU_Pair |
PAIR_MODE | This 1 bit register controls whether address |
interleaving between MSU_PAIRs is selected. Address | |
interleaving should only be enabled when both | |
MSU_PAIRs are present. | |
When | |
= 0 then Interleave between MSU_PAIRs | |
= 1 then Stack between MSU_PAIRs (Pair0 first, | |
overflow into Pair1) | |
SMALLEST— | This register1 holds one of two memory size values2 |
PAIR_SZ | depending on whether address interleaving between |
MSU_PAIRs is enabled. | |
if PAIR_MODE = 0 (interleaving then) | |
= the smaller of the two memory size values between | |
MSU_Pair0 ( |
|
( |
|
else PAIR_MODE = 1 (stacking) | |
= the memory size of the MSU pairs selected by the | |
PAIR_SEL register | |
PAIR_SEL | This 1 bit register specifies which one of the two |
MSU_PAIRs is to be addressed first. The value | |
depending on whether address interleaving is being | |
performed. For interleaving, the MSU_Pair with the | |
largest installed memory must be selected. For stacking, | |
either MSU_Pair can be selected. | |
if PAIR_MODE = 0 (interleaving) then | |
= 0 if pair0 has more storage then pair1 | |
= if 1 if pair1 has more storage then pair0 | |
else PAIR_MODE = 1 (stacking) | |
= Pair which gets the memory “address0” | |
(0 - Pair0; 1 - Pair1) |
MSU_Pair0 Configuration Registers: |
used to control accesses to a specific MSU within pair0 |
PAIR0_MODE | This 1 bid register controls whether address interleaving |
between MSUs within an MSU_Pair is selected. | |
Address interleaving should only be enabled when both | |
MSUs are present in MSU_Pair0. | |
= 0 Interleave between MSUs of pair0 ( |
|
and MSU #1) | |
= 1 Stack the MSUs of pair0 | |
PAIR0— | This register1 holds one of two memory size2 |
SMALLEST— | values depending on whether address interleaving within |
MSU_SZ | this MSU_Pair is enabled. |
= the smaller of the two memory size values | |
between |
|
else (PAIR0_MODE0 = 1:stacking) | |
= the memory size of the MSU selected by the | |
PAIR0_SEL register | |
PAIR0_SEL | This 1 bid register specifies one of the two MSUs within |
a MSU_Pair is to be addressed first. The value | |
depending on whether address interleaving is being | |
performed. For interleaving, the MSU with the largest | |
installed memory must be selected. For stacking, | |
either MSU can be selected. | |
if PAIR0_MODE = 0 (interleaving) then | |
= 0 if |
|
|
|
= 1 if |
|
|
|
else PAIR0_MODE = 1 (stacking) | |
= MSU of pair0 which gets the memory “ |
|
(0 - |
MSU_Pair1 Configuration Registers: |
used to control access to a specific MSU within pair1 |
PAIR1_MODE | This 1 bit register controls whether address interleaving |
between MSUs within an MSU_Pair is selected. | |
Address interleaving should only be enabled when both | |
MSUs are present in MSU_Pair1. | |
When | |
= 0 Interleave between MSUs of paif1 | |
( |
|
= 1 then Stack the MSUs of |
|
PAIR1— | This register1 holds one of two memory size values2 |
SMALLEST— | depending on whether address interleaving within this |
MSU_SZ | MSU_Pair is enabled. |
if PAIR1_MODE = 0 (interleaving) then | |
= the smaller of the two memory size values between | |
|
|
else PAIR1_MODE = 1 (stacking) | |
= the memory size of the MSU selected by the | |
PAIR1_SEL register | |
PAIR1_SEL | This 1 bit register specifies one of the two MSUs within |
a MSU_Pair is to be addressed first. The value | |
depending on whether address interleaving is being | |
performed. For interleaving, the MSU with the largest | |
installed memory must be selected. For stacking, | |
either MSU can be selected. | |
if PAIR1_MODE = 0 (interleaving) then | |
= 0 if |
|
|
|
= 1 if |
|
|
|
else PAIR1_MODE = 1 (stacking) | |
= MSU of pair1 which gets the memory “ |
|
(0 - |
|
1Note: The size of this register is not specified in this table. It is implementation specific, and is not necessary for the understanding of the translation algorithm. | |
2Note: The memory size is equal to the maximum |
Initialization for both.phases: | |
PROCESSOR_ADDR[35:0] = | 000000000H |
TEMP_ADDR[29:0] = | 00000000H |
TOP_OF_INTRLV_RANGE = | 003H |
PAIR0_TOP_OF_INTLV_RANGE= | 002H |
PAIR1_TOP_OF_INTLV_RANGE= | 004H |
the MSU_Pair selection phase: |
In |
TEMP_ADDR[29:0] = | 00000000H |
Results: |
RCVING_MSU = | 0 (MSU PAIR0) |
TEMP_ADDR[29:0] = | 00000000H |
the MSU# selection phase: |
In |
TEMP_ADDR[29:0] = | 00000000H |
Results: |
RCVING_MSU = | 0 (MSU#0) |
TEMP_ADDR[29:0] = | 00000000H |
the final results: |
MSU_ADDR[29:0] = | 000000000H |
MSU_SEL[1 :0] = | 00 (MSU#0 of MSU_PAIR0) |
Processing the second address |
Initialization: |
PROCESSOR_ADDR[35: | 000000040H |
0] = | |
TEMP_ADDR[29:0] = | 00000001H |
RCVING_PAIR = | 1 (MSU_PAIR1) |
TEMP_ADDR[29:0] = | 00000000H |
RCVING_MSU = | 0 (MSU#2) |
TEMP_ADDR[29:0] = | 00000000H |
the final results: |
MSU_ADDR[29:0] = | 00000000H |
MSU_SEL[1:0] = | 10 (MSU#2 OF |
MSU_PAIR1) |
The third address yields: |
Initialization: |
PROCESSOR_ADDR[35: | 000000080H |
0] = | |
TEMP_ADDR[29:0] = | 00000002H |
RVCING_PAIR = | 1(MSU_PAIR1) |
TEMP_ADDR[29:0] = | 00000001H |
RCVING_MSU = | 0 (MSU#2) |
TEMP ADDR[29:0] = | 00000000H |
Final results: |
MSU_ADDR[29:0] = | 00000000H |
MSU_SEL[1:0] = | 01(MSU#1 OF |
MSU_PAIR0) |
While the fourth address yields the final results: |
Initialization: |
PROCESSOR_ADDR[35: | 0000000C0H |
0]= | |
TEMP_ADDR[29:0] = | 00000003H |
RVCING_PAIR = | 1 (MSU_PAIR1) |
TEMP_ADDR[29:0] = | 00000001H |
RCVING_MSU = | 0 (MSU#2) |
TEMP_ADDR[29:0] = | 00000000H |
Final results: |
MSU_ADDR[29:0] = | 00000000H |
MSU_SEL[1:0] = | 01(MSU#2 OF |
MSU_PAIR1) | |
Claims (30)
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/215,424 US6314501B1 (en) | 1998-07-23 | 1998-12-18 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
JP2000588687A JP2002532806A (en) | 1998-12-18 | 1999-12-17 | Computer system and method for operating multiple operating systems in different partitions of a computer system so that different partitions can communicate with each other via shared memory |
PCT/US1999/030437 WO2000036509A2 (en) | 1998-12-18 | 1999-12-17 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
CA002355065A CA2355065C (en) | 1998-12-18 | 1999-12-17 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
BR9916308-0A BR9916308A (en) | 1998-12-18 | 1999-12-17 | Computer system and method to operate multiple operating systems on different partitions of the computer system and to allow different partitions to communicate with each other through shared memory |
DE69935805T DE69935805T2 (en) | 1998-12-18 | 1999-12-17 | COMPUTER SYSTEM AND METHOD FOR OPERATING SEVERAL OPERATING SYSTEMS IN VARIOUS PARTITIONS OF THE COMPUTER SYSTEM AND FOR ALLOWING THE DIFFERENT PARTITIONS TO COMMUNICATE TOGETHER THROUGH JOINT STORES |
AT99964305T ATE359550T1 (en) | 1998-12-18 | 1999-12-17 | COMPUTER SYSTEM AND METHOD FOR OPERATING MULTIPLE OPERATING SYSTEMS IN DIFFERENT PARTITIONS OF THE COMPUTER SYSTEM AND FOR ALLOWING THE DIFFERENT PARTITIONS TO COMMUNICATE WITH EACH OTHER THROUGH COMMON MEMORY |
EP99964305A EP1145122B1 (en) | 1998-12-18 | 1999-12-17 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
US09/923,175 US7571440B2 (en) | 1998-07-23 | 2001-08-06 | System and method for emulating network communications between partitions of a computer system |
JP2006049063A JP2006216068A (en) | 1998-12-18 | 2006-02-24 | Computer system for actuating two or more operating systems in different partitions on computer system to communicate different partitions with each other via common memory, and its method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12079798A | 1998-07-23 | 1998-07-23 | |
US09/215,424 US6314501B1 (en) | 1998-07-23 | 1998-12-18 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12079798A Continuation-In-Part | 1998-07-23 | 1998-07-23 | |
US09/215,424 Continuation-In-Part US6314501B1 (en) | 1998-07-23 | 1998-12-18 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/215,424 Continuation-In-Part US6314501B1 (en) | 1998-07-23 | 1998-12-18 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
US09/923,175 Division US7571440B2 (en) | 1998-07-23 | 2001-08-06 | System and method for emulating network communications between partitions of a computer system |
Publications (1)
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US6314501B1 true US6314501B1 (en) | 2001-11-06 |
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Application Number | Title | Priority Date | Filing Date |
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US09/215,424 Expired - Lifetime US6314501B1 (en) | 1998-07-23 | 1998-12-18 | Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory |
US09/923,175 Expired - Fee Related US7571440B2 (en) | 1998-07-23 | 2001-08-06 | System and method for emulating network communications between partitions of a computer system |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US09/923,175 Expired - Fee Related US7571440B2 (en) | 1998-07-23 | 2001-08-06 | System and method for emulating network communications between partitions of a computer system |
Country Status (8)
Country | Link |
---|---|
US (2) | US6314501B1 (en) |
EP (1) | EP1145122B1 (en) |
JP (2) | JP2002532806A (en) |
AT (1) | ATE359550T1 (en) |
BR (1) | BR9916308A (en) |
CA (1) | CA2355065C (en) |
DE (1) | DE69935805T2 (en) |
WO (1) | WO2000036509A2 (en) |
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WO2000036509A2 (en) | 2000-06-22 |
WO2000036509A3 (en) | 2001-04-19 |
BR9916308A (en) | 2001-12-11 |
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DE69935805T2 (en) | 2007-12-27 |
EP1145122B1 (en) | 2007-04-11 |
JP2006216068A (en) | 2006-08-17 |
US7571440B2 (en) | 2009-08-04 |
EP1145122A2 (en) | 2001-10-17 |
DE69935805D1 (en) | 2007-05-24 |
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JP2002532806A (en) | 2002-10-02 |
US20030037178A1 (en) | 2003-02-20 |
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