US6353265B1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US6353265B1 US6353265B1 US09/877,038 US87703801A US6353265B1 US 6353265 B1 US6353265 B1 US 6353265B1 US 87703801 A US87703801 A US 87703801A US 6353265 B1 US6353265 B1 US 6353265B1
- Authority
- US
- United States
- Prior art keywords
- semiconductor chip
- die pad
- pads
- stacked
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 388
- 238000007789 sealing Methods 0.000 claims abstract description 108
- 239000011347 resin Substances 0.000 claims abstract description 87
- 229920005989 resin Polymers 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000003566 sealing material Substances 0.000 claims abstract description 4
- 230000002093 peripheral effect Effects 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 34
- 239000010931 gold Substances 0.000 description 34
- 229910052737 gold Inorganic materials 0.000 description 34
- 238000000034 method Methods 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 16
- 238000004806 packaging method and process Methods 0.000 description 10
- 238000009751 slip forming Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 241000272168 Laridae Species 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85191—Translational movements connecting first both on and outside the semiconductor or solid-state body, i.e. regular and reverse stitches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001029342A JP2002231882A (en) | 2001-02-06 | 2001-02-06 | Semiconductor device |
JP2001-029342 | 2001-02-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
US6353265B1 true US6353265B1 (en) | 2002-03-05 |
Family
ID=18893701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/877,038 Expired - Lifetime US6353265B1 (en) | 2001-02-06 | 2001-06-11 | Semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (1) | US6353265B1 (en) |
JP (1) | JP2002231882A (en) |
KR (1) | KR100445502B1 (en) |
CN (1) | CN1197156C (en) |
DE (1) | DE10136283A1 (en) |
TW (1) | TW499722B (en) |
Cited By (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010055838A1 (en) * | 2000-04-28 | 2001-12-27 | Matrix Semiconductor Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
US20020028541A1 (en) * | 2000-08-14 | 2002-03-07 | Lee Thomas H. | Dense arrays and charge storage devices, and methods for making same |
US20020116668A1 (en) * | 2001-02-20 | 2002-08-22 | Matrix Semiconductor, Inc. | Memory card with enhanced testability and methods of making and using the same |
US6483736B2 (en) * | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6509637B1 (en) * | 2002-03-08 | 2003-01-21 | Amkor Technology, Inc. | Low profile mounting of thick integrated circuit packages within low-profile circuit modules |
US6525953B1 (en) | 2001-08-13 | 2003-02-25 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
US20030058629A1 (en) * | 2001-09-25 | 2003-03-27 | Taro Hirai | Wiring substrate for small electronic component and manufacturing method |
US6583511B2 (en) * | 2001-05-17 | 2003-06-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of producing the same |
US6593624B2 (en) | 2001-09-25 | 2003-07-15 | Matrix Semiconductor, Inc. | Thin film transistors with vertically offset drain regions |
US6624485B2 (en) | 2001-11-05 | 2003-09-23 | Matrix Semiconductor, Inc. | Three-dimensional, mask-programmed read only memory |
US20030218241A1 (en) * | 2002-05-22 | 2003-11-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6731011B2 (en) | 2002-02-19 | 2004-05-04 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
US6737675B2 (en) | 2002-06-27 | 2004-05-18 | Matrix Semiconductor, Inc. | High density 3D rail stack arrays |
US6774659B1 (en) * | 2002-01-09 | 2004-08-10 | Bridge Semiconductor Corporation | Method of testing a semiconductor package device |
US20040207001A1 (en) * | 2001-03-28 | 2004-10-21 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
US6843421B2 (en) | 2001-08-13 | 2005-01-18 | Matrix Semiconductor, Inc. | Molded memory module and method of making the module absent a substrate support |
US6858922B2 (en) * | 2001-01-19 | 2005-02-22 | International Rectifier Corporation | Back-to-back connected power semiconductor device package |
US20050067694A1 (en) * | 2003-09-30 | 2005-03-31 | Pon Florence R. | Spacerless die stacking |
US20050070060A1 (en) * | 2001-08-13 | 2005-03-31 | Matrix Semiconductor, Inc. | TFT mask ROM and method for making same |
US20050104170A1 (en) * | 2003-11-17 | 2005-05-19 | Akio Nakamura | Semiconductor device and manufacturing method thereof |
US20050110127A1 (en) * | 2003-11-20 | 2005-05-26 | Renesas Technology Corp. | Semiconductor device |
US20050112804A1 (en) * | 2002-03-13 | 2005-05-26 | Matrix Semiconductor, Inc. | Silicide-silicon oxide-semiconductor antifuse device and method of making |
US6919620B1 (en) * | 2002-09-17 | 2005-07-19 | Amkor Technology, Inc. | Compact flash memory card with clamshell leadframe |
US6933223B1 (en) | 2004-04-15 | 2005-08-23 | National Semiconductor Corporation | Ultra-low loop wire bonding |
US6936495B1 (en) | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
US20050212106A1 (en) * | 2004-03-24 | 2005-09-29 | Youngwoo Kwon | Multilayer integrated circuit for RF communication and method for assembly thereof |
US6987034B1 (en) | 2002-01-09 | 2006-01-17 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes singulating and trimming a lead |
US20060027901A1 (en) * | 2004-08-09 | 2006-02-09 | Ming-Sung Tsai | Stacked chip package with exposed lead-frame bottom surface |
US7190060B1 (en) | 2002-01-09 | 2007-03-13 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same |
US7199469B2 (en) * | 2000-10-16 | 2007-04-03 | Renesas Technology Corp. | Semiconductor device having stacked semiconductor chips sealed with a resin seal member |
US20070108604A1 (en) * | 2005-02-10 | 2007-05-17 | Stats Chippac Ltd. | Stacked integrated circuit leadframe package system |
US20080017955A1 (en) * | 2006-07-21 | 2008-01-24 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die |
US20080036052A1 (en) * | 2006-08-09 | 2008-02-14 | Stats Chippac Ltd. | Integrated circuit package system with supported stacked die |
US20080049483A1 (en) * | 2006-07-31 | 2008-02-28 | Mitsumi Electric Co., Ltd. | Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage |
US20080073763A1 (en) * | 2006-09-27 | 2008-03-27 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20080099892A1 (en) * | 2006-10-26 | 2008-05-01 | Chipmos Technologies Inc. | Stacked chip packaging with heat sink structure |
US20080136005A1 (en) * | 2006-12-09 | 2008-06-12 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US20080136006A1 (en) * | 2006-12-09 | 2008-06-12 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US20080136007A1 (en) * | 2006-12-09 | 2008-06-12 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US20080174000A1 (en) * | 2007-01-19 | 2008-07-24 | Yu-Ren Chen | Zigzag-stacked package structure |
CN100411170C (en) * | 2005-05-30 | 2008-08-13 | 矽品精密工业股份有限公司 | Stack architecture of multiple chips |
US20080315408A1 (en) * | 2007-06-20 | 2008-12-25 | Samsung Electronics Co., Ltd. | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same |
WO2009046030A1 (en) * | 2007-10-03 | 2009-04-09 | Micron Technology, Inc. | Stackable integrated circuit package |
US20090161402A1 (en) * | 2007-12-20 | 2009-06-25 | Hakjune Oh | Data storage and stackable configurations |
US20100039847A1 (en) * | 2006-07-31 | 2010-02-18 | Mitsumi Electric Co. Ltd. | Method of manufacturing a single chip semiconductor integrated circuit device including a mask rom in a short time |
US20100117217A1 (en) * | 2007-06-20 | 2010-05-13 | Chul Park | Semiconductor package |
US20110037158A1 (en) * | 2008-05-21 | 2011-02-17 | Sunpil Youn | Ball-grid-array package, electronic system and method of manufacture |
US8575719B2 (en) | 2000-04-28 | 2013-11-05 | Sandisk 3D Llc | Silicon nitride antifuse for use in diode-antifuse memory arrays |
US9478495B1 (en) | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
US9627395B2 (en) | 2015-02-11 | 2017-04-18 | Sandisk Technologies Llc | Enhanced channel mobility three-dimensional memory structure and method of making thereof |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10243981B4 (en) * | 2002-09-20 | 2015-06-03 | Robert Bosch Gmbh | Electronic assembly, in particular regulator for generators in motor vehicles |
JP3941953B2 (en) * | 2003-12-03 | 2007-07-11 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
JP2006278913A (en) * | 2005-03-30 | 2006-10-12 | Toyota Motor Corp | Circuit device and manufacturing method therefor |
JP4674113B2 (en) * | 2005-05-06 | 2011-04-20 | Okiセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
JP2007129182A (en) | 2005-05-11 | 2007-05-24 | Toshiba Corp | Semiconductor device |
JP4835449B2 (en) * | 2007-01-29 | 2011-12-14 | 株式会社デンソー | Semiconductor device |
JP5183186B2 (en) * | 2007-12-14 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2009252815A (en) * | 2008-04-02 | 2009-10-29 | Toppan Printing Co Ltd | Composite lead frame structure and semiconductor device |
KR101909203B1 (en) | 2011-07-21 | 2018-10-17 | 삼성전자 주식회사 | Multi-channel package and electronic system comprising the same package |
CN108155158A (en) * | 2017-12-22 | 2018-06-12 | 中国电子科技集团公司第四十七研究所 | The 3D encapsulating structures of mass storage circuit |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302164A (en) | 1991-03-29 | 1992-10-26 | Fujitsu Ltd | Semiconductor device |
JPH10256469A (en) | 1997-03-10 | 1998-09-25 | Sanyo Electric Co Ltd | Semiconductor device |
JP2000156464A (en) | 1998-11-20 | 2000-06-06 | Hitachi Ltd | Manufacture of semiconductor device |
US6087722A (en) * | 1998-05-28 | 2000-07-11 | Samsung Electronics Co., Ltd. | Multi-chip package |
US6118184A (en) * | 1997-07-18 | 2000-09-12 | Sharp Kabushiki Kaisha | Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow |
US6265760B1 (en) * | 1998-05-01 | 2001-07-24 | Nec Corporation | Semiconductor device, and semiconductor device with die pad and protruding chip lead frame and method of manufacturing the same |
-
2001
- 2001-02-06 JP JP2001029342A patent/JP2002231882A/en not_active Withdrawn
- 2001-06-11 US US09/877,038 patent/US6353265B1/en not_active Expired - Lifetime
- 2001-07-25 DE DE2001136283 patent/DE10136283A1/en not_active Ceased
- 2001-09-03 TW TW90121747A patent/TW499722B/en not_active IP Right Cessation
- 2001-10-17 KR KR10-2001-0063891A patent/KR100445502B1/en not_active IP Right Cessation
- 2001-10-17 CN CNB011357762A patent/CN1197156C/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04302164A (en) | 1991-03-29 | 1992-10-26 | Fujitsu Ltd | Semiconductor device |
JPH10256469A (en) | 1997-03-10 | 1998-09-25 | Sanyo Electric Co Ltd | Semiconductor device |
US6118184A (en) * | 1997-07-18 | 2000-09-12 | Sharp Kabushiki Kaisha | Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow |
US6265760B1 (en) * | 1998-05-01 | 2001-07-24 | Nec Corporation | Semiconductor device, and semiconductor device with die pad and protruding chip lead frame and method of manufacturing the same |
US6087722A (en) * | 1998-05-28 | 2000-07-11 | Samsung Electronics Co., Ltd. | Multi-chip package |
JP2000156464A (en) | 1998-11-20 | 2000-06-06 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (125)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050063220A1 (en) * | 1998-11-16 | 2005-03-24 | Johnson Mark G. | Memory device and method for simultaneously programming and/or reading memory cells on different levels |
US20060134837A1 (en) * | 1998-11-16 | 2006-06-22 | Vivek Subramanian | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US20100171152A1 (en) * | 1998-11-16 | 2010-07-08 | Johnson Mark G | Integrated circuit incorporating decoders disposed beneath memory arrays |
US6483736B2 (en) * | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US7816189B2 (en) | 1998-11-16 | 2010-10-19 | Sandisk 3D Llc | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US20030016553A1 (en) * | 1998-11-16 | 2003-01-23 | Vivek Subramanian | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US20060141679A1 (en) * | 1998-11-16 | 2006-06-29 | Vivek Subramanian | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US20110019467A1 (en) * | 1998-11-16 | 2011-01-27 | Johnson Mark G | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US8208282B2 (en) | 1998-11-16 | 2012-06-26 | Sandisk 3D Llc | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US7978492B2 (en) | 1998-11-16 | 2011-07-12 | Sandisk 3D Llc | Integrated circuit incorporating decoders disposed beneath memory arrays |
US6780711B2 (en) | 1998-11-16 | 2004-08-24 | Matrix Semiconductor, Inc | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US8503215B2 (en) | 1998-11-16 | 2013-08-06 | Sandisk 3D Llc | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US8897056B2 (en) | 1998-11-16 | 2014-11-25 | Sandisk 3D Llc | Pillar-shaped nonvolatile memory and method of fabrication |
US9214243B2 (en) | 1998-11-16 | 2015-12-15 | Sandisk 3D Llc | Three-dimensional nonvolatile memory and method of fabrication |
US20010055838A1 (en) * | 2000-04-28 | 2001-12-27 | Matrix Semiconductor Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
US8575719B2 (en) | 2000-04-28 | 2013-11-05 | Sandisk 3D Llc | Silicon nitride antifuse for use in diode-antifuse memory arrays |
US8853765B2 (en) | 2000-08-14 | 2014-10-07 | Sandisk 3D Llc | Dense arrays and charge storage devices |
US8981457B2 (en) | 2000-08-14 | 2015-03-17 | Sandisk 3D Llc | Dense arrays and charge storage devices |
US9171857B2 (en) | 2000-08-14 | 2015-10-27 | Sandisk 3D Llc | Dense arrays and charge storage devices |
US8823076B2 (en) | 2000-08-14 | 2014-09-02 | Sandisk 3D Llc | Dense arrays and charge storage devices |
US20040214379A1 (en) * | 2000-08-14 | 2004-10-28 | Matrix Semiconductor, Inc. | Rail stack array of charge storage devices and method of making same |
US9559110B2 (en) | 2000-08-14 | 2017-01-31 | Sandisk Technologies Llc | Dense arrays and charge storage devices |
US10008511B2 (en) | 2000-08-14 | 2018-06-26 | Sandisk Technologies Llc | Dense arrays and charge storage devices |
US7825455B2 (en) | 2000-08-14 | 2010-11-02 | Sandisk 3D Llc | Three terminal nonvolatile memory device with vertical gated diode |
US10644021B2 (en) | 2000-08-14 | 2020-05-05 | Sandisk Technologies Llc | Dense arrays and charge storage devices |
US20070029607A1 (en) * | 2000-08-14 | 2007-02-08 | Sandisk 3D Llc | Dense arrays and charge storage devices |
US20020028541A1 (en) * | 2000-08-14 | 2002-03-07 | Lee Thomas H. | Dense arrays and charge storage devices, and methods for making same |
US7199469B2 (en) * | 2000-10-16 | 2007-04-03 | Renesas Technology Corp. | Semiconductor device having stacked semiconductor chips sealed with a resin seal member |
US6858922B2 (en) * | 2001-01-19 | 2005-02-22 | International Rectifier Corporation | Back-to-back connected power semiconductor device package |
US20020116668A1 (en) * | 2001-02-20 | 2002-08-22 | Matrix Semiconductor, Inc. | Memory card with enhanced testability and methods of making and using the same |
US7352199B2 (en) | 2001-02-20 | 2008-04-01 | Sandisk Corporation | Memory card with enhanced testability and methods of making and using the same |
US20040207001A1 (en) * | 2001-03-28 | 2004-10-21 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
US6583511B2 (en) * | 2001-05-17 | 2003-06-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of producing the same |
US20060249735A1 (en) * | 2001-08-13 | 2006-11-09 | Sandisk Corporation | TFT mask ROM and method for making same |
US6525953B1 (en) | 2001-08-13 | 2003-02-25 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
US6689644B2 (en) | 2001-08-13 | 2004-02-10 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
US6843421B2 (en) | 2001-08-13 | 2005-01-18 | Matrix Semiconductor, Inc. | Molded memory module and method of making the module absent a substrate support |
US20050070060A1 (en) * | 2001-08-13 | 2005-03-31 | Matrix Semiconductor, Inc. | TFT mask ROM and method for making same |
US20030058629A1 (en) * | 2001-09-25 | 2003-03-27 | Taro Hirai | Wiring substrate for small electronic component and manufacturing method |
US6593624B2 (en) | 2001-09-25 | 2003-07-15 | Matrix Semiconductor, Inc. | Thin film transistors with vertically offset drain regions |
US6624485B2 (en) | 2001-11-05 | 2003-09-23 | Matrix Semiconductor, Inc. | Three-dimensional, mask-programmed read only memory |
US6803651B1 (en) | 2002-01-09 | 2004-10-12 | Bridge Semiconductor Corporation | Optoelectronic semiconductor package device |
US6989584B1 (en) | 2002-01-09 | 2006-01-24 | Bridge Semiconductor Corporation | Semiconductor package device that includes a conductive trace with a routing line, a terminal and a lead |
US6936495B1 (en) | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
US6774659B1 (en) * | 2002-01-09 | 2004-08-10 | Bridge Semiconductor Corporation | Method of testing a semiconductor package device |
US6908794B1 (en) | 2002-01-09 | 2005-06-21 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes a conductive trace with recessed and non-recessed portions |
US6987034B1 (en) | 2002-01-09 | 2006-01-17 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes singulating and trimming a lead |
US6989295B1 (en) | 2002-01-09 | 2006-01-24 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes an insulative housing with first and second housing portions |
US6891276B1 (en) | 2002-01-09 | 2005-05-10 | Bridge Semiconductor Corporation | Semiconductor package device |
US7190060B1 (en) | 2002-01-09 | 2007-03-13 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same |
US7009309B1 (en) | 2002-01-09 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor package device that includes an insulative housing with a protruding peripheral portion |
US20040169285A1 (en) * | 2002-02-19 | 2004-09-02 | Vani Verma | Memory module having interconnected and stacked integrated circuits |
US7005730B2 (en) * | 2002-02-19 | 2006-02-28 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
US6731011B2 (en) | 2002-02-19 | 2004-05-04 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
US20060118927A1 (en) * | 2002-02-19 | 2006-06-08 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
US6509637B1 (en) * | 2002-03-08 | 2003-01-21 | Amkor Technology, Inc. | Low profile mounting of thick integrated circuit packages within low-profile circuit modules |
US20080009105A1 (en) * | 2002-03-13 | 2008-01-10 | Sandisk 3D Llc | Silicide-silicon oxide-semiconductor antifuse device and method of making |
US7915095B2 (en) | 2002-03-13 | 2011-03-29 | Sandisk 3D Llc | Silicide-silicon oxide-semiconductor antifuse device and method of making |
US7655509B2 (en) | 2002-03-13 | 2010-02-02 | Sandisk 3D Llc | Silicide-silicon oxide-semiconductor antifuse device and method of making |
US20050112804A1 (en) * | 2002-03-13 | 2005-05-26 | Matrix Semiconductor, Inc. | Silicide-silicon oxide-semiconductor antifuse device and method of making |
US20030218241A1 (en) * | 2002-05-22 | 2003-11-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US7145223B2 (en) * | 2002-05-22 | 2006-12-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6737675B2 (en) | 2002-06-27 | 2004-05-18 | Matrix Semiconductor, Inc. | High density 3D rail stack arrays |
US6919620B1 (en) * | 2002-09-17 | 2005-07-19 | Amkor Technology, Inc. | Compact flash memory card with clamshell leadframe |
US20050067694A1 (en) * | 2003-09-30 | 2005-03-31 | Pon Florence R. | Spacerless die stacking |
US20050104170A1 (en) * | 2003-11-17 | 2005-05-19 | Akio Nakamura | Semiconductor device and manufacturing method thereof |
US20080179723A1 (en) * | 2003-11-17 | 2008-07-31 | Oki Electric Industry Co., Ltd. | Semiconductor device including a plural chips with protruding edges laminated on a die pad section that has a through section |
US20050110127A1 (en) * | 2003-11-20 | 2005-05-26 | Renesas Technology Corp. | Semiconductor device |
US20070170583A1 (en) * | 2004-03-24 | 2007-07-26 | Youngwoo Kwon | Multilayer integrated circuit for RF communication and method for assembly thereof |
US20050212106A1 (en) * | 2004-03-24 | 2005-09-29 | Youngwoo Kwon | Multilayer integrated circuit for RF communication and method for assembly thereof |
US20050212078A1 (en) * | 2004-03-24 | 2005-09-29 | Youngwoo Kwon | Integrated circuit module package and assembly method thereof |
US7132747B2 (en) * | 2004-03-24 | 2006-11-07 | Youngwoo Kwon | Multilayer integrated circuit for RF communication and method for assembly thereof |
US8067824B2 (en) * | 2004-03-24 | 2011-11-29 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Integrated circuit module package and assembly method thereof |
US7638364B2 (en) | 2004-03-24 | 2009-12-29 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Multilayer integrated circuit for RF communication and method for assembly thereof |
US6933223B1 (en) | 2004-04-15 | 2005-08-23 | National Semiconductor Corporation | Ultra-low loop wire bonding |
US20060027901A1 (en) * | 2004-08-09 | 2006-02-09 | Ming-Sung Tsai | Stacked chip package with exposed lead-frame bottom surface |
US7679169B2 (en) | 2005-02-10 | 2010-03-16 | Stats Chippac Ltd. | Stacked integrated circuit leadframe package system |
US20070108604A1 (en) * | 2005-02-10 | 2007-05-17 | Stats Chippac Ltd. | Stacked integrated circuit leadframe package system |
US7446396B2 (en) * | 2005-02-10 | 2008-11-04 | Stats Chippac Ltd. | Stacked integrated circuit leadframe package system |
US20090026597A1 (en) * | 2005-02-10 | 2009-01-29 | Choong Bin Yim | Stacked integrated circuit leadframe package system |
CN100411170C (en) * | 2005-05-30 | 2008-08-13 | 矽品精密工业股份有限公司 | Stack architecture of multiple chips |
US20100193926A1 (en) * | 2006-07-21 | 2010-08-05 | Byung Tai Do | Integrated circuit package system with offset stacked die |
US20080017955A1 (en) * | 2006-07-21 | 2008-01-24 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die |
US8018041B2 (en) | 2006-07-21 | 2011-09-13 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die |
US8759954B2 (en) | 2006-07-21 | 2014-06-24 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die |
US7727816B2 (en) * | 2006-07-21 | 2010-06-01 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die |
US7892865B2 (en) | 2006-07-31 | 2011-02-22 | Mitsumi Electric Co., Ltd. | Method of manufacturing a single chip semiconductor integrated circuit device including a mask ROM in a short time |
US8046599B2 (en) * | 2006-07-31 | 2011-10-25 | Mitsumi Electric Co., Ltd. | Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage |
US20080049483A1 (en) * | 2006-07-31 | 2008-02-28 | Mitsumi Electric Co., Ltd. | Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage |
US20100039847A1 (en) * | 2006-07-31 | 2010-02-18 | Mitsumi Electric Co. Ltd. | Method of manufacturing a single chip semiconductor integrated circuit device including a mask rom in a short time |
US20080036052A1 (en) * | 2006-08-09 | 2008-02-14 | Stats Chippac Ltd. | Integrated circuit package system with supported stacked die |
US7618848B2 (en) | 2006-08-09 | 2009-11-17 | Stats Chippac Ltd. | Integrated circuit package system with supported stacked die |
US7968996B2 (en) | 2006-08-09 | 2011-06-28 | Stats Chippac Ltd. | Integrated circuit package system with supported stacked die |
US20100001391A1 (en) * | 2006-08-09 | 2010-01-07 | Byung Tai Do | Integrated circuit package system with supported stacked die |
US20080073763A1 (en) * | 2006-09-27 | 2008-03-27 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20080099892A1 (en) * | 2006-10-26 | 2008-05-01 | Chipmos Technologies Inc. | Stacked chip packaging with heat sink structure |
US7663246B2 (en) * | 2006-10-26 | 2010-02-16 | Chipmos Technologies Inc. | Stacked chip packaging with heat sink structure |
US20080136006A1 (en) * | 2006-12-09 | 2008-06-12 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US8617924B2 (en) * | 2006-12-09 | 2013-12-31 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system and method of manufacture thereof |
US20080136005A1 (en) * | 2006-12-09 | 2008-06-12 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US20080136007A1 (en) * | 2006-12-09 | 2008-06-12 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US8729687B2 (en) | 2006-12-09 | 2014-05-20 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US8304874B2 (en) * | 2006-12-09 | 2012-11-06 | Stats Chippac Ltd. | Stackable integrated circuit package system |
US20100044849A1 (en) * | 2006-12-09 | 2010-02-25 | Kim Ohsug | Stacked integrated circuit package-in-package system and method of manufacture thereof |
US7635913B2 (en) | 2006-12-09 | 2009-12-22 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US7772683B2 (en) | 2006-12-09 | 2010-08-10 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US20080174000A1 (en) * | 2007-01-19 | 2008-07-24 | Yu-Ren Chen | Zigzag-stacked package structure |
US7781878B2 (en) * | 2007-01-19 | 2010-08-24 | Chipmos Technologies Inc. | Zigzag-stacked package structure |
US20100117217A1 (en) * | 2007-06-20 | 2010-05-13 | Chul Park | Semiconductor package |
US7745932B2 (en) | 2007-06-20 | 2010-06-29 | Samsung Electronics Co., Ltd. | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same |
US20080315408A1 (en) * | 2007-06-20 | 2008-12-25 | Samsung Electronics Co., Ltd. | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same |
US8193626B2 (en) | 2007-06-20 | 2012-06-05 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
US20090091009A1 (en) * | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
WO2009046030A1 (en) * | 2007-10-03 | 2009-04-09 | Micron Technology, Inc. | Stackable integrated circuit package |
US20090161402A1 (en) * | 2007-12-20 | 2009-06-25 | Hakjune Oh | Data storage and stackable configurations |
US9183892B2 (en) | 2007-12-20 | 2015-11-10 | Conversant Intellectual Property Management Inc. | Data storage and stackable chip configurations |
US8399973B2 (en) | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
WO2009079749A1 (en) * | 2007-12-20 | 2009-07-02 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
US9455217B2 (en) | 2008-05-21 | 2016-09-27 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
US9502345B2 (en) | 2008-05-21 | 2016-11-22 | Samsung Electronics Co., Ltd. | Ball-grid-array package, electronic system and method of manufacture |
US20110037158A1 (en) * | 2008-05-21 | 2011-02-17 | Sunpil Youn | Ball-grid-array package, electronic system and method of manufacture |
US8901750B2 (en) | 2009-03-17 | 2014-12-02 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
US8723333B2 (en) | 2009-03-17 | 2014-05-13 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
US9627395B2 (en) | 2015-02-11 | 2017-04-18 | Sandisk Technologies Llc | Enhanced channel mobility three-dimensional memory structure and method of making thereof |
US9478495B1 (en) | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
Also Published As
Publication number | Publication date |
---|---|
KR100445502B1 (en) | 2004-08-21 |
DE10136283A1 (en) | 2002-08-22 |
TW499722B (en) | 2002-08-21 |
KR20020065326A (en) | 2002-08-13 |
CN1197156C (en) | 2005-04-13 |
JP2002231882A (en) | 2002-08-16 |
CN1368760A (en) | 2002-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6353265B1 (en) | Semiconductor device | |
US5409866A (en) | Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe | |
JP2875139B2 (en) | Method for manufacturing semiconductor device | |
KR101160694B1 (en) | Manufacturing Method of Semiconductor Device | |
JP4097403B2 (en) | Semiconductor device | |
JP4969113B2 (en) | Circuit device manufacturing method | |
WO2004004005A1 (en) | Semiconductor device and its manufacturing method | |
JP2002222889A (en) | Semiconductor device and method of manufacturing the same | |
KR20020060558A (en) | Semiconductor device | |
JP3958522B2 (en) | Semiconductor device | |
KR20110079800A (en) | Semiconductor device | |
JP2001077232A (en) | Semiconductor device and manufacture thereof | |
US6893898B2 (en) | Semiconductor device and a method of manufacturing the same | |
JP2004349316A (en) | Semiconductor device and its manufacturing method | |
JP2005150647A (en) | Semiconductor device and method for manufacturing same | |
KR100227120B1 (en) | Semiconductor chip package having combinational structure of lead-on-chip leads and standard normal leads | |
JP2003110080A (en) | Semiconductor device | |
KR20030009627A (en) | Horizontal dual die package | |
JP3468206B2 (en) | Semiconductor device | |
JPH0582672A (en) | Semiconductor device and manufacturing method thereof | |
JP3954586B2 (en) | Semiconductor device | |
JP3954585B2 (en) | Semiconductor device | |
JP4162758B2 (en) | Manufacturing method of semiconductor device | |
JPH0922959A (en) | Semiconductor device and semiconductor device unit | |
JPH04320365A (en) | Plastic sealed semiconductor device and memory card |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICHII, KAZUNARI;REEL/FRAME:011894/0638 Effective date: 20010530 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:025980/0219 Effective date: 20110307 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001 Effective date: 20150806 |