US6393498B1 - System for reducing processor workloads with memory remapping techniques - Google Patents
System for reducing processor workloads with memory remapping techniques Download PDFInfo
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- US6393498B1 US6393498B1 US09/260,637 US26063799A US6393498B1 US 6393498 B1 US6393498 B1 US 6393498B1 US 26063799 A US26063799 A US 26063799A US 6393498 B1 US6393498 B1 US 6393498B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0692—Multiconfiguration, e.g. local and global addressing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
Definitions
- the present invention relates to a data-processing system and method using memory-remapping technique.
- Such invention is designed to reduce the workload of processors, such as central processing units (CPUs) in personal computers, and to serve the data transfer requirement of various peripheral devices.
- processors such as central processing units (CPUs) in personal computers, and to serve the data transfer requirement of various peripheral devices.
- Memory is an infrastructure block in data-processing or computing systems (hereafter is referred to as “the System”). Under normal operation, the System must spend a lot of time to move data from and write data into the memory. Therefore, how to effectively access memory is a critical issue when assessing the System's overall performance.
- FIG. 1 (Prior Art) is a block diagram which illustrates the fundamental structure of the System.
- the System includes processor 1 , system controller 3 , memory 5 and several peripheral devices such as peripheral device 7 and peripheral device 9 .
- Processor 1 is the key component in the System for performing various data-processing operations, such as arithmetic and logical operations, and data transfer operations.
- Memory 5 usually implemented by dynamic random access memories (hereafter referred as DRAMs), is a main storage device for storing major program codes and data.
- Peripheral devices 7 and 9 are used to communicate with the exterior or supplement extra functions to the System.
- System controller 3 which is installed between processor 1 , memory 5 and peripheral devices 7 and 9 , is used to link processor 1 and the peripheral devices.
- system controller 3 provides an accessing scheme for memory 5 to help processor 3 and the peripheral devices to access memory 5 . From the viewpoint of memory accessing, system controller 3 should handle all requests ready for accessing memory 5 in the predefined timing, from either processor 1 or peripheral devices 7 and 9 . It is noticed that some essential components in modern computer systems are omitted from the illustrated system architecture, such as caches in the memory hierarchy, shown in FIG. 1 .
- FIG. 2 illustrates detail structures of system controller 3 and memory 5 in the System.
- physical memory devices such as DRAMs
- memory 5 is consisted of memory bank 5 a, memory bank 5 b, memory bank 5 c, and so on, which can be accessed independently under the control of dedicated access controlling signals (not shown).
- FIG. 2 also illustrates three memory access components of system controller 3 , including access control circuit 31 , page management circuit 33 and open-page address table (stored in memories) 35 .
- Access control circuit 31 is responsible for receiving external access requests, which come from either processor 1 or other peripheral devices. It is also responsible for physically executing the access control protocol of memory 5 .
- Page management circuit 33 helps the access control circuit 31 in access controlling, especially in page management.
- Each page of memory 5 contains a fixed number of bytes that can be accessed in the faster operation mode. The byte number of each page depends on the practical application, usually about 32 bytes or more. If a page is “open”, it means that all memory locations contained in this page can be accessed (esp. the writing operation) faster than those contained in “Non open” pages since pre-fetch operations are not required.
- Open-page address table 35 which is implemented by memory devices, is used to memorize the addressing information of all “open” pages in memory 5 .
- page management circuit 33 can properly alter all the addressing information that is stored in open-page address table 35 according to the physical access operations of access control circuit 31 .
- page management circuit 33 also assists access control circuit 31 to effectively access to memory 3 , with reference to the addressing information of all open pages maintained in the open-page address table 35 .
- FIG. 3 shows the schematic system diagram of such an access example, in which peripheral device 9 provides the System with specific data and then peripheral device 7 performs an operation on these specific data.
- the example illustrated in FIG. 3 can be thought of as the case that a modem device (i.e., peripheral device 9 ) downloads an archived video file from the Internet, such as one encoded by the MPEG scheme, and the System employs a dedicated MPEG card (i.e., peripheral device 7 ) to decode or recover the video data.
- each of the peripheral devices is assigned with a dedicated segment of memory used to communicating with each other.
- peripheral device 7 accesses memory segment B 2 by using addresses ADDR# 2 that are dedicated to peripheral device 7 ; the peripheral device 9 accesses memory segment B 1 by addresses ADDR# 1 that are dedicated to peripheral device 9 .
- step S 1 peripheral device 9 stores data, which may be an archived file, to the memory segment B 1 mapping to the addresses ADDR# 1 .
- step S 2 processor 1 must move the inputted data stored in memory segment B 1 to memory segment B 2 mapping to the addresses ADDR# 2 that are dedicated to peripheral device 7 .
- processor 1 reads the data stored in memory segment B 1 (step S 2 ) and writes the data to the memory segment B 2 (step S 3 ). It is obvious that the workload of processor 1 increases since processor 1 must involve in the process of moving data.
- peripheral device 7 can retrieve the data currently stored in memory segment B 2 (step S 4 ), perform the desired operation on these data, such as MPEG decoding, and then write the resulting data back to memory segment B 2 (step S 5 ).
- processor 1 must involve itself in the process of moving data between two memory segments that are individually assigned to two different peripheral devices. It means that the processor 1 must waste time to execute the required data transfer operations and delay other necessary tasks.
- moving data from memory segment B 1 to memory segment B 2 is a time-consuming process. Accordingly, it is obvious that the overall system performance will be degraded due to the task of moving data between two memory segments in such an application.
- An object of the present invention is to provide a method and system for facilitating data exchange between two isolated memory segments and reducing the workload and the processing time of the system processor, thereby increasing the overall performance of the System.
- the present invention achieves this objective by providing an enhanced system controller that supports memory-remapping technology to the System.
- the memory device in the System contains a first memory segment (or first set of physical storage locations) and a second memory segment (or second sets of physical storage locations).
- the system controller is operated under two operating modes.
- the first operating mode also called a normal mode
- the system controller maps a first set of addresses that is dedicated to the first peripheral device to the first memory segment, and maps a second set of addresses that is dedicated to the second peripheral device to the second memory segment.
- Such mapping relationship is the same as that in the conventional case.
- the second operation mode also called a remapping mode
- the system controller changes the original relationship of the addresses to the memory segments.
- the first set of addresses dedicated to the first peripheral device is remapped to the second memory segment and the second set of the addresses dedicated to the second peripheral device is remapped to the first memory segment. Accordingly, the second peripheral device can access the first memory segment involving data previously processed by the first peripheral device without data transfer.
- Switching from the normal mode to the remapping mode is triggered by a first control signal, which can be activated in response to the case that the first peripheral device finishes accessing the first memory segment in the normal mode.
- switching from the remapping mode back to the normal mode is triggered by a second control signal, which can be activated in response to the case that the second peripheral device finishes accessing the first memory segment in the remapping mode.
- the system controller consists of an accessing device, a storage device (embedded memories) and a controlling device.
- the accessing device is responsible for accessing a memory device in response to access requests issued by peripheral devices.
- the storage device is responsible for storing a first mapping table and a second mapping table indicating the relationship of memory segments to different memory address sets.
- the controlling device which is coupled to the storage device and the accessing device, must perform the following two functions.
- the first function is to pick up the required mapping table defining the relationship of the addressing information contained in the input requests to the memory segments from the storing device in response to the current operating mode.
- the second function is to cooperate with the accessing device in actually accessing the memory device by referring to the picked-up mapping table. Therefore, the memory segments, more specifically, the data stored therein, can be readily accessed by different peripheral devices in the different operating modes. No physical data transfer is required.
- the present invention provides a general processing access method requested between the first peripheral device, second peripheral device and memory device to reduce possibility of physical data transfer.
- the first set of addresses dedicated to the first peripheral device is mapped to one of the memory segments within the memory device.
- the first peripheral device can write data to this memory segment using the first set of the addresses.
- the second set of the addresses dedicated to the second peripheral device is remapped to this memory segment in place of the first set. Therefore, the second device can easily read data from this memory segment using the second set of the addresses. No data transfer between two different memory segments is needed in such process.
- FIG. 1 (Prior Art) is a block diagram that illustrates the structure of a conventional computing system or a data-processing system
- FIG. 2 (Prior Art) shows the detail structure of a system controller and a main memory in the computing system or data-processing system;
- FIG. 3 shows the schematic system diagram of a conventional accessing example, in which one peripheral device provides the System with the specific data and the other peripheral device performs an operation on these specific data;
- FIG. 4 is a schematic block diagram that shows architecture of a system controller in accordance with the embodiment of the present invention.
- FIG. 5A shows the schematic system diagram of an accessing example that is the same as the conventional one in the prior art section, in which one peripheral device provides the System with the specific data and the other peripheral device performs an operation on these specific data;
- FIG. 5B is a flowchart that shows detailed steps of accessing example in FIG. 5A;
- FIG. 6 shows the schematic diagram of an accessing example in which three peripheral devices are involved.
- FIGS. 7A, 7 B and 7 C illustrate detailed operational stages of the accessing example in FIG. 6, respectively.
- the present invention employs the memory-remapping technique to facilitate information exchange between various peripheral devices in computing systems or data-processing systems. Since a system controller can access both main memory and various peripheral devices and control physical access to the main memory, it is preferable that the memory-remapping function is directly implemented in the system controller.
- FIG. 4 is a schematic block diagram showing the architecture of a novel system controller 3 a supporting the memory-remapping function.
- the system controller 3 a contains access control circuit 31 , page/remapping management circuit 33 a and open/remapping address table 35 a.
- the function of access control circuit 31 is the same as that of access control circuit 31 in FIG. 2 .
- functions of page/remapping management circuit 33 a and open/remapped address table 35 a are slightly different from those of page management circuit 33 and open-page address table 35 . As a result, they are attached by different notations.
- access control circuit 31 is responsible for physically accessing memory 5 according to the instructions contained in the access requests issued by various peripheral devices.
- CMD 1 , CMD 2 and CMD 3 represent different instructions.
- access requests CMD 1 , CMD 2 and CMD 3 contain different addresses ADDR# 1 , ADDR# 2 and ADDR# 3 which belong to the address ranges dedicated to different peripheral devices, respectively. From the viewpoint of the peripheral devices, they are trying to access the memory segments mapping to these addresses ADDR# 1 , ADDR# 2 and ADDR# 3 , respectively. Assume that the addresses ADDR# 1 , ADDR# 2 and ADDR# 3 are mapped to memory segments 5 a, 5 b and 5 c in the initial settings of the System.
- Open/remapped address table 35 a is used to maintain the mapping relationship of the addressing information contained in the access requests to physical locations of memory 5 . More specifically, open/remapped address table 35 a should clearly define how to map different addresses ADDR# 1 , ADDR# 2 and ADDR# 3 to corresponding physical storage locations of memory 5 , such as segments 5 a ⁇ 5 c. In this embodiment, open/remapped address table 35 a stores two mapping tables, including an initial mapping table used in a normal operating mode (marked by INITIAL) and a remapped mapping table used in a remapping operating mode (marked by REMAPPED).
- INITIAL initial mapping table used in a normal operating mode
- REMAPPED a remapped mapping table used in a remapping operating mode
- open/remapped address table 35 a is capable of containing more mapping tables that are applicable to different default operating modes if necessary.
- open/remapped address table 35 a can be readily implemented using the existing open-page address memory device of the system controller.
- Page/remapping management circuit 33 a is a key component of system controller 3 a and can be implemented by adding the conventional page management circuit with additional circuitry pertaining to remapping function. There are two necessary jobs for page/remapping management circuit 33 a. The first job is to cooperate with access control circuit 31 in actually accessing memory 5 by referring to information contained in the open/remapped address table 35 a. The second job is to select a mapping table from open/remapping address table 35 a for indicating the mapping relationship between memory segments 5 a - 5 c and addresses ADDR# 1 ⁇ ADDR# 3 in the current operating mode. More specifically, according to input control signal CTRL, page/remapping management circuit 33 a can switch the operating modes of system controller 3 a. As described above, in the normal operating mode the initial mapping table indicating pre-defined mapping relationship is applied. On the other hand, the remapped table is applied in the remapping operating mode.
- addresses ADDR# 1 ⁇ ADDR# 3 are one-to-one mapped to memory segments 5 a ⁇ 5 c , respectively. That is, access request CMD 1 can access the memory segment 5 a through addresses ADDR# 1 and access request CMD 2 can access the memory segment 5 b through addresses ADDR# 2 under the control of access control circuit 31 .
- the mapping relationship of memory segments to address will be varied in different operating modes. According to the remapped address table of open/remapped address table 35 a, addresses ADDR# 2 should be mapped to memory segment 5 a, addresses ADDR# 1 should be mapped to memory segment 5 b and addresses ADDR# 1 should be mapped to memory segment 5 c.
- access request CMD 1 involving access addresses ADDR# 1 physically accesses memory segment 5 b and access request CMD 2 involving access addresses ADDR# 2 accesses the memory segment 5 a in such mode.
- peripheral devices can access and process data stored in different memory segments by the change of the operating mode instead of physical data transfer. Changing the current operating mode can be done by the system controller independently and automatically.
- the function of swapping mapping relationship is transparent to users and application programs of the System. The user does not need to activate the function manually as some applications are running. Such processing method can effectively lower the workload of processors and save much time on data transfer between various memory segments.
- Page/remapping management circuit 33 a can utilize mapping information stored in open/remapped address table 35 a by following the command pertaining to control signal CTRL. In the remapping mode, page/remapping management circuit 33 a can redirect addressing information pertaining to an access request received by access control circuit 31 to a memory segment different from the usual one, by referring to the remapping table contained in the open/remapped page address table 35 a.
- FIG. 5A shows a schematic diagram of an accessing example, in which a system controller with memory-remapping function is involved.
- the accessing example shown in FIG. 5A is similar to the conventional case shown in FIG. 2 . That is, the peripheral device 9 stores specific data to memory segment B 1 and the peripheral device 7 retrieves these specific data, processes them and writes the resulting data back.
- FIG. 5A shows detail steps of this accessing example, which are marked by S 11 , S 12 (not shown), S 13 and S 14 . The details of these steps in the flowchart of FIG. 5B are described as follows.
- step S 11 peripheral device 9 writes data to memory segment B 1 , which are currently addressed by addresses ADDR# 1 dedicated to peripheral device 9 . Meanwhile, the peripheral device 7 accesses memory segment B 2 that is currently addressed by addresses ADDR# 2 .
- the mapping relations between (B 1 , ADDR# 1 ) and (B 2 , ADDR# 2 ) are controlled and managed by the system controller of this embodiment shown in FIG. 4 .
- system controller 3 a starts to perform a remapping operation in step S 12 , thereby redirecting addresses ADDR# 2 dedicated to peripheral device 7 to memory segment B 1 containing the data stored by peripheral device 9 .
- system controller 3 a can execute such a remapping function under the control of page/remapping management circuit 33 a, which redirects any request containing addresses ADDR# 1 to access memory segment B 2 and redirects any requests containing addresses ADDR# 2 to access memory segment B 1 .
- peripheral device 7 reads the data from memory segment B 1 by using the addresses ADDR# 2 . From the viewpoint of peripheral device 7 , it always uses addresses ADDR# 2 to access memory 5 . However, peripheral device 7 physically accesses memory segment B 2 in the normal operating mode and physically accesses memory segment B 1 in the remapping operating mode. After processing the retrieved data, peripheral device 7 writes the resulting data back to memory segment B 1 in step S 14 by using addresses ADDR# 2 .
- FIG. 6 shows a schematic system diagram of a practical accessing example involving three peripheral devices.
- these peripheral devices includes modem 60 , MPEG II card 61 and graphic adaptor 62 .
- modem 60 first retrieves archived video data (encoded by MPEG II scheme) from an external site and writes them into memory 5 .
- MPEG II card 61 retrieves the archived video data from memory 5 and applies the MPEG decoding scheme on these archived video data to recover the normal video data.
- graphic adaptor 62 displays the normal video data on a specific monitor. Therefore, in this example, the archived video data and the normal video data should be placed in the physical storage locations that these peripheral devices can properly access.
- ADDR# 1 , ADDR# 2 and ADDR# 3 the corresponding addressing ranges of modem 60 , MPEG II card 61 and graphic adaptor 62 are denoted by ADDR# 1 , ADDR# 2 and ADDR# 3 , respectively.
- memory segments R 1 , R 2 and R 3 of memory 5 are assigned to ADDR# 1 , ADDR# 2 and ADDR# 3 in the normal mode.
- symbols a ⁇ f sequentially indicate the data flow in this example.
- FIGS. 7A, 7 B and 7 C illustrate operation stages of this accessing example, in which the system controller with memory-remapping function is employed. It is noticed that there are two extra remapped modes: a first remapped mode and a second remapped mode. They will be described later in detail.
- FIG. 7A illustrates the case in which the System is in the normal mode. Accordingly, modem 60 can access memory segment R 1 by using its dedicated addresses ADDR# 1 . More specifically, modem 60 writes the archived video data, which may be downloaded from the outside, to memory segment R 1 . At the same time, MPEG II card 61 and graphic adaptor 62 access memory segments R 2 and R 3 , respectively.
- the system controller can activate a remapping process to change the current normal mode to the first remapping mode, in which memory segments R 1 , R 2 and R 3 are addressed by addresses ADDR# 2 , ADDR# 3 and ADDR# 1 , respectively. It is noticed that the mapping relationship of memory segments and peripheral devices are changed.
- MPEG II card 61 can directly access memory segment R 1 by using its dedicated addresses ADDR# 2 . The archived video data still remain in memory segment R 1 . Accordingly, MPEG II card 61 can retrieve the archived video data stored in memory segment R 1 , decode them and write the normal video data to memory segment R 1 , as shown in FIG. 7 B.
- the system controller can activate a remapping process to switch to the second remapped operating mode, in which memory segments R 1 , R 2 and R 3 are addressed by the addresses ADDR# 3 , ADDR# 1 and ADDR# 2 , respectively.
- graphic adaptor 62 can directly access memory segment R 1 by using its dedicated addresses ADDR# 3 . Notice that data still remain in memory segment R 1 . Accordingly, graphic adaptor 62 can retrieve the normal video data from memory segment R 1 and display them on the display monitor, as shown in FIG. 7 C.
- FIGS. 7A, 7 B and 7 C form a working cycle that can be recursively executed until all data are processed.
- the presented access scheme is better than the conventional case.
- the system processor is not involved and it is not required to actually transfer data between different memory segments.
- control signal CTRL for informing the page/remapping management circuit 33 a of mode-related information is briefly explained.
- control signal CTRL is used to indicate the current operating mode required.
- control signal CTRL may be issued when modem 60 finishes data-writing operation, or when MPEG II card 61 finishes data-processing operation, or when graphic adaptor 62 finishes data-retrieving operation.
- the most proper method for maintaining data integrity is to wait until all peripheral devices have finished the required tasks in each phase before performing any remapping operation.
- MPEG II card 61 usually requires more processing time than other peripherals. Therefore, control signal CTRL can also be activated in response to the processing status of MPEG II card 61 .
- these memory segments mapped to these peripheral devices should be located in different memory banks, and can be accessed simultaneously.
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US09/260,637 US6393498B1 (en) | 1999-03-02 | 1999-03-02 | System for reducing processor workloads with memory remapping techniques |
TW088108183A TW432281B (en) | 1999-03-02 | 1999-05-19 | Method and system for reducing processor workload by using memory-remapping technique |
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US09/260,637 US6393498B1 (en) | 1999-03-02 | 1999-03-02 | System for reducing processor workloads with memory remapping techniques |
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US20140215130A1 (en) * | 2013-01-28 | 2014-07-31 | Phison Electronics Corp. | Clock switching method, memory controller and memory storage apparatus |
US9424177B2 (en) * | 2013-01-28 | 2016-08-23 | Phison Electronics Corp. | Clock switching method, memory controller and memory storage apparatus |
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