US6473346B1 - Self burn-in circuit for semiconductor memory - Google Patents
Self burn-in circuit for semiconductor memory Download PDFInfo
- Publication number
- US6473346B1 US6473346B1 US08/587,746 US58774696A US6473346B1 US 6473346 B1 US6473346 B1 US 6473346B1 US 58774696 A US58774696 A US 58774696A US 6473346 B1 US6473346 B1 US 6473346B1
- Authority
- US
- United States
- Prior art keywords
- burn
- test
- data
- signal
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
Definitions
- the present invention relates to a self burn-in circuit for semiconductor memory, and in particular to an improved self burn-in circuit for a semiconductor memory capable of generating a control signal, an address, and a test data from the interior of a chip for a burn-in test operation when a certain self burn-in test condition is satisfied.
- the burn-in test is referred to a process for testing chip by applying a certain level voltage higher than that of a normal voltage so that an initial error of chip can effectively checked for a relatively short time.
- an internal power generator is provided, so that the device of the chip can be driven by voltage lower than an externally supplied voltage.
- the internal voltage generator has a characteristic of maintaining a constant level of voltage irrespective of variation of an externally supplied voltage in a normal operation interval so as to secure chip reliability and stable operation. Therefore, a certain voltage higher than that of the normal operation should be applied to the entire devices of the chip.
- the internal voltage generator maintaining a constant voltage should generate voltage proportional to the variation of the externally supplied voltage. That is, in case that the level of the externally supplied voltage applied to the chip is beyond the normal operation interval and approaches a burn-in start voltage, the burn-in circuit detects the above-mentioned state and converts the operation state of the chip into a burn-in test mode. In addition, in case that the externally supplied voltage is converted into the normal operation state, the burn-in circuit acts as a role of converting the operation state of the chip into the normal operation mode.
- the conventional burn-in circuit for testing a burn-in test is directed to detecting a start of the burn-in operation when an externally supplied voltage is increased up to a certain level by providing a burn-in detection unit and to performing a cell aging operation by receiving a test data so as to test the operation the cell for selecting a control signal and a cell array from the outside of the system.
- the conventional burn-in circuit for a burn-in test has disadvantages in that in a state that the memory chip is connected to the burn-in test apparatus, since a control signal, an address and a test data outputted from the burn-in test apparatus is provided to the chip, the test board becomes complicated due to lines for receiving and transmitting signals, so that the number of chips available is limited, and the test process becomes complicated.
- a self burn-in circuit for a semiconductor memory which includes a burn-in detector for generating a certain control signal, an address signal, and a test data for a burn-in test operation when a certain self burn-in test condition is achieved; and a memory array for performing a burn-in test operation when said test data is written on/read from a memory cell which is selected by said address signal in accordance with said control signal.
- FIG. 1 is a block diagram of a self burn-in circuit for a semiconductor memory according to the present invention.
- FIG. 2 is a flow chart of an operation of a self burn-in circuit for a semiconductor memory according to the present invention.
- FIG. 3 is a view showing an address and test data format of FIG. 1 according to the present invention.
- FIGS. 4A through 4I are views showing a timing of a signal outputted from each element of FIG. 1 according to the present invention.
- FIG. 1 shows a self burn-in circuit for a semiconductor memory of the present invention, which includes a memory cell array 10 , a burn-in detector 20 for outputting a self burn-in test control signal, an address, and a test data when a burn-in test mode signal TM is not inputted thereto which indicates a general burn-in test operation in a state that the externally supplied voltage is increased up to a certain level, a control signal buffer 30 for buffering a control signal outputted from the burn-in detector 20 , an address buffer 40 for buffering an address outputted from the burn-in detector 20 , a column decoder 50 and a row decoder 60 for decoding an address outputted from the address buffer 40 in accordance with a control signal outputted from the control signal buffer 30 and for selecting word line and a bit line of the memory cell array 10 , and a data comparator 70 for comparing the data outputted from the memory cell array 10 with the data outputted from the burn-in detector 20 .
- a control signal buffer 30 for buffer
- the burn-in detector 20 includes a burn-in detector 21 for outputting a self burn-in test signal SBITM for the burn-in test when a test mode signal TM which indicates a burn-in test operation is not inputted thereto in a state that an externally supplied voltage is increased up to a certain level, a pulse generator 22 for outputting a clock signal having a certain cycle in accordance with a self burn-in test signal outputted from the burn-in detector 21 , a control signal generator 23 for generating a row address strobe (RAS) and a column address strobe (CAS) using a clock pulse in accordance with a self burn-in test signal and for outputting write/read enable signals WE and OE using an address of an address counter 24 , an address counter 24 for generating an address using a clock pulse in accordance with a self burn-in test signal and for synchronizing the generated address to the RAS and CAS, and a data generator 25 for reading a test data from the address and for outputting the read data to the
- the burn-in detector 21 detects whether voltage Vcc is increased up to a certain level.
- the burn-in detector 21 judges as a burn-in mode for a burn-in test when the level of the voltage Vcc is increased up to a certain level, and otherwise judges as a normal operation mode. Therefore, when the burn-in detector 21 detects a burn-in mode, the burn-in related operations are performed, and otherwise a normal operation mode is performed. Thereafter, the burn-in detector 21 judges whether a burn-in test operation mode is externally supplied.
- the burn-in detector 21 When the test mode signal TM indicating a general burn-in test operation is inputted from the outside, the burn-in detector 21 performs a certain process same as the prior art, and otherwise the burn-in detector 21 generates a self burn-in test signal SBITM for a self burn-in test operation.
- the burn-in detector 21 When the burn-in detector 21 outputs a self burn-in test signal SBITM, the pulse generator 22 outputs a clock pulse having a constant cycle in cooperation with an oscillator or the like. Thereafter, the control signal generator 23 is enabled in accordance with a self burn-in test signal and divides the clock pulse into a certain cycle and outputs a self burn-in test RAS and CAS and outputs to the control signal buffer 30 .
- the address counter 24 is enabled by a self burn-in test signal SBITM and outputs an M-bit low address and an N-bit column address in accordance with a clock pulse applied thereto.
- the forms of the low address and column address as shown in FIG. 3 consist of the M- and N-bits, respectively.
- write/read selection bits which indicate a separation between the write operation and the read operation at an upper portion of the M- and N-bit address, and the test data written to and read from a certain cell selected in accordance with M- and N-bits addresses is occupied at a most significant bit.
- the thusly formed address is synchronized with RAS and CAS outputted from the control signal generator 23 and outputted to the address buffer 40 .
- the control signal generator 23 outputs a write enable signal WE and a lead enable signal OE in accordance with a write/read selection bit of the address and outputs to the control signal buffer 30 .
- control signal buffer 30 outputs the RAS, CAS and the write enable signal WE outputted from, the control signal generator 23 to the column decoder 50 and the row decoder 60 , respectively, and the address buffer 40 outputs the address and the test data outputted from the address counter 24 to the column decoder 50 and the row decoder 60 , respectively. Therefore, the column decoder 50 and the row decoder 60 decode the row address and the column address in accordance with a control signal and select a corresponding cell of the memory cell array 10 , and writes a test data to the corresponding cell.
- the thusly written test data are read in accordance with a control of the read enable signal OE outputted from the control signal generator 23 and outputted to the data comparator 70 .
- the data comparator 70 compares the test data outputted from the cells of the memory cell array 10 with the test data outputted from the data generator 25 .
- the data generator 25 reads the test data contained in the MSB (most significant bit) of the address and outputs to the data comparator 70 .
- RAS, CAS, the write enable signal WE, the lead enable signal OE, and the address which are applied from the externally connected test apparatus, are generated by the burn-in detector 20 .
- FIGS. 4A through 4I show timings of each signal related to the self burn-in operation.
- FIG. 4A shows voltage Vcc applied to the burn-in detector 21 .
- the burn-in detector 21 checks whether a test mode signal TM is externally applied.
- the burn-in detector 21 outputs a self burn-in test signal SBITM as shown in FIG. 4 C. Therefore, the pulse generator 22 is enabled in accordance with a self burn-in test signal SBITM and generates a certain clock pulse as shown in FIG. 4 D.
- control signal generator 23 is enabled in accordance with a self burn-in test signal SBITM and divides the clock pulse into a certain ratio and outputs self burn-in test RAS signal SBIRASB and CAS signal SBICASB as shown in FIGS. 4E and 4F.
- the address counter 24 is enabled in accordance with a self burn-in test signal SBITM and divides the clock pulse into a certain ratio and outputs an address as shown in FIG. 4G, and the thusly outputted address is synchronized with the self burn-in RAS SBIRASB and CAS SBICASB and outputted.
- the address is directed to changing the row address in order with respect to one column address, and all of the cells with respect to the corresponding column address is selected.
- test data SBIDin When a certain cell with respect to one column address is selected, the next cell with the respect to a certain column address is selected. That is, all of the cells are selected in the above-mentioned method.
- the test data SBIDin When the test data SBIDin are written with respect to all of the cells of the memory cell array 10 , a data reading operation with respect to the thusly written data is performed as shown in FIG. 4 H. The time that the test data is written/read is determined as the control signal generator 23 reads the write/read selection bit from the address outputted from the address counter 24 . While the test data is written on/read from the mode cell of the memory cell array 23 , the test data SBIDin outputted from the data generator 25 retains the data form as shown in FIG.
- the self burn-in circuit for a semiconductor memory is directed to effectively adapting an application specific memory (ASM) to a burn-in test operation so that the self burn-in test is performed by itself in case that an externally supplied voltage exceeds a certain level and the burn-in test operation is not forcibly performed.
- ASM application specific memory
- various control signals which are necessary for the common burn-in test process are generated in the chip, it is possible to reduce burn-in test time in the common burn-in test operation which is forcibly performed. In addition, it is possible to increase the number of chips which are tested at one time.
Abstract
Description
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR95-0056430 | 1995-12-26 | ||
KR1019950056430A KR100214466B1 (en) | 1995-12-26 | 1995-12-26 | Circuit self burn-in of semiconductor memory |
Publications (1)
Publication Number | Publication Date |
---|---|
US6473346B1 true US6473346B1 (en) | 2002-10-29 |
Family
ID=19444345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/587,746 Expired - Fee Related US6473346B1 (en) | 1995-12-26 | 1996-01-19 | Self burn-in circuit for semiconductor memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US6473346B1 (en) |
JP (1) | JP2938797B2 (en) |
KR (1) | KR100214466B1 (en) |
DE (1) | DE19603107B4 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020008984A1 (en) * | 1997-05-30 | 2002-01-24 | Brent Keeth | 256 Meg dynamic random access memory |
US20030014702A1 (en) * | 2001-06-20 | 2003-01-16 | Thomas Finteis | Apparatus and method for testing a device for storing data |
US6650581B2 (en) * | 2001-06-29 | 2003-11-18 | Hynix Semiconductor Inc. | Semiconductor memory device, and method for testing the same |
US20040230880A1 (en) * | 2003-05-12 | 2004-11-18 | Kingston Technology Corp. | Memory-Module Burn-In System With Removable Pattern-Generator Boards Separated from Heat Chamber by Backplane |
US20080112249A1 (en) * | 2006-11-14 | 2008-05-15 | Hynix Semiconductor Inc. | Circuit and method of generating voltage of semiconductor memory apparatus |
US20080239842A1 (en) * | 2007-03-31 | 2008-10-02 | Hynix Semiconductor Inc. | Semiconductor memory device |
CN109346119A (en) * | 2018-08-30 | 2019-02-15 | 武汉精鸿电子技术有限公司 | A kind of semiconductor memory burn-in test core board |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100510480B1 (en) * | 1999-02-25 | 2005-08-26 | 삼성전자주식회사 | Data write circuit for burn in mode |
DE10014388A1 (en) | 2000-03-23 | 2001-10-04 | Infineon Technologies Ag | Conducting memory device burn-in process enabling electrical characteristics of memory device to be stabilised - involves applying reference potential, second voltage to voltage connections, varying control voltage between reference potential and operating voltage |
KR100753050B1 (en) | 2005-09-29 | 2007-08-30 | 주식회사 하이닉스반도체 | Test device |
Citations (4)
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US5321653A (en) * | 1992-03-31 | 1994-06-14 | Samsung Electronics Co., Ltd. | Circuit for generating an internal source voltage |
US5452253A (en) * | 1992-09-24 | 1995-09-19 | Goldstar Electron, Co. Ltd. | Burn-in test circuit for semiconductor memory device |
US5471429A (en) * | 1993-11-26 | 1995-11-28 | Samsung Electronics Co., Ltd. | Burn-in circuit and method therefor of semiconductor memory device |
US5537537A (en) * | 1990-01-12 | 1996-07-16 | Sony Corporation | Burn-in diagnostic technique for a disc driving apparatus |
Family Cites Families (6)
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JPS63184989A (en) * | 1987-01-28 | 1988-07-30 | Mitsubishi Electric Corp | Semiconductor storage device |
JPH02276090A (en) * | 1989-04-17 | 1990-11-09 | Nec Corp | Semiconductor memory integrated circuit |
JPH033200A (en) * | 1989-05-30 | 1991-01-09 | Nec Corp | Semiconductor memory |
KR950004858B1 (en) * | 1992-03-17 | 1995-05-15 | 삼성전자 주식회사 | Internal source voltage generating circuit |
JP2557594B2 (en) * | 1992-04-16 | 1996-11-27 | 株式会社東芝 | Semiconductor memory device |
US5375091A (en) * | 1993-12-08 | 1994-12-20 | International Business Machines Corporation | Method and apparatus for memory dynamic burn-in and test |
-
1995
- 1995-12-26 KR KR1019950056430A patent/KR100214466B1/en not_active IP Right Cessation
-
1996
- 1996-01-19 US US08/587,746 patent/US6473346B1/en not_active Expired - Fee Related
- 1996-01-25 JP JP8011145A patent/JP2938797B2/en not_active Expired - Fee Related
- 1996-01-29 DE DE19603107A patent/DE19603107B4/en not_active Expired - Fee Related
Patent Citations (4)
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US5537537A (en) * | 1990-01-12 | 1996-07-16 | Sony Corporation | Burn-in diagnostic technique for a disc driving apparatus |
US5321653A (en) * | 1992-03-31 | 1994-06-14 | Samsung Electronics Co., Ltd. | Circuit for generating an internal source voltage |
US5452253A (en) * | 1992-09-24 | 1995-09-19 | Goldstar Electron, Co. Ltd. | Burn-in test circuit for semiconductor memory device |
US5471429A (en) * | 1993-11-26 | 1995-11-28 | Samsung Electronics Co., Ltd. | Burn-in circuit and method therefor of semiconductor memory device |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7477556B2 (en) * | 1997-05-30 | 2009-01-13 | Micron Technology, Inc. | 256 Meg dynamic random access memory |
US20020008984A1 (en) * | 1997-05-30 | 2002-01-24 | Brent Keeth | 256 Meg dynamic random access memory |
US8189423B2 (en) | 1997-05-30 | 2012-05-29 | Round Rock Research, Llc | 256 Meg dynamic random access memory |
US7969810B2 (en) | 1997-05-30 | 2011-06-28 | Round Rock Research, Llc | 256 Meg dynamic random access memory |
US7489564B2 (en) * | 1997-05-30 | 2009-02-10 | Micron Technology, Inc. | 256 Meg dynamic random access memory |
US20070008811A1 (en) * | 1997-05-30 | 2007-01-11 | Brent Keeth | 256 Meg dynamic random access memory |
US20030014702A1 (en) * | 2001-06-20 | 2003-01-16 | Thomas Finteis | Apparatus and method for testing a device for storing data |
US7159157B2 (en) * | 2001-06-20 | 2007-01-02 | Infineon Technologies Ag | Apparatus and method for testing a device for storing data |
US6650581B2 (en) * | 2001-06-29 | 2003-11-18 | Hynix Semiconductor Inc. | Semiconductor memory device, and method for testing the same |
US6910162B2 (en) | 2003-05-12 | 2005-06-21 | Kingston Technology Corp. | Memory-module burn-in system with removable pattern-generator boards separated from heat chamber by backplane |
US20040230880A1 (en) * | 2003-05-12 | 2004-11-18 | Kingston Technology Corp. | Memory-Module Burn-In System With Removable Pattern-Generator Boards Separated from Heat Chamber by Backplane |
US20080112249A1 (en) * | 2006-11-14 | 2008-05-15 | Hynix Semiconductor Inc. | Circuit and method of generating voltage of semiconductor memory apparatus |
US7602664B2 (en) * | 2006-11-14 | 2009-10-13 | Hynix Semiconductor Inc. | Circuit and method of generating voltage of semiconductor memory apparatus |
US7936633B2 (en) | 2006-11-14 | 2011-05-03 | Hynix Semiconductor Inc. | Circuit and method of generating voltage of semiconductor memory apparatus |
US20080239842A1 (en) * | 2007-03-31 | 2008-10-02 | Hynix Semiconductor Inc. | Semiconductor memory device |
US7782684B2 (en) * | 2007-03-31 | 2010-08-24 | Hynix Semiconductor, Inc. | Semiconductor memory device operating in a test mode and method for driving the same |
CN109346119A (en) * | 2018-08-30 | 2019-02-15 | 武汉精鸿电子技术有限公司 | A kind of semiconductor memory burn-in test core board |
CN109346119B (en) * | 2018-08-30 | 2021-07-23 | 武汉精鸿电子技术有限公司 | Semiconductor memory aging test core board |
Also Published As
Publication number | Publication date |
---|---|
DE19603107A1 (en) | 1997-07-03 |
KR100214466B1 (en) | 1999-08-02 |
DE19603107B4 (en) | 2013-01-31 |
JPH09219099A (en) | 1997-08-19 |
JP2938797B2 (en) | 1999-08-25 |
KR970051423A (en) | 1997-07-29 |
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