US6687863B1 - Integrated circuit internal signal monitoring apparatus - Google Patents

Integrated circuit internal signal monitoring apparatus Download PDF

Info

Publication number
US6687863B1
US6687863B1 US09/674,018 US67401801A US6687863B1 US 6687863 B1 US6687863 B1 US 6687863B1 US 67401801 A US67401801 A US 67401801A US 6687863 B1 US6687863 B1 US 6687863B1
Authority
US
United States
Prior art keywords
signal
internal
integrated circuit
monitoring apparatus
flags
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US09/674,018
Inventor
Takao Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority claimed from PCT/JP1999/004103 external-priority patent/WO2001013135A1/en
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INOUE, TAKAO
Application granted granted Critical
Publication of US6687863B1 publication Critical patent/US6687863B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's

Definitions

  • the present invention relates to an integrated circuit internal signal monitoring apparatus, in particular, an apparatus characterized by a read operation of a plurality of internal states without increasing the number of input/output pins provided in a large scale integrated circuit (hereinafter, referred to as an LSI) system.
  • an LSI large scale integrated circuit
  • a conventional integrated circuit internal signal monitoring apparatus will be described with reference to FIG. 3 .
  • a selector 19 is provided in order to monitor from outside an internal operation of a circuit block 12 provided in an LSI 11 .
  • the circuit block 12 has its original function.
  • the selector 19 receives signals 21 to be monitored among signals inside the circuit block 12 as inputs, and also receives a selection signal 31 from outside the LSI 11 through an input pin, thus to designate the specific signal to be monitored. Based on the value of the selection signal 31 , the selector 19 selects a plurality of signals 32 from the input signals 21 and outputs the signals 32 to outside the LSI 11 through an output pin, so that the signals can be monitored.
  • the conventional structure described above has the following problem.
  • signals driven inside the LSI 11 are monitored outside through the LSI output pins, a large number of output pins for monitoring and the selection signal input pins are required, as the number of the signals to be simultaneously monitored increases. Therefore, the number of pins in the entire LSI 11 increases.
  • An integrated circuit internal signal monitoring apparatus includes: an integrated circuit, including: signal change information generating means for detecting changes in a plurality of internal signals to be monitored in a circuit block, and for, when a level of at least one of the plurality of internal signals is changed, sequentially generating flags indicating the internal signal whose level has been changed, the post-change level, and that the levels of other internal signals have not been changed, storage means for sequentially storing the flags generated by the signal change information generating means, and trigger generating means for generating a write stop trigger signal for stopping a write operation of the flags to the storage means; and internal signal waveform reproduction means for reading the flags from the storage means after the generation of the write stop trigger signal, and reproducing waveforms of the plurality of internal signals.
  • the storage means includes a ring buffer, and the flags may be sequentially stored in the ring buffer in a time series.
  • the trigger generating means may generate the write stop trigger signal when a value of one of the plurality of internal signals and an expected value of a signal input from outside the integrated circuit match each other.
  • LSI internal signals around a required point can be monitored with a significantly smaller number of input/output pins compared to the prior art, and debug can easily be performed based on a signal state around a generation time of external events and internal events.
  • a signal change point value is stored to a storage device, and information of the storage device is read from outside to form waveforms as necessary.
  • the number of LSI input/output pins can be reduced, and, in a system incorporating an LSI, the system can easily be debugged by monitoring an internal signal state with the time to monitor being specified.
  • the capacity of storage means can be reduced, and an internal signal state of an LSI system can be monitored without increasing the number of LSI input/output pins, and thus system debug is easily performed.
  • FIG. 1 is a block diagram of an integrated circuit internal signal monitoring apparatus according to an embodiment of the present invention.
  • FIG. 2 shows a waveform diagram of signals to be monitored by the integrated circuit internal signal monitoring apparatus according to the embodiment of the present invention and a diagram for schematically illustrating a recording state of a ring buffer.
  • FIG. 3 is a block diagram of a conventional integrated circuit internal signal monitoring apparatus.
  • FIG. 1 illustrates a block structure of an LSI internal signal monitoring apparatus 100 according to the present invention.
  • FIG. 2 illustrates a waveform diagram and storage contents for illustrating an operation of recording signal change information of internal signals to be monitored of an LSI 11 to a storage device.
  • signals 21 as monitoring targets inside the circuit block 12 are processed with a structure described below.
  • the circuit block 12 has its original function.
  • the signals 21 as monitoring targets are input to a signal change information generating section 13 .
  • changes, flags 28 indicating the signal level immediately after the change, and that the other signals have not been changed are generated, and are sequentially stored in a ring buffer 14 .
  • the timing to stop a write operation to the ring buffer 14 depends on a write stop trigger signal 27 , which is output from an event trigger generating section 15 .
  • a process of an event trigger generation There are two types of trigger events; one is based on a change in a signal 24 from outside the LSI 11 , and the other is based on a change in an internal signal 22 of the circuit block 12 .
  • the write stop trigger signal 27 is generated based on the change in the signal 24 from outside.
  • the write stop trigger signal 27 is generated based on the change in the internal signal 22 .
  • a signal used for a trigger event is selected from the internal signals 22 by using a selector 18 based on an event designation signal 23 set from outside the LSI 11 and stored in an internal state latching section 16 .
  • An expected value of the signal selected by the event designation signal 23 is written to an event designation section 17 .
  • a signal value 25 which is to be a trigger factor and an expected signal value 26 written to the event designation section are continuously compared by the event trigger generating section 15 , and when the signal values 25 and 26 match, the trigger signal 27 is output.
  • the write stop trigger signal 27 output by the event trigger generating section 15 stops the write operation of the flag information 28 to the ring buffer 14 .
  • the write stop trigger signal 27 is output to an internal signal waveform reproduction section 30 , and thus, the information that the write operation to the ring buffer 14 has been stopped is sent to the internal signal waveform reproduction section 30 .
  • the internal signal waveform reproduction section 30 provided outside the LSI 11 reads out read information 29 from the ring buffer 14 .
  • the read operation can also be performed by using a single serial pin.
  • the internal signal waveform reproduction section 30 reproduces an internal signal waveform based on the read information 29 .
  • the flag 28 is write information to be written to the ring buffer 14 (having 8 locations) for storing the signal change information of the internal signals of the LSI 11 to be monitored. It is assumed that 4 types of signals are input to the signal change information generating section 13 . First, at point [ 1 ] where signal A changes from “L” to “H”, other signals B, C, and D do not change. Therefore, the flag 28 , which is the write information to be written to the ring buffer 14 , is “1” for signal A immediately after a rise, indicating “H”, and “2” for the other signals, indicating that the level has not been changed.
  • the flag 28 as the write information to be written to the ring buffer 14 is “0” for signal B immediately after a fall, indicating “L”, and “2” for the other signals, indicating that the level has not been changed. Thereafter, flag information at the signal change points are sequentially written to the ring buffer 14 in a similar manner.
  • the flag information at point [ 9 ](“1” for signal B, and “2” for the other signals) is written over the leading information of the ring buffer 14 .
  • an address pointer of the ring buffer 14 points to the pointer position in the figure in the state where the flag information up to the state at change point [ 10 ] has been written to the ring buffer 14 .
  • the event trigger generating section 15 outputs the write stop trigger signal 27 at this point, the write operation of the flag information 28 to the ring buffer 14 stops.
  • the output flag information 29 is read in the order of [ 3 ], [ 4 ], [ 5 ], [ 6 ], [ 7 ], [ 8 ], [ 9 ], and [ 10 ], starting from the pointer.
  • waveforms of signals A, B, C, and D can be reproduced.
  • the present invention it is possible to reduce the number of input/output pins used, regardless of the number of internal control signals to be monitored, and thus to provide an integrated circuit internal signal monitoring apparatus which is capable of simultaneously monitoring a large number of signals.
  • a chip size of the LSI can be smaller.
  • trigger generation and signal analysis using an external logic analyzer not required. Therefore, a phase relation of the inner control signals around the event trigger generation time can easily be analyzed.

Abstract

An integrated circuit internal signal monitoring apparatus comprises an integrated circuit. The integrated circuit comprises a signal change information generating section for detecting changes in a plurality of internal signals to be monitored in a circuit block, and in response to a level of at least one of the plurality of internal signals changing sequentially generating flags indicating the internal signal whose level has been changed, the post-change level, and that the levels of other internal signals have not been changed; a storage section for sequentially storing the flags and a trigger generating section for generating a write stop trigger signal for stopping a write operation of the flags to the storage section The integrated circuit internal signal monitoring apparatus further comprises an internal signal waveform reproduction section for reading the flags from the storage section after the generation of the write stop trigger signal.

Description

TECHNICAL FIELD
The present invention relates to an integrated circuit internal signal monitoring apparatus, in particular, an apparatus characterized by a read operation of a plurality of internal states without increasing the number of input/output pins provided in a large scale integrated circuit (hereinafter, referred to as an LSI) system.
BACKGROUND ART
Conventionally, an integrated circuit internal signal monitoring apparatus as described in Japanese Patent No. 2580558 is known.
A conventional integrated circuit internal signal monitoring apparatus will be described with reference to FIG. 3. In order to monitor from outside an internal operation of a circuit block 12 provided in an LSI 11, a selector 19 is provided. The circuit block 12 has its original function. The selector 19 receives signals 21 to be monitored among signals inside the circuit block 12 as inputs, and also receives a selection signal 31 from outside the LSI 11 through an input pin, thus to designate the specific signal to be monitored. Based on the value of the selection signal 31, the selector 19 selects a plurality of signals 32 from the input signals 21 and outputs the signals 32 to outside the LSI 11 through an output pin, so that the signals can be monitored.
However, the conventional structure described above has the following problem. When signals driven inside the LSI 11 are monitored outside through the LSI output pins, a large number of output pins for monitoring and the selection signal input pins are required, as the number of the signals to be simultaneously monitored increases. Therefore, the number of pins in the entire LSI 11 increases.
Furthermore, when monitoring the LSI internal signals from outside the LSI 11 with a logic analyzer or the like, a signal analysis performed with the internal states of the LSI as event conditions requires even the internal signals relating to the event conditions to be output externally. This causes a problem of a further increase in the number of the input/output pins.
DISCLOSURE OF THE INVENTION
An integrated circuit internal signal monitoring apparatus according to the present invention includes: an integrated circuit, including: signal change information generating means for detecting changes in a plurality of internal signals to be monitored in a circuit block, and for, when a level of at least one of the plurality of internal signals is changed, sequentially generating flags indicating the internal signal whose level has been changed, the post-change level, and that the levels of other internal signals have not been changed, storage means for sequentially storing the flags generated by the signal change information generating means, and trigger generating means for generating a write stop trigger signal for stopping a write operation of the flags to the storage means; and internal signal waveform reproduction means for reading the flags from the storage means after the generation of the write stop trigger signal, and reproducing waveforms of the plurality of internal signals. Thus, the above-described problems are solved.
The storage means includes a ring buffer, and the flags may be sequentially stored in the ring buffer in a time series.
The trigger generating means may generate the write stop trigger signal when a value of one of the plurality of internal signals and an expected value of a signal input from outside the integrated circuit match each other.
According to one aspect of the present invention, LSI internal signals around a required point can be monitored with a significantly smaller number of input/output pins compared to the prior art, and debug can easily be performed based on a signal state around a generation time of external events and internal events.
According to another aspect of the present invention, only a signal change point value is stored to a storage device, and information of the storage device is read from outside to form waveforms as necessary. Thus, the number of LSI input/output pins can be reduced, and, in a system incorporating an LSI, the system can easily be debugged by monitoring an internal signal state with the time to monitor being specified.
According to still another aspect of the present invention, the capacity of storage means can be reduced, and an internal signal state of an LSI system can be monitored without increasing the number of LSI input/output pins, and thus system debug is easily performed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an integrated circuit internal signal monitoring apparatus according to an embodiment of the present invention.
FIG. 2 shows a waveform diagram of signals to be monitored by the integrated circuit internal signal monitoring apparatus according to the embodiment of the present invention and a diagram for schematically illustrating a recording state of a ring buffer.
FIG. 3 is a block diagram of a conventional integrated circuit internal signal monitoring apparatus.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment according to the present invention will be described with reference to FIGS. 1 and 2.
FIG. 1 illustrates a block structure of an LSI internal signal monitoring apparatus 100 according to the present invention. FIG. 2 illustrates a waveform diagram and storage contents for illustrating an operation of recording signal change information of internal signals to be monitored of an LSI 11 to a storage device.
In order to monitor from outside an internal operation of a circuit block 12 provided in the LSI 11, signals 21 as monitoring targets inside the circuit block 12 are processed with a structure described below. The circuit block 12 has its original function. The signals 21 as monitoring targets are input to a signal change information generating section 13. When an arbitrary signal, among all the signals 21 as monitoring targets, changes, flags 28 indicating the signal level immediately after the change, and that the other signals have not been changed, are generated, and are sequentially stored in a ring buffer 14. The timing to stop a write operation to the ring buffer 14 depends on a write stop trigger signal 27, which is output from an event trigger generating section 15.
Next, a process of an event trigger generation will be described. There are two types of trigger events; one is based on a change in a signal 24 from outside the LSI 11, and the other is based on a change in an internal signal 22 of the circuit block 12. In the former case, the write stop trigger signal 27 is generated based on the change in the signal 24 from outside. In the latter case, the write stop trigger signal 27 is generated based on the change in the internal signal 22. In more detail, a signal used for a trigger event is selected from the internal signals 22 by using a selector 18 based on an event designation signal 23 set from outside the LSI 11 and stored in an internal state latching section 16. An expected value of the signal selected by the event designation signal 23 is written to an event designation section 17. A signal value 25 which is to be a trigger factor and an expected signal value 26 written to the event designation section are continuously compared by the event trigger generating section 15, and when the signal values 25 and 26 match, the trigger signal 27 is output.
The write stop trigger signal 27 output by the event trigger generating section 15 stops the write operation of the flag information 28 to the ring buffer 14. The write stop trigger signal 27 is output to an internal signal waveform reproduction section 30, and thus, the information that the write operation to the ring buffer 14 has been stopped is sent to the internal signal waveform reproduction section 30. The internal signal waveform reproduction section 30 provided outside the LSI 11 reads out read information 29 from the ring buffer 14. The read operation can also be performed by using a single serial pin. The internal signal waveform reproduction section 30 reproduces an internal signal waveform based on the read information 29.
Next, a write operation of the flag 28 will be described with reference to FIG. 2. The flag 28 is write information to be written to the ring buffer 14 (having 8 locations) for storing the signal change information of the internal signals of the LSI 11 to be monitored. It is assumed that 4 types of signals are input to the signal change information generating section 13. First, at point [1] where signal A changes from “L” to “H”, other signals B, C, and D do not change. Therefore, the flag 28, which is the write information to be written to the ring buffer 14, is “1” for signal A immediately after a rise, indicating “H”, and “2” for the other signals, indicating that the level has not been changed. Next, at point [2] where signal B changes from “H” to “L”, the flag 28 as the write information to be written to the ring buffer 14 is “0” for signal B immediately after a fall, indicating “L”, and “2” for the other signals, indicating that the level has not been changed. Thereafter, flag information at the signal change points are sequentially written to the ring buffer 14 in a similar manner.
After the flag is written for the final point [8] of the ring buffer 14, at the next change point [9], the flag information at point [9](“1” for signal B, and “2” for the other signals) is written over the leading information of the ring buffer 14. In this example, an address pointer of the ring buffer 14 points to the pointer position in the figure in the state where the flag information up to the state at change point [10] has been written to the ring buffer 14. In the case where the event trigger generating section 15 outputs the write stop trigger signal 27 at this point, the write operation of the flag information 28 to the ring buffer 14 stops. Then, for reading the information of the ring buffer 14 from outside, the output flag information 29 is read in the order of [3], [4], [5], [6], [7], [8], [9], and [10], starting from the pointer. Thus, waveforms of signals A, B, C, and D can be reproduced.
INDUSTRIAL APPLICABILITY
As described above, according to the present invention, it is possible to reduce the number of input/output pins used, regardless of the number of internal control signals to be monitored, and thus to provide an integrated circuit internal signal monitoring apparatus which is capable of simultaneously monitoring a large number of signals. Compared to the prior art, a chip size of the LSI can be smaller. When a system including the LSI is debugged, trigger generation and signal analysis using an external logic analyzer not required. Therefore, a phase relation of the inner control signals around the event trigger generation time can easily be analyzed.

Claims (5)

What is claimed is:
1. An integrated circuit internal signal monitoring apparatus, comprising:
an integrated circuit, comprising:
signal change information generating means for detecting changes in a plurality of internal signals to be monitored in a circuit block, and in response to a level of at least one of the plurality of internal signals changing, and for sequentially generating flags indicating the internal signal whose level has been changed, the post-change level, and that the levels of other internal signals have not been changed,
storage means for sequentially storing the flags generated by the signal change information generating means, and
trigger generating means for generating a write stop trigger signal for stopping a write operation of the flags to the storage means, and
internal signal waveform reproduction means for reading the flags from the storage means in response to the generation of the write stop trigger signal, and reproducing waveforms of the plurality of internal signals.
2. An integrated circuit internal signal monitoring apparatus according to claim 1, wherein the storage means includes a ring buffer, and the flags are sequentially stored in the ring buffer in a time series.
3. An integrated circuit internal signal monitoring apparatus according to claim 1, wherein the trigger generating means generates the write stop trigger signal when a value of one of the plurality of internal signals and an expected value of a signal input from outside the integrated circuit match each other.
4. An integrated circuit internal signal monitoring apparatus according to claim 1, wherein the integrated circuit further comprises a selector for selecting one of the internal signals and inputting the selected internal signal into the trigger generating means for use as a trigger factor in generating the write stop trigger signal.
5. An integrated circuit internal signal monitoring apparatus according to claim 4, wherein the selector selects one of the internal signals in response to an event designation signal input from outside the integrated circuit.
US09/674,018 1999-07-29 1999-07-29 Integrated circuit internal signal monitoring apparatus Expired - Fee Related US6687863B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1999/004103 WO2001013135A1 (en) 1998-01-30 1999-07-29 Internal signal monitor of integrated circuit

Publications (1)

Publication Number Publication Date
US6687863B1 true US6687863B1 (en) 2004-02-03

Family

ID=30658557

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/674,018 Expired - Fee Related US6687863B1 (en) 1999-07-29 1999-07-29 Integrated circuit internal signal monitoring apparatus

Country Status (2)

Country Link
US (1) US6687863B1 (en)
KR (1) KR100400957B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070079188A1 (en) * 2003-05-28 2007-04-05 Veendrick Hendricus J M Signal integrity self-test architecture
US7493434B1 (en) * 2005-05-25 2009-02-17 Dafca, Inc. Determining the value of internal signals in a malfunctioning integrated circuit

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450560A (en) * 1981-10-09 1984-05-22 Teradyne, Inc. Tester for LSI devices and memory devices
JPS61133867A (en) 1984-11-30 1986-06-21 ダイナミック　システムズ　インコーポレーテッド Signal waveform recorder
US4876685A (en) * 1987-06-08 1989-10-24 Teradyne, Inc. Failure information processing in automatic memory tester
US5109505A (en) * 1988-09-29 1992-04-28 Kabushiki Kaisha Toshiba Semiconductor memory disk apparatus with backup device capable of being accessed immediately after power source is recovered
JPH04171542A (en) 1990-11-06 1992-06-18 Nec Corp Microprocessor containing debugging function
JPH0534416A (en) 1991-07-30 1993-02-09 Nec Ibaraki Ltd Semiconductor logic integrated circuit
US5285323A (en) * 1990-10-05 1994-02-08 Digital Equipment Corporation Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
JPH06201787A (en) 1992-07-08 1994-07-22 Sony Tektronix Corp Assigning method for memory of logic analyzer
US5379300A (en) 1991-03-27 1995-01-03 Nec Corporation Test signal output circuit for LSI
US5465257A (en) 1992-03-03 1995-11-07 Nec Corporation Test signal output circuit in LSI
JPH0863374A (en) 1994-08-22 1996-03-08 Toshiba Corp Tracing function incorporated type lsi
US5596530A (en) * 1993-08-31 1997-01-21 Macronix International Co., Ltd. Flash EPROM with block erase flags for over-erase protection

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450560A (en) * 1981-10-09 1984-05-22 Teradyne, Inc. Tester for LSI devices and memory devices
JPS61133867A (en) 1984-11-30 1986-06-21 ダイナミック　システムズ　インコーポレーテッド Signal waveform recorder
US4876685A (en) * 1987-06-08 1989-10-24 Teradyne, Inc. Failure information processing in automatic memory tester
US5109505A (en) * 1988-09-29 1992-04-28 Kabushiki Kaisha Toshiba Semiconductor memory disk apparatus with backup device capable of being accessed immediately after power source is recovered
US5285323A (en) * 1990-10-05 1994-02-08 Digital Equipment Corporation Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
JPH04171542A (en) 1990-11-06 1992-06-18 Nec Corp Microprocessor containing debugging function
US5379300A (en) 1991-03-27 1995-01-03 Nec Corporation Test signal output circuit for LSI
JPH0534416A (en) 1991-07-30 1993-02-09 Nec Ibaraki Ltd Semiconductor logic integrated circuit
US5465257A (en) 1992-03-03 1995-11-07 Nec Corporation Test signal output circuit in LSI
JPH06201787A (en) 1992-07-08 1994-07-22 Sony Tektronix Corp Assigning method for memory of logic analyzer
US5596530A (en) * 1993-08-31 1997-01-21 Macronix International Co., Ltd. Flash EPROM with block erase flags for over-erase protection
JPH0863374A (en) 1994-08-22 1996-03-08 Toshiba Corp Tracing function incorporated type lsi

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070079188A1 (en) * 2003-05-28 2007-04-05 Veendrick Hendricus J M Signal integrity self-test architecture
US7478302B2 (en) * 2003-05-28 2009-01-13 Nxp B.V. Signal integrity self-test architecture
US7493434B1 (en) * 2005-05-25 2009-02-17 Dafca, Inc. Determining the value of internal signals in a malfunctioning integrated circuit

Also Published As

Publication number Publication date
KR20010106495A (en) 2001-11-29
KR100400957B1 (en) 2003-10-10

Similar Documents

Publication Publication Date Title
US5051997A (en) Semiconductor integrated circuit with self-test function
EP0042422B1 (en) Diagnostic circuitry in a data processor
US4611281A (en) Apparatus for analyzing microprocessor operation
KR970004077B1 (en) Method and apparatus for detecting retention faults in memory
US6594788B1 (en) Method of analyzing a relief of failure cell in a memory and memory testing apparatus having a failure relief analyzer using the method
US5291449A (en) IC memory testing apparatus
US20050262401A1 (en) Central processing unit and micro computer
JPH10144095A (en) Defect analyzing memory for semiconductor memory test device
US6711705B1 (en) Method of analyzing a relief of failure cell in a memory and memory testing apparatus having a failure relief analyzer using the method
US6006350A (en) Semiconductor device testing apparatus and method for testing memory and logic sections of a semiconductor device
US6687863B1 (en) Integrated circuit internal signal monitoring apparatus
US20080082874A1 (en) FBM generation device and FBM generation method
JPH11282709A (en) In-circuit emulator
JP4704131B2 (en) Test apparatus and test method
JP2006048767A (en) Semiconductor memory test apparatus
JP3339398B2 (en) Integrated circuit internal signal monitoring device
CN1171094C (en) Internal signal/monitor of integrated circuit
US20060092753A1 (en) Semiconductor device and testing method for semiconductor device
KR100247858B1 (en) Error information storage circuit of memory apparatus
KR100296425B1 (en) Memory fault emulator
US7475300B2 (en) Test circuit and test method
JPH07128372A (en) Signal measuring method
JP2000285698A (en) Memory testing deivce
JPH02276090A (en) Semiconductor memory integrated circuit
JPH10307166A (en) Ic testing device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INOUE, TAKAO;REEL/FRAME:012003/0126

Effective date: 20010115

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20120203