US6743642B2 - Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology - Google Patents
Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology Download PDFInfo
- Publication number
- US6743642B2 US6743642B2 US10/289,488 US28948802A US6743642B2 US 6743642 B2 US6743642 B2 US 6743642B2 US 28948802 A US28948802 A US 28948802A US 6743642 B2 US6743642 B2 US 6743642B2
- Authority
- US
- United States
- Prior art keywords
- barrier layer
- mechanical polishing
- conductor
- chemical mechanical
- rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/26—Thin magnetic films, e.g. of one-domain structure characterised by the substrate or intermediate layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3254—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/14—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates
- H01F41/30—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE]
- H01F41/302—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F41/305—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices applying the spacer or adjusting its interface, e.g. in order to enable particular effect different from exchange coupling
- H01F41/307—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices applying the spacer or adjusting its interface, e.g. in order to enable particular effect different from exchange coupling insulating or semiconductive spacer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
Definitions
- This invention relates generally to the manufacture of magnetoresistive random access memory (MRAM) cells. More particularly, this invention relates to a method of manufacturing such MRAM cells using a bilayer CMP process to improve the interficial roughness between magnetic layers.
- MRAM magnetoresistive random access memory
- Magnetoresisteive random access memory has the advantages of non-volatility, capability of three-dimensional cell packing, low power consumption, simpler and cheaper process compared to conventional DRAM and FLASH memory.
- the architecture for MRAM comprises a plurality or array of memory cells and a plurality of digit and bit line intersections.
- the MRAM cell generally used is composed of a magnetic tunnel junction (MTJ), and isolation transistor, and the intersection of digit and bit lines.
- An interconnect stack connects the isolation transistor to the MTJ device, to the bit line, and to the digit line used to create part of the magnetic field for programming the MRAM cell.
- MRAM uses the relative orientation of the magnetization in ferromagnetic materials to store information.
- Optimal performance of magneto-resistive tunnel junction devices requires smooth tunnel barriers.
- the relative orientation of the magnetization can be corrupted by surface roughness. This corruption of the magnetization is known as “Neel coupling,” and is the remnant magnetism due to the roughness of the interfacial surface as shown in FIG. 1.
- a rough tunnel barrier induces Neel coupling which, in effect creates an offset in the switching field of the magneto-resistive device thereby reducing the operating margin of the device in a memory array.
- CMP chemical mechanical polishing
- barrier refers to the diffusion resistance of this layer to metallic contamination from the wiring conductor. This distinguishes the function of this barrier layer from the device electron tunnel barrier.
- One common material for the barrier layer is tantalum nitride (TaN).
- Other common materials are ruthenium (Ru), tantalum (Ta) and titanium nitride (TiN) implemented as single layers or also in combination to achieve the smooth interfaces to eliminate the deleterious effect of Neel coupling.
- buffer layer used beneath the metal stack is that it must be removed during the device patterning to isolate the devices.
- the problems described above are addressed through use of the present invention, which is directed to a method for fabricating a magnetoresistive random access memory cell, comprising the steps of providing a semiconductor substrate including at least one conductor embedded in a dielectric material, the top surface of the conductor being coplanar with the top surface of the dielectric material, depositing a first material on the conductor and the dielectric material; depositing a second material on the first material, wherein the second material has a polish rate faster than the first material; essentially removing the second material by chemical mechanical polishing; depositing a first magnetic layer stack, a non-magnetic tunnel junction barrier layer, and a second magnetic layer; and patterning the first material, the first magnetic layer stack, the non-magnetic tunnel junction barrier layer, and the second magnetic layer by a lithographic process.
- FIGS. 1 ( a )- 1 ( b ) are schematic cross-sectional views of a partially-fabricated MRAM cell showing the corruption of relative orientation of magnetization caused by interfacial roughness;
- FIGS. 2 ( a )- 2 ( d ) illustrate a prior art method for forming a MRAM cell
- FIGS. 3 ( a )- 3 ( d ) illustrate a method for forming a MRAM cell in accordance with a preferred embodiment of this invention.
- FIG. 1 ( a ) illustrates a partially-fabricated MRAM cell showing the corruption of relative orientation of magnetization caused by interfacial roughness.
- FIG. 1 ( a ) shows a partially-fabricated MRAM cell which includes non-magnetic conductor 2 forming a lower electrode for the MRAM cell, and further includes barrier layer 3 , pinned magnetic layer 4 , non-magnetic tunnel barrier layer 5 , and free magnetic layer 6 .
- the surface of tunnel barrier layer 5 often suffers from interfacial roughness 7 .
- the corruption of magnetization caused by such roughness is known as “Neel coupling,” and results in a Remnant Magnetic moment misaligned to the orientation of the Dominant Magnetic moment, as shown in FIG. 1 ( b ). This Neel coupling in effect creates an offset in the switching field of the magneto-resistive device thereby reducing the operating margin of the device in a memory array.
- FIGS. 2 ( a )- 2 ( e ) A typical manufacturing process for a magnetic tunnel junction metal stack is shown in FIGS. 2 ( a )- 2 ( e ).
- FIG. 2 ( a ) shows a partially-fabricated metal stack in which dielectric layer 10 is patterned and etched to form trenches, the trenches are lined with liner material 11 , and then conductive material 12 is deposited.
- Conductive material 12 is typically copper, and liner material II may be TaN.
- FIG. 2 ( b ) shows the partially-fabricated metal stack after excess conductive material 12 and liner material 11 are removed by CMP polishing.
- barrier layer 13 is blanket deposited on dielectric material 10 and conductors 12 .
- Barrier layer 13 is typically TaN, and is typically about 500 ⁇ thick as deposited.
- Barrier layer 13 is then smoothed by CMP to provide a smooth surface for magnetoresistive metal stack deposition.
- CMP chemical vapor deposition
- non-uniform polish rates often result in thickness variation in the remaining barrier layer 13 , as shown in FIG. 2 ( d ).
- barrier layer 13 is subsequently etched, some portions of barrier layer 13 may be underetched resulting in shorts between conductors, while other portions of barrier layer 13 may be overetched resulting in destruction of the underlying dielectric layer 10 .
- FIG. 2 ( e ) shows the partially-fabricated metal stack after barrier layer 13 is etched, the remaining metal stack layers (collectively shown as layer 15 ) are deposited, and metal mask 16 is used to etch barrier layer 13 and the additional metal stack layers 15 in areas exposed by mask 16 using a lithographic process.
- barrier layer 13 In area a of the partially-fabricated metal stack shown in FIG. 2 ( e ), barrier layer 13 is too thick following CMP and is therefore incompletely etched, leaving barrier material 13 a which will cause shorts between conductors.
- barrier layer 13 is too thin following CMP and is therefore overetched, resulting in removal of dielectric material 10 from between the conductors.
- roughness in the surface of polished conductor 12 may be translated to the interface between the tunnel barrier layer and the magnetic layers, resulting in the interfacial roughness 7 shown in FIG. 1 .
- FIGS. 3 ( a )- 3 ( d ) One embodiment of the method is shown in FIGS. 3 ( a )- 3 ( d ).
- conductors 112 have been formed in dielectric material 110 .
- a liner 111 is typically disposed between conductors 112 and dielectric material 110 .
- a first barrier layer 113 is blanket deposited, and then a second barrier layer 114 is blanket deposited over first barrier layer 113 .
- First barrier layer 113 is preferably formed of a material different from second barrier layer 114 . More preferably, first barrier layer 113 has a significantly slower polish rate than second barrier layer 114 resulting in a polish selectivity with respect to first barrier layer 113 . In other words, first barrier layer 113 preferably has a polish rate of about 200 to 300 angstroms/min., and second barrier layer 114 preferably has a polish rate of about 800 to 1200 angstroms/min., resulting in a polish selectivity of about 1:4.
- first barrier layer 113 should also be selected such that a very smooth surface is obtained upon polishing.
- first barrier layer 113 is TaN
- second barrier layer 114 is Ta.
- first barrier layer 113 may be TiN deposited by chemical vapor deposition (CVD)
- second barrier layer 114 may be TiN deposited by physical vapor deposition (PVD).
- polish pads IC1000TM on SubalVTM, or IC1000TM on IC1000TM K-grooved may be used with a commercially available silica abrasive slurry.
- second barrier layer 114 is essentially removed by polishing using CMP, exposing first barrier layer 113 and creating a very smooth surface on first barrier layer 113 . It is preferable to remove completely the second barrier layer 114 while leaving at least a portion of the first barrier layer 113 .
- metal stack layers 115 are deposited on barrier layer 113 , and metal stack layers 115 and barrier layer 113 are removed by etching in areas exposed by metal mask 116 using a lithography process.
- barrier layer 113 is polished uniformly, there are no areas where barrier layer 113 is underetched thereby causing shorts between conductors 112 , and there are no areas where barrier layer 113 is overetched thereby removing too much dielectric material 110 . Moreover, because barrier layer 113 is polished to a very smooth finish, interfacial roughness is not present at the interface between the tunnel barrier layer and the magnetic layers in metal stack 115 , thereby eliminating the Neel coupling problem discussed above.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
Abstract
Description
Claims (10)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/289,488 US6743642B2 (en) | 2002-11-06 | 2002-11-06 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology |
TW092130147A TWI231562B (en) | 2002-11-06 | 2003-10-29 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology |
CNA2003801028273A CN1729538A (en) | 2002-11-06 | 2003-11-05 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology |
PCT/EP2003/012353 WO2004042735A1 (en) | 2002-11-06 | 2003-11-05 | Bilayer cmp process to improve surface roughness of magnetic stack in mram technology |
EP03810441A EP1559107B1 (en) | 2002-11-06 | 2003-11-05 | Bilayer cmp process to improve surface roughness of magnetic stack in mram technology |
KR1020057008075A KR100694566B1 (en) | 2002-11-06 | 2003-11-05 | Bilayer cmp process to improve surface roughness of magnetic stack in mram technology |
DE60311131T DE60311131T2 (en) | 2002-11-06 | 2003-11-05 | TWO-LAYER CMP PROCESS TO IMPROVE SURFACE RETENTION OF A MAGNETIC STACK IN MRAM TECHNOLOGY |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/289,488 US6743642B2 (en) | 2002-11-06 | 2002-11-06 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040087038A1 US20040087038A1 (en) | 2004-05-06 |
US6743642B2 true US6743642B2 (en) | 2004-06-01 |
Family
ID=32176075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/289,488 Expired - Fee Related US6743642B2 (en) | 2002-11-06 | 2002-11-06 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology |
Country Status (7)
Country | Link |
---|---|
US (1) | US6743642B2 (en) |
EP (1) | EP1559107B1 (en) |
KR (1) | KR100694566B1 (en) |
CN (1) | CN1729538A (en) |
DE (1) | DE60311131T2 (en) |
TW (1) | TWI231562B (en) |
WO (1) | WO2004042735A1 (en) |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060292815A1 (en) * | 2005-06-28 | 2006-12-28 | Roberts Douglas R | MIM capacitor in a semiconductor device and method therefor |
US20070201265A1 (en) * | 2006-02-25 | 2007-08-30 | Rajiv Yadav Ranjan | High capacity low cost multi-state magnetic memory |
US20070253245A1 (en) * | 2006-04-27 | 2007-11-01 | Yadav Technology | High Capacity Low Cost Multi-Stacked Cross-Line Magnetic Memory |
US7296339B1 (en) | 2004-09-08 | 2007-11-20 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording head |
US20080094886A1 (en) * | 2006-10-20 | 2008-04-24 | Rajiv Yadav Ranjan | Non-uniform switching based non-volatile magnetic based memory |
US20080164548A1 (en) * | 2006-02-25 | 2008-07-10 | Yadav Technology | Low resistance high-tmr magnetic tunnel junction and process for fabrication thereof |
US20080180991A1 (en) * | 2006-11-01 | 2008-07-31 | Yadav Technology | Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM) |
US20080191295A1 (en) * | 2007-02-12 | 2008-08-14 | Yadav Technology | Non-Volatile Magnetic Memory Element with Graded Layer |
US20080225585A1 (en) * | 2007-02-12 | 2008-09-18 | Yadav Technology | Low Cost Multi-State Magnetic Memory |
US20080246104A1 (en) * | 2007-02-12 | 2008-10-09 | Yadav Technology | High Capacity Low Cost Multi-State Magnetic Memory |
US20080293165A1 (en) * | 2006-02-25 | 2008-11-27 | Yadav Technology, Inc. | Method for manufacturing non-volatile magnetic memory |
US7508627B1 (en) | 2006-03-03 | 2009-03-24 | Western Digital (Fremont), Llc | Method and system for providing perpendicular magnetic recording transducers |
US20090154229A1 (en) * | 2006-02-25 | 2009-06-18 | Yadav Technology Inc. | Sensing and writing to magnetic random access memory (mram) |
US7552523B1 (en) | 2005-07-01 | 2009-06-30 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording transducer |
US8015692B1 (en) | 2007-11-07 | 2011-09-13 | Western Digital (Fremont), Llc | Method for providing a perpendicular magnetic recording (PMR) head |
US8141235B1 (en) | 2006-06-09 | 2012-03-27 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording transducers |
US8183652B2 (en) | 2007-02-12 | 2012-05-22 | Avalanche Technology, Inc. | Non-volatile magnetic memory with low switching current and high thermal stability |
US8333008B1 (en) | 2005-07-29 | 2012-12-18 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording transducer |
US8486285B2 (en) | 2009-08-20 | 2013-07-16 | Western Digital (Fremont), Llc | Damascene write poles produced via full film plating |
US8802451B2 (en) | 2008-02-29 | 2014-08-12 | Avalanche Technology Inc. | Method for manufacturing high density non-volatile magnetic memory |
US9099118B1 (en) | 2009-05-26 | 2015-08-04 | Western Digital (Fremont), Llc | Dual damascene process for producing a PMR write pole |
US20170062699A1 (en) * | 2015-08-31 | 2017-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetoresistive Random Access Memory Cell and Fabricating the Same |
US10256190B2 (en) | 2017-01-20 | 2019-04-09 | Samsung Electronics Co., Ltd. | Variable resistance memory devices |
US10937828B2 (en) | 2018-10-11 | 2021-03-02 | International Business Machines Corporation | Fabricating embedded magnetoresistive random access memory device with v-shaped magnetic tunnel junction profile |
US11223008B2 (en) | 2019-11-27 | 2022-01-11 | International Business Machines Corporation | Pillar-based memory hardmask smoothing and stress reduction |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1677095A1 (en) | 2003-09-26 | 2006-07-05 | The Kitasato Gakuen Foundation | Variable-wavelength light generator and light interference tomograph |
US20050073878A1 (en) * | 2003-10-03 | 2005-04-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-sensing level MRAM structure with different magnetoresistance ratios |
KR100829361B1 (en) * | 2006-12-26 | 2008-05-13 | 동부일렉트로닉스 주식회사 | Method for fabricating mram |
US9034491B2 (en) * | 2012-11-30 | 2015-05-19 | Seagate Technology Llc | Low resistance area magnetic stack |
US8947834B2 (en) * | 2013-03-12 | 2015-02-03 | Seagate Technology Llc | Method and apparatus for chemical-mechanical polishing |
US10586914B2 (en) * | 2016-10-14 | 2020-03-10 | Applied Materials, Inc. | Method of forming ultra-smooth bottom electrode surface for depositing magnetic tunnel junctions |
CN109216541B (en) * | 2017-06-30 | 2022-05-17 | 中电海康集团有限公司 | MRAM and manufacturing method thereof |
CN111697131B (en) * | 2019-03-11 | 2023-04-07 | 中电海康集团有限公司 | MRAM preparation method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5496759A (en) | 1994-12-29 | 1996-03-05 | Honeywell Inc. | Highly producible magnetoresistive RAM process |
US5702831A (en) | 1995-11-06 | 1997-12-30 | Motorola | Ferromagnetic GMR material |
US6004188A (en) | 1998-09-10 | 1999-12-21 | Chartered Semiconductor Manufacturing Ltd. | Method for forming copper damascene structures by using a dual CMP barrier layer |
US6205052B1 (en) | 1999-10-21 | 2001-03-20 | Motorola, Inc. | Magnetic element with improved field response and fabricating method thereof |
US6217416B1 (en) | 1998-06-26 | 2001-04-17 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper/tantalum substrates |
US6365419B1 (en) | 2000-08-28 | 2002-04-02 | Motorola, Inc. | High density MRAM cell array |
US6677631B1 (en) * | 2002-08-27 | 2004-01-13 | Micron Technology, Inc. | MRAM memory elements and method for manufacture of MRAM memory elements |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10043159A1 (en) * | 2000-09-01 | 2002-03-21 | Infineon Technologies Ag | Memory cell arrangement and method for its production |
US20020098705A1 (en) * | 2001-01-24 | 2002-07-25 | Infineon Technologies North America Corp. | Single step chemical mechanical polish process to improve the surface roughness in MRAM technology |
-
2002
- 2002-11-06 US US10/289,488 patent/US6743642B2/en not_active Expired - Fee Related
-
2003
- 2003-10-29 TW TW092130147A patent/TWI231562B/en not_active IP Right Cessation
- 2003-11-05 KR KR1020057008075A patent/KR100694566B1/en not_active IP Right Cessation
- 2003-11-05 EP EP03810441A patent/EP1559107B1/en not_active Expired - Fee Related
- 2003-11-05 WO PCT/EP2003/012353 patent/WO2004042735A1/en active IP Right Grant
- 2003-11-05 DE DE60311131T patent/DE60311131T2/en not_active Expired - Fee Related
- 2003-11-05 CN CNA2003801028273A patent/CN1729538A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5496759A (en) | 1994-12-29 | 1996-03-05 | Honeywell Inc. | Highly producible magnetoresistive RAM process |
US5702831A (en) | 1995-11-06 | 1997-12-30 | Motorola | Ferromagnetic GMR material |
US6217416B1 (en) | 1998-06-26 | 2001-04-17 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper/tantalum substrates |
US6004188A (en) | 1998-09-10 | 1999-12-21 | Chartered Semiconductor Manufacturing Ltd. | Method for forming copper damascene structures by using a dual CMP barrier layer |
US6205052B1 (en) | 1999-10-21 | 2001-03-20 | Motorola, Inc. | Magnetic element with improved field response and fabricating method thereof |
US6365419B1 (en) | 2000-08-28 | 2002-04-02 | Motorola, Inc. | High density MRAM cell array |
US6677631B1 (en) * | 2002-08-27 | 2004-01-13 | Micron Technology, Inc. | MRAM memory elements and method for manufacture of MRAM memory elements |
Cited By (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8149536B1 (en) | 2004-09-08 | 2012-04-03 | Western Digital (Fremont), Llc | Perpendicular magnetic recording head having a pole tip formed with a CMP uniformity structure |
US7296339B1 (en) | 2004-09-08 | 2007-11-20 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording head |
US20060292815A1 (en) * | 2005-06-28 | 2006-12-28 | Roberts Douglas R | MIM capacitor in a semiconductor device and method therefor |
US7375002B2 (en) | 2005-06-28 | 2008-05-20 | Freescale Semiconductor, Inc. | MIM capacitor in a semiconductor device and method therefor |
US7552523B1 (en) | 2005-07-01 | 2009-06-30 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording transducer |
US8333008B1 (en) | 2005-07-29 | 2012-12-18 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording transducer |
US20080164548A1 (en) * | 2006-02-25 | 2008-07-10 | Yadav Technology | Low resistance high-tmr magnetic tunnel junction and process for fabrication thereof |
US8535952B2 (en) | 2006-02-25 | 2013-09-17 | Avalanche Technology, Inc. | Method for manufacturing non-volatile magnetic memory |
US8363457B2 (en) | 2006-02-25 | 2013-01-29 | Avalanche Technology, Inc. | Magnetic memory sensing circuit |
US20070201265A1 (en) * | 2006-02-25 | 2007-08-30 | Rajiv Yadav Ranjan | High capacity low cost multi-state magnetic memory |
US8508984B2 (en) | 2006-02-25 | 2013-08-13 | Avalanche Technology, Inc. | Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof |
US20080293165A1 (en) * | 2006-02-25 | 2008-11-27 | Yadav Technology, Inc. | Method for manufacturing non-volatile magnetic memory |
US8058696B2 (en) | 2006-02-25 | 2011-11-15 | Avalanche Technology, Inc. | High capacity low cost multi-state magnetic memory |
US20090154229A1 (en) * | 2006-02-25 | 2009-06-18 | Yadav Technology Inc. | Sensing and writing to magnetic random access memory (mram) |
US7508627B1 (en) | 2006-03-03 | 2009-03-24 | Western Digital (Fremont), Llc | Method and system for providing perpendicular magnetic recording transducers |
US20070253245A1 (en) * | 2006-04-27 | 2007-11-01 | Yadav Technology | High Capacity Low Cost Multi-Stacked Cross-Line Magnetic Memory |
US8141235B1 (en) | 2006-06-09 | 2012-03-27 | Western Digital (Fremont), Llc | Method for manufacturing a perpendicular magnetic recording transducers |
US8468682B1 (en) | 2006-06-09 | 2013-06-25 | Western Digital (Fremont), Llc | Method for manufacturing perpendicular magnetic recording transducers |
US8861134B1 (en) | 2006-06-09 | 2014-10-14 | Western Digital (Fremont), Llc | Method and system for providing perpendicular magnetic recording transducers utilizing a damascene approach |
US8084835B2 (en) | 2006-10-20 | 2011-12-27 | Avalanche Technology, Inc. | Non-uniform switching based non-volatile magnetic based memory |
US20080094886A1 (en) * | 2006-10-20 | 2008-04-24 | Rajiv Yadav Ranjan | Non-uniform switching based non-volatile magnetic based memory |
US7732881B2 (en) | 2006-11-01 | 2010-06-08 | Avalanche Technology, Inc. | Current-confined effect of magnetic nano-current-channel (NCC) for magnetic random access memory (MRAM) |
US20080180991A1 (en) * | 2006-11-01 | 2008-07-31 | Yadav Technology | Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM) |
US8183652B2 (en) | 2007-02-12 | 2012-05-22 | Avalanche Technology, Inc. | Non-volatile magnetic memory with low switching current and high thermal stability |
US20080246104A1 (en) * | 2007-02-12 | 2008-10-09 | Yadav Technology | High Capacity Low Cost Multi-State Magnetic Memory |
US20080225585A1 (en) * | 2007-02-12 | 2008-09-18 | Yadav Technology | Low Cost Multi-State Magnetic Memory |
US20080191295A1 (en) * | 2007-02-12 | 2008-08-14 | Yadav Technology | Non-Volatile Magnetic Memory Element with Graded Layer |
US8015692B1 (en) | 2007-11-07 | 2011-09-13 | Western Digital (Fremont), Llc | Method for providing a perpendicular magnetic recording (PMR) head |
US8802451B2 (en) | 2008-02-29 | 2014-08-12 | Avalanche Technology Inc. | Method for manufacturing high density non-volatile magnetic memory |
US9099118B1 (en) | 2009-05-26 | 2015-08-04 | Western Digital (Fremont), Llc | Dual damascene process for producing a PMR write pole |
US8486285B2 (en) | 2009-08-20 | 2013-07-16 | Western Digital (Fremont), Llc | Damascene write poles produced via full film plating |
US20170062699A1 (en) * | 2015-08-31 | 2017-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetoresistive Random Access Memory Cell and Fabricating the Same |
US9685604B2 (en) * | 2015-08-31 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetoresistive random access memory cell and fabricating the same |
US10256190B2 (en) | 2017-01-20 | 2019-04-09 | Samsung Electronics Co., Ltd. | Variable resistance memory devices |
US10937828B2 (en) | 2018-10-11 | 2021-03-02 | International Business Machines Corporation | Fabricating embedded magnetoresistive random access memory device with v-shaped magnetic tunnel junction profile |
US11223008B2 (en) | 2019-11-27 | 2022-01-11 | International Business Machines Corporation | Pillar-based memory hardmask smoothing and stress reduction |
US11812668B2 (en) | 2019-11-27 | 2023-11-07 | International Business Machines Corporation | Pillar-based memory hardmask smoothing and stress reduction |
Also Published As
Publication number | Publication date |
---|---|
KR20050088997A (en) | 2005-09-07 |
EP1559107A1 (en) | 2005-08-03 |
DE60311131D1 (en) | 2007-02-22 |
CN1729538A (en) | 2006-02-01 |
DE60311131T2 (en) | 2007-10-18 |
TW200414400A (en) | 2004-08-01 |
EP1559107B1 (en) | 2007-01-10 |
KR100694566B1 (en) | 2007-03-13 |
TWI231562B (en) | 2005-04-21 |
WO2004042735A1 (en) | 2004-05-21 |
US20040087038A1 (en) | 2004-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6743642B2 (en) | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology | |
US6709874B2 (en) | Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation | |
TWI282162B (en) | Magnetic yoke structures in MRAM devices to reduce programming power consumption and a method to make the same | |
TW536736B (en) | Metal hard mask for ILD RIE in damascene structures | |
US8754433B2 (en) | Semiconductor device and method of manufacturing the same | |
US20220302209A1 (en) | Method of forming memory cell | |
US20030224260A1 (en) | Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs | |
US11335729B2 (en) | Semiconductor memory device | |
WO2004023551A1 (en) | Mram mtj stack to conductive line alignment method | |
US7241668B2 (en) | Planar magnetic tunnel junction substrate having recessed alignment marks | |
US20200220072A1 (en) | Magnetic tunnel junction (mtj) bilayer hard mask to prevent redeposition | |
US6680500B1 (en) | Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers | |
US11482666B2 (en) | Method for fabricating a semiconductor device | |
US20020098705A1 (en) | Single step chemical mechanical polish process to improve the surface roughness in MRAM technology | |
US6913990B2 (en) | Method of forming isolation dummy fill structures | |
US7129173B2 (en) | Process for producing and removing a mask layer | |
US6846683B2 (en) | Method of forming surface-smoothing layer for semiconductor devices with magnetic material layers | |
US11844285B2 (en) | Magnetic tunnel junction memory cell with a buffer-layer and methods for forming the same | |
WO2022011878A1 (en) | Memory bit preparation method and mram preparation method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP., CALIFOR Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LOW, KIA-SENG;REEL/FRAME:013474/0074 Effective date: 20021030 Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:COSTRINI, GREGORY;HUMMEL, JOHN;KRISHNAN, MAHADEVAIYER;REEL/FRAME:013474/0069;SIGNING DATES FROM 20021030 TO 20021101 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;REEL/FRAME:014030/0269 Effective date: 20031007 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023853/0401 Effective date: 20060425 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160601 |