US6770912B2 - Semiconductor device and method for producing the same - Google Patents
Semiconductor device and method for producing the same Download PDFInfo
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- US6770912B2 US6770912B2 US10/079,951 US7995102A US6770912B2 US 6770912 B2 US6770912 B2 US 6770912B2 US 7995102 A US7995102 A US 7995102A US 6770912 B2 US6770912 B2 US 6770912B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title description 28
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 50
- 239000012535 impurity Substances 0.000 claims description 32
- 230000005669 field effect Effects 0.000 claims description 30
- 230000003247 decreasing effect Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 abstract description 24
- 239000000758 substrate Substances 0.000 abstract description 18
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 82
- 229910010271 silicon carbide Inorganic materials 0.000 description 82
- 239000013078 crystal Substances 0.000 description 34
- 238000000034 method Methods 0.000 description 25
- 238000010276 construction Methods 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 108010053481 Antifreeze Proteins Proteins 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a semiconductor device in which an ohmic electrode is formed on a substrate made of silicon carbide with a large bandgap, and a method for producing the same.
- SiC silicon carbide
- FIG. 6 is a cross-sectional view showing a configuration of a field-effect transistor that is one of the conventional SiC semiconductor devices.
- FIGS. 12A to 12 D are cross-sectional views illustrating the processes of a method for producing the field-effect transistor.
- a SiC member 62 doped with an impurity in a low concentration, and a SiC member 63 doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 61 by crystal growth.
- FIG. 12A a SiC member 62 doped with an impurity in a low concentration, and a SiC member 63 doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 61 by crystal growth.
- FIG. 12A a SiC member 62 doped with an impurity in a low concentration, and a SiC member 63 doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 61 by crystal growth.
- a part of the SiC member 63 that is the uppermost member is removed to expose the SiC member 62 .
- ohmic electrodes 68 are formed on the SiC member 63 , and a heat treatment is conducted at a high temperature, whereby an ohmic contact is obtained.
- the ohmic electrodes 68 will function as a drain electrode and a source electrode.
- a gate electrode 69 is formed on the SiC member 62 to obtain a Schottky contact.
- a SiC field-effect transistor with a conventional construction as shown in FIG. 6 is completed.
- a part of the SiC member 63 may be removed after the ohmic electrodes 68 are formed.
- An ohmic contact generally is obtained by inserting the SiC substrate 61 into a heating coil of a high-frequency heating furnace, and conducting a heat treatment at a high temperature of about 1000° C. to 1600° C. This method is disclosed by, for example, C. Arnodo et al., “Nickel and Molybdenum Ohmic Contacts on Silicon Carbide”, Institute of Physics Conference Series Number 142, pp. 577-580, 1996 and the like.
- a heat-treatment temperature is much higher than heat-resistant temperatures of conventional semiconductor materials such as Si and GaAs, and the resistance of an ohmic contact thus obtained also is high.
- a metal material for an ohmic electrode needs to have a melting point higher than the heat-treatment temperature, so that the selection is limited to refractory metals and the like.
- this heat-treatment temperature is close to a growth temperature of SiC crystal and an annealing temperature for activation conducted after ion implantation. This may degrade the crystal structure and cause an impurity to diffuse again.
- the conventional method also has various problems.
- the conventional method requires a special apparatus such as a high-frequency heating furnace for conducting a heat treatment at a high temperature, complicated management of a temperature and an atmospheric gas, safety management with respect to a high temperature, and the like. These problems hinder the practical use and mass-production of a SiC semiconductor device.
- an object of the present invention to provide a construction in which an ohmic electrode with a low resistance is formed on a SiC substrate without conducting a heat treatment at a high temperature, and a method for producing the same.
- the semiconductor device of the present invention includes a SiC substrate and an ohmic electrode, wherein a semiconductor member including a SiC member and a SiGe member is formed between the SiC substrate and the ohmic electrode.
- the semiconductor member may be composed of a SiGe member formed on a SiC member, and the ohmic electrode may be formed on the SiGe member.
- the semiconductor member may be composed of a Si member formed on a SiC member and a SiGe member formed on the Si member, and the ohmic electrode may be formed on the SiGe member.
- the semiconductor member may be composed of a semiconductor member in which a mole fraction is varied continuously from SiC to Si and from Si to SiGe, and the ohmic electrode may be formed on the semiconductor member.
- the semiconductor member may be composed of a semiconductor member in which a C mole fraction is decreased while a Ge mole fraction is increased continuously from SiC to SiGe, and the ohmic electrode is formed on the semiconductor member.
- the semiconductor member may be formed on both a p-type region and an n-type region.
- a gate electrode may be formed on the SiC member.
- the gate electrode may be formed on a Si oxide film.
- the method for producing a semiconductor device of the present invention includes: forming a semiconductor member including a SiC member and a SiGe member on a SiC substrate by crystal growth; and forming an ohmic electrode on the semiconductor member.
- the process of forming the semiconductor member by crystal growth may include forming a SiGe member on a SiC member by crystal growth.
- the process of forming the semiconductor member by crystal growth may include forming a Si member on a SiC member by crystal growth; and forming a SiGe member on the Si member by crystal growth.
- the process of forming the semiconductor member by crystal growth may include forming a semiconductor member, in which a mole fraction is varied continuously from SiC to Si and from Si to SiGe, on a SiC member by crystal growth.
- the process of forming the semiconductor member by crystal growth may include forming a semiconductor member, in which a C mole fraction is decreased while a Ge mole fraction is increased continuously from SiC to SiGe, on a SiC member by crystal growth.
- the semiconductor member may be formed on both a p-type region and an n-type region by crystal growth.
- the method for producing a semiconductor device of the present invention may include forming a gate electrode on the SiC member.
- the gate electrode may be formed on a Si oxide film.
- an ohmic electrode is formed on SiGe with a small bandgap. Therefore, a heat treatment for obtaining an ohmic contact may be conducted at a very low temperature, or such a heat treatment is not required if the impurity concentration of SiGe is high enough.
- the ohmic metal can be selected from various materials, which are suitable for other fabrication processes. Needless to say, even with polysilicon in a high concentration introduced into conventional technology as wiring, an ohmic contact can be formed. Furthermore, an intrinsic semiconductor portion is not degraded due to thermal hysteresis in the course of formation of an ohmic contact, so that stable device characteristics are achieved.
- FIG. 1 is a cross-sectional view showing a configuration of a field-effect transistor of Embodiment 1 according to the present invention.
- FIG. 2 is a cross-sectional view showing a configuration of a field-effect transistor of Embodiment 2 according to the present invention.
- FIG. 3 is a cross-sectional view showing a configuration of a field-effect transistor of Embodiment 3 according to the present invention.
- FIG. 4 is a cross-sectional view showing a configuration of a field-effect transistor of Embodiment 4 according to the present invention.
- FIG. 5 is a cross-sectional view showing a configuration of a field-effect transistor in which a part of Embodiment 1 according to the present invention is modified.
- FIG. 6 is a cross-sectional view showing a configuration of a field-effect transistor with a conventional construction.
- FIGS. 7A to 7 D are cross-sectional views illustrating the processes of a method for producing a field-effect transistor of Embodiment 1 according to the present invention.
- FIGS. 8A to 8 E are cross-sectional views illustrating the processes of a method for producing a field-effect transistor of Embodiment 2 according to the present invention.
- FIGS. 9A to 9 D are cross-sectional views illustrating the processes of a method for producing a field-effect transistor of Embodiment 3 according to the present invention.
- FIGS. 10A to 10 D are cross-sectional views illustrating the processes of a method for producing a field-effect transistor of Embodiment 4 according to the present invention.
- FIGS. 11A to 11 E are cross-sectional views illustrating the processes of a method for producing a field-effect transistor in which a part of Embodiment 1 according to the present invention is modified.
- FIGS. 12A to 12 D are cross-sectional views illustrating the processes of a method for producing a field-effect transistor with a conventional construction.
- FIGS. 13A to 13 D are schematic views of semiconductor/metal band diagrams when an ohmic contact is formed on an n-type semiconductor.
- FIGS. 14A to 14 D are schematic views of semiconductor/metal band diagrams when an ohmic contact is formed on a p-type semiconductor.
- FIG. 1 is a cross-sectional view showing a configuration of a SiC field-effect transistor with a first construction of the present invention.
- FIGS. 7A to 7 D are cross-sectional views illustrating the processes of a method for producing the SiC field-effect transistor.
- a SiC member 12 doped with an impurity in a low concentration and a SiGe member 15 doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 11 by crystal growth.
- a part of the SiGe member 15 that is the uppermost member is removed to expose the SiC member 12 .
- ohmic electrodes 18 are formed on the SiGe member 15 , and a heat treatment is conducted at a low temperature of about 300° C. to obtain an ohmic contact.
- the ohmic electrodes 18 will function as a drain electrode and a source electrode.
- a gate electrode 19 is formed on the SiC member 12 to obtain a Schottky contact.
- FIG. 7D is the same as FIG. 1 .
- FIG. 2 is a cross-sectional view showing a configuration of a SiC field-effect transistor with a second construction of the present invention.
- FIGS. 8A to 8 E are cross-sectional views illustrating the processes of a method for producing the SiC field-effect transistor.
- a SiC member 22 doped with an impurity in a low concentration, and a Si member 24 and a SiGe member 25 that are doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 21 by crystal growth.
- a part of the SiGe member 25 that is the uppermost member is removed to expose the Si member 24 .
- a part of the exposed Si member 24 is heat-treated at a high temperature of about 800° C. to 1000° C., whereby a gate oxide film 26 is formed.
- FIG. 8A a SiC member 22 doped with an impurity in a low concentration
- a Si member 24 and a SiGe member 25 that are doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 21 by crystal growth.
- a part of the SiGe member 25 that is the uppermost member is removed to expose the Si member 24 .
- a part of the exposed Si member 24 is heat-treated at a high temperature of
- ohmic electrodes 28 are formed on the SiGe member 25 , and a heat treatment is conducted at a low temperature of about 300° C. to obtain an ohmic contact. Furthermore, as shown in FIG. 8E, a gate electrode 29 is formed on the gate oxide film 26 to obtain a MOS gate.
- FIG. 8E is the same as FIG. 2 .
- FIG. 3 is a cross-sectional view showing a configuration of a SiC field-effect transistor with a third construction of the present invention.
- FIGS. 9A to 9 D are cross-sectional views illustrating the processes of a method for producing the SiC field-effect transistor.
- a SiC member 32 doped with an impurity in a low concentration and a SiC/Si/SiGe mixed crystal member 35 doped with an impurity in a high concentration are formed on the upper surface of a SiC substrate 31 by crystal growth.
- the mixed crystal member 35 is formed in such a manner that a C mole fraction is decreased continuously from SiC to Si from the substrate side and a Ge mole fraction is increased continuously from Si to SiGe.
- FIG. 9B a part of the mixed crystal member 35 that is the uppermost member is removed to expose the SiC member 32 . Thereafter, as shown in FIG.
- ohmic electrodes 38 are formed on the mixed crystal member 35 , and a heat treatment is conducted at a low temperature of about 300° C. to obtain an ohmic contact. Furthermore, as shown in FIG. 9D, a gate electrode 39 is formed on the SiC member 32 to obtain a Schottky contact. FIG. 9D is the same as FIG. 3 .
- FIG. 4 is a cross-sectional view showing a configuration of a SiC field-effect transistor with a fourth construction of the present invention.
- FIGS. 10A to 10 D are cross-sectional views illustrating the processes of a method for producing the SiC field-effect transistor.
- a SiC member 42 doped with an impurity in a low concentration and a SiC—SiGe mixed crystal member 45 doped with an impurity in a high concentration are formed on the upper surface of the SiC substrate 41 by crystal growth.
- the mixed crystal member 45 is composed of a member formed by decreasing a C mole fraction while increasing a Ge mole fraction continuously from SiC to SiGe from the substrate side.
- a part of the mixed crystal member 45 that is the uppermost member is removed to expose the SiC member 42 .
- ohmic electrodes 48 are formed on the mixed crystal member 45 , and a heat treatment is conducted at a low temperature of about 300° C. to obtain an ohmic contact.
- a gate electrode 49 is formed on the SiC member 42 to obtain a Schottky contact.
- FIG. 10D is the same as FIG. 4 .
- FIG. 5 is a cross-sectional view showing a configuration of a SiC field-effect transistor in which a part of the first construction of the present invention is modified.
- FIGS. 11A to 11 E are cross-sectional views illustrating the processes of a method for producing the SiC field-effect transistor.
- a SiC member 52 doped with an impurity in a low concentration is formed on the upper surface of a SiC substrate 51 by crystal growth.
- an impurity with a conductivity opposite to that of the SiC member 52 is implanted from the surface side by ion implantation to form an impurity-buried region 57 .
- the resultant stack is heat-treated at about 1000° C. to activate the impurity-buried region 57 .
- FIG. 11A a SiC member 52 doped with an impurity in a low concentration
- a part of the SiC member 52 on the impurity-buried region 57 is removed to expose the impurity-buried region 57 .
- a SiGe member 55 doped with an impurity in a high concentration is formed on the SiC member 52 and the exposed impurity-buried region 57 by crystal growth.
- a pn-junction is provided on the impurity-buried region 57 ; however, SiGe has a very narrow bangap with respect to SiC, so that the difference in conductivity is substantially negligible. If it is desired to improve a resistivity, it only is necessary to allow an impurity with the same conductivity to diffuse again into a part of the SiGe member 55 on the impurity-buried region 57 .
- FIG. 11C a part of the SiGe member 55 that is the uppermost member is removed to expose the SiC member 52 .
- ohmic electrodes 58 are formed on the SiGe member 55 , and a heat treatment is conducted at a low temperature of about 300° C. to obtain an ohmic contact.
- a gate electrode 59 is formed on the SiC member 52 to obtain a Schottky contact.
- FIG. 11E is the same as FIG. 5 .
- an ohmic electrode is formed by heat treatment at about 300° C. However, it is possible to increase the temperature of the heat treatment up to about 500° C.
- FIGS. 13A to 13 D are band diagrams showing a junction between an n-type semiconductor and metal
- FIGS. 14A to 14 D are band diagrams showing a junction between a p-type semiconductor and metal.
- FIG. 13A shows a junction between n-type SiC (n-SiC) and metal.
- n-SiC n-type SiC
- metal metal
- FIG. 13B showing the first construction of the present invention
- a semiconductor with a very small bandgap such as SiGe
- a Schottky barrier can be lowered.
- a semiconductor with a small bandgap is doped with an impurity in a high concentration, the semiconductor almost is metallized. Therefore, even if the semiconductor is brought into contact with metal at room temperature, an ohmic contact is formed therebetween, which makes it possible to form a so-called non-alloy contact.
- FIG. 13C shows the second construction of the present invention, in which Si is interposed between SiC and SiGe.
- This shows a more practical construction.
- the present crystal growth technique it is found that more satisfactory crystal is likely to be obtained in the case where Si is formed from SiC and SiGe is formed from Si, compared with the case where SiGe is grown abruptly from SiC.
- This mainly is ascribed to the lattice constant difference, the substrate temperature, the kind of a gas to be used, and the like.
- SiC itself is oxidized, C remains on an interface, which makes it difficult to obtain a satisfactory MOS structure. In the present construction, this problem also is overcome.
- FIG. 13D shows the fourth construction of the present invention, in which a C mole fraction is decreased successively from a SiC interface while a Ge mole fraction is increased successively, whereby a bandgap is varied continuously.
- this crystal growth technique is most difficult, it is most excellent in electrical continuity.
- crystal growth is conducted more easily, in which a C mole fraction is decreased successively from SiC to form Si, and a Ge mole fraction increased successively in Si to obtain SiGe. This method also is excellent in electrical continuity.
- FIGS. 14B to 14 D show the case where an n-type in FIGS. 13B to 13 D is changed to a p-type.
- the effect of interposing SiGe is greater in a p-type.
- a barrier is not present in a semiconductor, so that a contact resistance can be reduced remarkably.
- SiC is a semiconductor with a wide bandgap, and is considered to operate at a high voltage using this feature in practical use. Under a high electric field, unnecessary electron-hole pairs are generated by an avalanche effect between a gate and a drain. As in a SiMOSFET for power, a p-sinker absorbing the holes is required. However, if it is difficult to form a satisfactory contact with respect to a p-type as described above, the p-sinker does not function sufficiently.
- the construction described in Embodiment 5 solves this problem. In this construction, SiGe with a small bandgap is interposed, whereby n-SiC is connected to p-SiC at a low resistance, whereby holes generated under the gate are recombined in SiGe.
- an ohmic electrode is formed on SiGe with a small bandgap. Therefore, a heat treatment for obtaining an ohmic contact may be conducted at a very low temperature, or such a heat treatment is not required if the impurity concentration of SiGe is high enough.
- the ohmic metal can be selected from various materials, which are suitable for other fabrication processes. Needless to say, even with polysilicon in a high concentration introduced into conventional technology as wiring, an ohmic contact can be formed. Furthermore, an intrinsic semiconductor portion is not degraded due to thermal hysteresis in the course of formation of an ohmic contact, so that stable device characteristics are achieved.
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JP3650727B2 (en) * | 2000-08-10 | 2005-05-25 | Hoya株式会社 | Silicon carbide manufacturing method |
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US6956239B2 (en) * | 2002-11-26 | 2005-10-18 | Cree, Inc. | Transistors having buried p-type layers beneath the source region |
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Also Published As
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US6974751B2 (en) | 2005-12-13 |
JP2002252233A (en) | 2002-09-06 |
US20040178413A1 (en) | 2004-09-16 |
US20020113240A1 (en) | 2002-08-22 |
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