US6802066B1 - Method and system to share circular buffer without using locking mechanism - Google Patents
Method and system to share circular buffer without using locking mechanism Download PDFInfo
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- US6802066B1 US6802066B1 US09/358,796 US35879699A US6802066B1 US 6802066 B1 US6802066 B1 US 6802066B1 US 35879699 A US35879699 A US 35879699A US 6802066 B1 US6802066 B1 US 6802066B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
Definitions
- the subject invention relates generally to computer systems and more particularly to a software implemented lockless circular buffer.
- emulation software has been employed together with a number of microprocessor chips to emulate mainframe hardware.
- Such emulation software is comprised of many processes, each of which emulates a piece of prior art hardware, such as a central processor, an I/O processor or a task control unit.
- the processes request actions from each other by sending messages.
- Each message is 4 (64-bit) words long.
- the receiving process must receive messages in the order they are sent.
- Message ordering is critical. For example, a first of two messages might indicate a first value to be written in a disk storage space and the second message an update of that value. If the messages are reversed, the incorrect value will be stored on disk.
- the emulator implements message ordering by establishing a circular buffer for each process—a fixed length area where messages are placed when they are sent to the process. Sending processes put messages in each successive slot in the buffer, and the receiving process retrieves them in the same order, according to a first-in, first-out (FIFO) protocol.
- FIFO first-in, first-out
- the invention provides a lockless circular buffer. Slots in the buffer are assigned using a counter which is incremented atomically. In this manner, a process can fetch the counter from memory, increment it by 1, and store it back into memory without the possibility of interruption by another process. This “atomic” operation assures that a unique slot number will be assigned to each process request, even though such requests occur simultaneously.
- Two counters are kept for each buffer: one contains the number of messages inserted and the other contains the number of messages removed. The number of the last message removed is used to resolve overflow situations where the buffer fills up, resulting in two processes being assigned the same slot number.
- FIG. 1 is a schematic block diagram illustrating a number of processes which may request a slot in a buffer established by another process
- FIG. 2 is a block diagram illustrating data processing apparatus according to the preferred embodiment
- FIG. 3 is a portion of a flow diagram illustrating the method and apparatus according to the preferred embodiment
- FIG. 4 is a continuation of the diagram of FIG. 3;
- FIG. 5 is a portion of a second flow diagram illustrating the method and apparatus according to the preferred embodiment.
- FIG. 6 is a continuation of the flow diagram of FIG. 5 .
- FIG. 1 illustrates a buffer 11 associated with a first process 13 .
- Three other processes 15 , 17 , 19 are shown, each of which may wish to send a message to the first process 13 by placing such a message in the buffer 11 .
- Such a message might, for example, instruct the first process to perform an I/O operation.
- multiple processes may send messages to the buffer 11
- only the first process 13 may remove messages from the buffer 11 .
- each of the other three processes 15 , 17 , 19 has a buffer like buffer 11 so that all the processes may send messages to one another.
- FIG. 1 One example of the use of a number of processes as illustrated in FIG. 1 is in the use of a plurality of microprocessor chips to emulate a prior art main frame computer.
- a plurality of microprocessor chips may comprise a processor 16 as shown in FIG. 2 .
- the processor 16 may comprise, for example, two or four microprocessors.
- Each of the microprocessors may be, for example, an Intel Pentium Zeon operating at 500 MHz.
- the processor 16 is caused to emulate a desired main frame computer by emulation software contained in a random access memory (RAM) 18 .
- the emulation software is typically loaded into RAM 18 from a CD ROM 20 .
- the processes of the emulation software each emulate an actual piece of prior art main frame hardware, such as a central processor, an I/O processor and a Task Control Unit (TCU).
- main frame hardware such as a central processor, an I/O processor and a Task Control Unit (TCU).
- TCU Task Control Unit
- the lockless buffer of the preferred embodiment is created and controlled by a program written in “C” and stored in RAM 18 and CD ROM 20 .
- the buffer 11 per se is implemented or established by instructions comprising part of process 13 , which is typically initiated when a user starts the emulation software by clicking a PC mouse on an icon.
- Insert Event Caused when a message is inserted and a consumer “remover” is waiting to remove a message
- each slot in the buffer 11 is arranged to contain the following binarily encoded information:
- the Message Number of the message to be inserted is obtained by incrementing the Insert Count.
- the Insert Count comprises a very large word or “counter,” for example, 64 bits, stored in memory, which is incremented each time a message is inserted into the buffer 11 .
- the Message Number is “ ⁇ 1.” It is incremented to “0” for the first message, “1” for the second message etc.
- step 21 is performed using the XADD instruction of the Intel Pentium processor via the InterlockedIncrement function in Microsoft C.
- step 21 is performed “atomically”, that is the sending process fetches the counter from memory, increments it by one, and stores it back into the memory without the possibility of interruption by another process.
- the slot number is determined by performing the operation:
- the sending process obtains the current slot state and increments the active writer inserter count of the Message State.
- This step 25 is also performed atomically using the XADD instruction to insure integrity of the active inserter count variable.
- the sending process performs a test to determine whether the slot computed in step 25 is available to receive a message.
- the flow proceeds to decision point 35 where the sending process awaits removal of a message from the buffer 11 , which could potentially open a slot for the waiting message. If a remove event occurs, the flow proceeds along path 37 to the test 27 to determine whether the slot has now become available. If, while a process is at decision point 35 , a remove event does not occur within a selected timeout, the process proceeds along path 39 (FIG. 4) to the “return failure” step 40 .
- the message passing module is only responsible for trying to pass a message from one process to another.
- the message could not be delivered. What the sender does at this point is dependent on the application. Some senders may decide to try again later. Some may put out an error message to the operator and abort themselves. The particular response depends on the application and the criticality of the message. In an emulator, the senders will typically inform the operator and halt the emulator.
- step 39 the message content and message number are stored in the slot identified in step 23 .
- step 41 the message state is marked as “ready to be removed.” This marking allows the Remover to distinguish between a slot where the message is in the process of being inserted (i.e., the data has not yet been completely transferred) and a slot from which the Remover can safely extract a complete message.
- the active inserter count is also decremented since the process in question is no longer attempting to insert a message into the buffer. The decrementing of the active inserter count is again performed atomically via the XADD instruction.
- step 55 of FIG. 5 the Message Number of the message to be removed is computed by incrementing the Remove Count. This step need not be achieved by an atomic operation since there is only one remover.
- step 57 the slot number of the message to be removed is determined by performing the operation:
- Step 59 the process 13 gets the current Message State of the slot so determined and sets the “Remover waiting” bit of the Message State.
- Step 59 is also performed atomically by XADD to ensure integrity of the procedure.
- the “message ready to be removed” indication of the Message State is then tested in Step 61 . If there is a message ready to be removed, i.e., a message in the slot, the process proceeds to Step 71 to retrieve the message content. If there is no message in the slot, the procedure follows along path 63 to Step 65 wherein the remover process waits on an insert event to occur, i.e., the process waits on a slot to be filled with a message. If an insert event occurs, the remover process obtains the Message State in Step 67 and returns to perform test 61 .
- step 75 the slot from which the message was just removed in step 71 has its state marked to indicate the slot as empty with no remover waiting.
- step 75 an inquiry is made as to whether or not an inserter is waiting for this slot (diamond 77 ). If the answer to this inquiry is yes, then the event is caused (block 81 ) and a return of Success is sent (bubble 82 ). On the other hand, if no inserter is waiting for this slot, then Success is returned without having to cause the event.
- the algorithm according to the preferred embodiment relies on the XADD and XCHG instructions of the Intel Pentium processor (via the InterlockedIncrement, InterlockedDecrement and InterlockedExchangeAdd functions in Microsoft C).
- Such instructions allow a counter to be incremented atomically. That is: a process can fetch the counter from memory, increment it by 1, and store it back into memory without the possibility of interruption by another process. Two such counters are kept for each buffer: one contains the number of messages inserted and the other contains the number of messages removed.
- the senders need to be able to determine which should use the slot next.
- the insert algorithm therefore has each sender check the number of the last message removed by the receiver (Step 27 of FIG. 3 ). If a sender's message number is within 256 of the last received message number, then it is that sender's turn to use the slot. Otherwise, the sender continues to wait until the slot becomes available again.
- the methods and apparatus of the present invention may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
- the methods and apparatus of the present invention may also be embodied in the form of program code that is transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
- the program code When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits.
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US09/358,796 US6802066B1 (en) | 1999-07-22 | 1999-07-22 | Method and system to share circular buffer without using locking mechanism |
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US09/358,796 US6802066B1 (en) | 1999-07-22 | 1999-07-22 | Method and system to share circular buffer without using locking mechanism |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040004960A1 (en) * | 2002-01-07 | 2004-01-08 | Via Technologies, Inc. | Message transmitting queue and associated method |
US20050155041A1 (en) * | 2004-01-12 | 2005-07-14 | International Business Machines Corporation | Random access for processing messages in a message queue |
US20050262510A1 (en) * | 2004-05-13 | 2005-11-24 | Ittiam Systems (P) Ltd | Multi-threaded processing design in architecture with multiple co-processors |
US20060048162A1 (en) * | 2004-08-26 | 2006-03-02 | Bull Hn Information Systems Inc. | Method for implementing a multiprocessor message queue without use of mutex gate objects |
US7185061B1 (en) * | 2000-09-06 | 2007-02-27 | Cisco Technology, Inc. | Recording trace messages of processes of a network component |
US7802062B2 (en) | 2007-09-28 | 2010-09-21 | Microsoft Corporation | Non-blocking variable size recyclable buffer management |
US9223638B2 (en) | 2012-09-24 | 2015-12-29 | Sap Se | Lockless spin buffer |
EP2979182A1 (en) * | 2013-03-28 | 2016-02-03 | Microsoft Technology Licensing, LLC | On-demand scalable timer wheel |
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US5797035A (en) * | 1993-12-10 | 1998-08-18 | Cray Research, Inc. | Networked multiprocessor system with global distributed memory and block transfer engine |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7899878B2 (en) | 2000-09-06 | 2011-03-01 | Cisco Technology, Inc. | Recording trace messages of processes of a network component |
US7185061B1 (en) * | 2000-09-06 | 2007-02-27 | Cisco Technology, Inc. | Recording trace messages of processes of a network component |
US20070168993A1 (en) * | 2000-09-06 | 2007-07-19 | Cisco Technology, Inc. | Recording Trace Messages of Processes of a Network Component |
US20040004960A1 (en) * | 2002-01-07 | 2004-01-08 | Via Technologies, Inc. | Message transmitting queue and associated method |
US7779083B2 (en) * | 2002-01-07 | 2010-08-17 | Via Technologies, Inc. | Message transmitting queue and associated method |
US20050155041A1 (en) * | 2004-01-12 | 2005-07-14 | International Business Machines Corporation | Random access for processing messages in a message queue |
US7562365B2 (en) * | 2004-01-12 | 2009-07-14 | International Business Machines Corporation | Random access for processing messages in a message queue |
US20050262510A1 (en) * | 2004-05-13 | 2005-11-24 | Ittiam Systems (P) Ltd | Multi-threaded processing design in architecture with multiple co-processors |
US7634776B2 (en) * | 2004-05-13 | 2009-12-15 | Ittiam Systems (P) Ltd. | Multi-threaded processing design in architecture with multiple co-processors |
US20060048162A1 (en) * | 2004-08-26 | 2006-03-02 | Bull Hn Information Systems Inc. | Method for implementing a multiprocessor message queue without use of mutex gate objects |
US7802062B2 (en) | 2007-09-28 | 2010-09-21 | Microsoft Corporation | Non-blocking variable size recyclable buffer management |
US9223638B2 (en) | 2012-09-24 | 2015-12-29 | Sap Se | Lockless spin buffer |
EP2979182A1 (en) * | 2013-03-28 | 2016-02-03 | Microsoft Technology Licensing, LLC | On-demand scalable timer wheel |
EP2979182B1 (en) * | 2013-03-28 | 2021-11-03 | Microsoft Technology Licensing, LLC | On-demand scalable timer wheel |
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