US6898060B2 - Gated diode overvoltage protection - Google Patents
Gated diode overvoltage protection Download PDFInfo
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- US6898060B2 US6898060B2 US10/445,617 US44561703A US6898060B2 US 6898060 B2 US6898060 B2 US 6898060B2 US 44561703 A US44561703 A US 44561703A US 6898060 B2 US6898060 B2 US 6898060B2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
Definitions
- SOI semiconductor-on-insulator
- Si semiconductor-on-insulator
- insulating material e.g., a buried oxide region
- SOI circuits like other electronic devices, are susceptible to damage from electrostatic discharge (ESD).
- ESD electrostatic discharge
- protection schemes attempt to provide a discharge path with a low voltage turn-on and a high current capacity (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed).
- Discharge paths using traditional bulk devices do not work well on SOI devices because of the presence of a relatively thin SOI buried oxide layer. That is, conventional diodes on SOI devices have small current capacity because the current is carried laterally through an active device region of limited thickness.
- Lu discloses a SOI diode, which could be used for ESD design.
- the SOI diode disclosed in Lu consists of a floating-body SOI transistor, with the gate connected to a signal pad.
- the Lu diode itself may have a thin insulating layer that is susceptible to damage from relatively moderate voltage differences.
- Lu shorts the gate to the cathode.
- the Lu diode may not be suitable for usage in a mixed-voltage environment because the voltage difference between the gate and the anode may be sufficient to damage the insulating layer. This damage may lead to early ESD failures.
- This problem is not limited to SOI devices. Rather, it exists in bulk Si devices as well.
- the circuit includes: a terminal, a gated diode, and a bias circuit.
- the terminal is configured to convey a voltage signal.
- the gated diode has an anode, a cathode, and a gate.
- the gated diode is coupled between the terminal and a predetermined voltage node so as to enter a forward conduction mode during electrostatic discharge (ESD) events, overvoltage conditions, or transient signal excursions.
- ESD electrostatic discharge
- the bias circuit is configured to establish a low-resistance path between the cathode and gate when the gated diode is in a forward conduction mode, and to eliminate the low-resistance path when the gated diode is not in the forward conduction mode.
- the method comprises: (a) configuring one or more gated diodes to shunt ESD events and minimize any signal excursion outside a predetermined voltage range; and (b) protecting gate insulators of the one or more gated diodes.
- the protecting includes (1) minimizing a voltage difference between the cathode and gate of each gated diode that is operating in a forward conduction mode; and (2) increasing the voltage difference between the cathode and gate of each gated diode that is not operating in the forward conduction mode to provide a gate voltage between the positive and negative supply voltages.
- FIG. 1 shows an illustrative cross-section of a gated diode
- FIG. 2 a shows a schematic symbol used to represent a gated diode
- FIG. 2 b shows parasitic capacitances that may be associated with a gated diode
- FIG. 3 shows an electrostatic discharge (ESD) protection circuit in accordance with a first embodiment
- FIG. 4 shows an ESD protection circuit in accordance with a second embodiment
- FIG. 5 shows voltage curves associated with simulations of normal operations for the second embodiment
- FIG. 6 a shows voltage and current curves associated with simulations of ESD operation
- FIG. 6 b shows a circuit used for simulating the ESD operation shown in FIG. 6 a;
- FIG. 7 shows an ESD protection circuit in accordance with a third embodiment
- FIG. 8 shows voltage curves associated with simulations of normal operations for the third embodiment.
- FIG. 9 shows an ESD protection circuit in accordance with a fourth embodiment.
- FIG. 1 shows a cross-sectional view of a gated SOI (semiconductor-on-insulator) diode 100 .
- SOI semiconductor-on-insulator
- diode 100 is manufactured on the surface of a substrate 102 .
- Substrate 102 may be a portion of a silicon wafer because silicon is an inexpensive, well-understood material that offers various beneficial properties including a relatively high thermal conductivity.
- substrate materials are known and may be used.
- the characteristic feature of SOI technology is the creation of semiconductor devices on an insulating surface.
- the substrate itself is not an insulator due to the poor thermal conductivity of most insulating materials. Accordingly, an insulating layer 104 may be created on substrate 102 .
- the insulating layer is silicon dioxide (SiO 2 ), but again, other insulating materials are known and may be used.
- Diode 100 may be an isolated region of semiconducting material 108 that is deposited on insulation layer 104 and that is laterally isolated within a second insulating layer 106 .
- the electrical isolation of region 108 may advantageously allow diode 100 to operate faster, to be smaller, and to be placed more closely to other devices.
- Semiconducting material 108 includes at least three subregions that are tailored to form the active device region of diode 100 . The subregions are labeled P+, N, and N+ to indicate the doping of the material (i.e., the type and amount of impurities introduced into the semiconducting material).
- diode 100 is either “U-shaped” or rectangular in nature, so that the two N+ regions may actually be a single N+-type region that surrounds an inner N-type region, which in turn surrounds the inmost P+-type region.
- the N+ region may be coupled to an electrical conductor 110 , and the P+ region may be coupled to another electrical conductor 112 .
- Conventional materials for these conductors may include aluminum, copper, silver, gold, tungsten, molybdenum, tantalum, titanium, and various suicides (e.g., WSi 2 , MoSi 2 , TaSi 2 , TiSi 2 ). Of course, other conducting (and semiconducting) materials are known and may be used.
- Diode 100 may also include a gate 114 that is isolated from the semiconducting material 108 and contacts 110 , 112 by a thin insulator 116 .
- Gate 114 may be a conventional conducting material, but for a number of reasons, polycrystalline silicon (“polysilicon”) may be preferred. In addition to its well-understood nature, polysilicon may operate as a mask in a self-aligned deposition technique for creating diode 100 . Between the gate 114 and the semiconducting material 108 , the gate insulator 116 is thin. Certain limits may be enforced on the maximum voltage difference across the gate insulator to avoid significant degradation. For a standard goal of a 10-year lifetime, the steady-state difference for these gate thicknesses may be limited to less than 1.5 volts.
- Diode 100 is thus a three-terminal device.
- the three terminals are labeled A (anode), K (cathode), and G (gate).
- a P-N junction exists between the P+ and N-type regions of material 108 .
- Current can flow with relative ease from anode to cathode, but will under normal conditions be unable to flow from cathode to anode.
- a positive voltage difference between the anode and the gate will induce an inversion layer in the N-type region, thereby increasing the junction area and reducing the resistance to current flow from anode to cathode.
- Diode 100 is only one example of a gated diode.
- Various other material configurations in both SOI and bulk silicon technologies, may be used to implement a gated diode. Further, though the protection of a gate insulator in a gated diode is discussed in detail below, the described techniques may also be suitable for protecting insulation layers in other gated devices.
- FIG. 2 a shows a circuit schematic symbol used herein to represent a gated diode.
- the three terminals are labeled A (anode), K (cathode), and G (gate).
- FIG. 2 b shows a gated diode along with parasitic capacitances that exist between the three terminals.
- Capacitance 202 represents the parasitic capacitance between the gate and the anode (C GA )
- capacitance 204 represents the parasitic capacitance between the gate and the cathode (C GK )
- capacitance 206 represents the parasitic capacitance between the anode and the cathode (C AK ).
- the gate-anode capacitance 202 is expected to be relatively small and may be neglected for purposes of the present discussion.
- the gate-cathode capacitance 204 is expected to be dominated by capacitance across the gate insulator, which may be relatively substantial.
- the anode-cathode capacitance 206 is expected to be dominated by the inherent capacitance of the P-N junction. This capacitance can vary enormously based on device geometry, but is expected to be minimal, particularly in devices constructed using SOI techniques. In the subsequent figures, the parasitic gate-cathode capacitance 204 will be explicitly shown.
- FIG. 3 shows an integrated circuit pad 302 that may be used for connecting an integrated circuit to an external terminal, pin, solder ball, or other electrical connector suitable for transporting electrical signals to or from the integrated circuit. It may be desirable to protect circuitry (not shown) coupled to pad 302 from damage due to electrostatic discharge (ESD) events, overvoltage conditions, and/or transient signal excursions beyond a predetermined voltage range. Though these concerns are similar and indeed may involve significant overlap, to the extent that they can be distinguished, they may be characterized in the following ways. ESD events generally occur when the integrated circuit is unpowered. Transient signal excursions generally occur when the integrated circuit is powered.
- ESD electrostatic discharge
- Overvoltage conditions involve somewhat more sustained application of a signal voltage outside a given voltage range (i.e., the time scale is greater than that generally encountered for ESD events and transient signal excursions), and are most commonly encountered as the integrated circuit is being powered up.
- the circuits and methods described below may be used to provide protection in each of these circumstances, and accordingly, the labels “ESD event”, “overvoltage condition”, and “signal excursion” may be used interchangeably.
- the anode of gated diode 304 is coupled to pad 302 , and the cathode is coupled to a positive voltage rail (e.g., supply voltage VDD) or some other node having a predetermined voltage at the upper end of a predetermined voltage range when power is applied to the integrated circuit.
- the cathode of gated diode 306 is coupled to pad 302 , and the anode is coupled to a negative voltage rail (e.g., ground, supply voltage VSS) or some other node having a predetermined voltage at the lower end of the predetermined voltage range when power is applied to the integrated circuit.
- the power rails may provide a low resistance path with the maximum available current capacity for dissipating the event energy and minimizing the probability of damage.
- this diode configuration ideally operates to keep the pad signal voltage (VPAD) within the predetermined voltage range (e.g., between the voltage rails). That is, diode 304 ideally prevents VPAD from exceeding the upper end of the predetermined voltage range, and diode 306 ideally prevents VPAD from dropping below the lower end of the voltage range.
- VPAD pad signal voltage
- gated diodes 304 , 306 may include a gate insulator that is susceptible to damage from even moderate voltage differences. Accordingly, FIG. 3 also shows an “upper” bias circuit 308 and a “lower” bias circuit 310 that operate to protect gated diodes 304 and 306 , respectively.
- the bias circuits provide two desirable features: a) a “short circuit” between the cathode and gate when the gated diode operates in a forward-conduction mode (i.e., current flows from anode to cathode); and b) a gate voltage that is between the voltages of the nodes defining the predetermined voltage range when the pad voltage is also in the range.
- upper bias circuit 308 provides a short circuit between cathode and gate when diode 304 is in forward conduction mode, and a gate voltage approximately midway between the positive voltage rail and the lowest pad voltage expected during normal operations.
- lower bias circuit 310 provides a short circuit between cathode and gate when diode 306 is in forward conduction mode, and a gate voltage approximately midway between the negative voltage rail and the highest pad voltage expected during normal operations.
- the short circuit between gate and cathode during forward conduction may be desirable for two reasons. First, the resistance to current flow is minimized. Second, the parasitic gate-cathode capacitance is bypassed, which may alternatively be viewed as simply minimizing the voltage drop across the gate insulator.
- the intermediate gate voltages described above may be desirable during normal operations to extend the operating range of gated devices.
- a SOI gated diode that is limited to a maximum voltage drop of 1.5 volts across the gate insulator may nevertheless be used in a circuit where the expected pad voltage ranges between 0 and 1.8 volts.
- the voltage rails VSS and VDD are 0 and 1.8 volts, respectively.
- FIG. 4 shows one embodiment of the upper and lower bias circuits 308 , 310 .
- Upper bias circuit 308 may include two resistances 402 and 404 coupled in series between the voltage rails VDD and VSS. This configuration is commonly known as a “voltage divider”, and when power is applied, the circuit creates an intermediate voltage at the node (VG 1 ) between the resistances by splitting the difference between the voltage rails in accordance with the ratio of the resistances. If it is desired to place VG 1 at, say, 1.5 volts when the voltage difference between VDD and VSS is 1.8 volts, the resistances would be given a 3:15 ratio. The magnitude of the resistances may be large enough to reduce power consumption to tolerable levels, and may further be small enough to minimize their area requirements on the integrated circuit substrate.
- Upper bias circuit 308 may further include a transistor 406 (which may be a metal-insulator-semiconductor field effect transistor, commonly called a MOSFET) coupled in parallel with resistance 402 , and with its gate coupled to the pad voltage VPAD.
- transistor 406 which may be a metal-insulator-semiconductor field effect transistor, commonly called a MOSFET
- MOSFET metal-insulator-semiconductor field effect transistor
- Transistor 406 may be off until the pad voltage approximately equals or exceeds the positive voltage rail VDD, at which point transistor 406 turns on, allowing current to bypass resistance 402 . Again, the gate and cathode of diode 304 are in effect “short circuited” when transistor 406 is on.
- Lower bias circuit 310 may also include two resistances 408 and 410 in a voltage divider configuration between the voltage rails to create an intermediate voltage for the gate (VG 2 ) of diode 306 when power is applied. VG 2 may be placed at the midpoint between the voltage rails using resistances with a 1:1 ratio. Lower bias circuit 310 may further include a transistor 412 (again, this may be a MOSFET) coupled between the gate VG 2 of diode 306 and the pad VPAD, with the gate of transistor 412 coupled to the negative voltage rail VSS. When the circuit is unpowered, the gate voltage is zero.
- the falling pad voltage causes transistor 412 to turn on, thereby creating a short circuit between the gate and cathode of diode 306 .
- the voltage divider may operate normally as long as transistor 412 is off. Transistor 412 may be off until the pad voltage approximately equals or drops below the negative voltage rail VSS, at which point transistor 412 turns on. When transistor 412 is on, it may nullify the effect of the voltage divider and in effect “short circuit” the gate and cathode of diode 306 .
- the intermediate voltage during normal operations may be any voltage that satisfies the following conditions:
- the intermediate voltages produced by the voltage dividers may be subject to variation from competing effects such as parasitic capacitances and/or partial turn-on of the transistors.
- FIG. 5 shows a set of waveforms that result from simulated operation of the embodiment of FIG. 4 under normal operating conditions.
- Waveform “A” is the positive voltage rail (constant at 1.8 volts); waveform “C” is the negative voltage rail (constant at 0 volts); and waveform “R” shows an input voltage applied to the pad (VPAD).
- the input voltage as shown alternates between 1.0 and 1.8 volts, with nonzero rise and fall times.
- Waveform “H” is the gate voltage VG 1 , which holds relatively steady at 1.5 volts but shows roughly 0.1 volts of variation which may be due to small parasitic capacitances in diode 304 and transistor 406 .
- Waveform “L” is the gate voltage VG 2 which averages about 0.85 volts and shows about 0.35 volts of variation in each direction. This variation is in phase with the pad voltage, and may be due to the gate-cathode capacitance of diode 306 . Although the use of smaller resistances in lower circuit 310 might significantly reduce this variation, the voltage drops across the gate insulator are well within limits, and the smaller resistances would undesirably increase the impedance loading on the input signal.
- FIG. 6A shows two waveforms that result from simulated operation of the embodiment of FIG. 4 under ESD conditions (more specifically, an HBM discharge applied to VSS with the pad grounded). Note that ESD events may occur when the circuit is unpowered, so that for this simulation, the embodiment of FIG. 4 may be simplified and represented as shown in FIG. 6 B.
- Waveform “B” is the current flowing through transistor 412 during the first 20 nanosecond after a negative-going electrostatic impulse is applied to the pad (VPAD), and waveform “E” is the gate voltage VG 2 for diode 306 during this time. Note that the gate-cathode capacitance is quickly discharged as the gate is shorted to the cathode, and the voltage drop across the gate insulator is maintained well within the limits.
- FIG. 7 shows another embodiment of the upper bias circuit 308 . It may include a pair of complementary transistors 702 , 704 , which may be MOSFETs. Transistor 702 may be coupled between the gate and the cathode of diode 304 , with the transistor gate coupled to the pad voltage VPAD. Transistor 704 may be coupled between the gate of diode 304 and a voltage rail. In one contemplated embodiment, the negative voltage rail (VSS) is used. In an alternative embodiment, an intermediate supply voltage (VALT) may be used (e.g., about 1.2 volts). As before, when the circuit is unpowered, the gate voltage VG 1 is zero. A positive-going ESD event causes transistor 702 to turn on, short circuiting the gate and cathode of diode 304 .
- VGS negative voltage rail
- VVT intermediate supply voltage
- the transistors 702 and 704 bring the gate voltage VG 1 to some voltage between the positive voltage rail and the supply voltage to which transistor 704 is coupled. As the pad voltage rises above the positive voltage rail, transistor 702 is on while transistor 704 is off. In this state, the circuit effectively shorts the gate of diode 304 to its cathode. As the pad voltage falls below the supply voltage to which transistor 704 is coupled, transistor 702 is off while transistor 704 is on. This configuration places the gate voltage VG 1 at the supply voltage (VSS or VALT).
- FIG. 8 shows a set of waveforms that result from simulated operation of the embodiment of FIG. 7 under normal operating conditions.
- Waveform “A” is the positive voltage rail (constant at 1.8 volts); waveform “C” is the negative voltage rail (constant at 0); and waveform “E” is an input waveform applied to the pad (VPAD). The input waveform alternates between 1.0 and 1.8 volts, with nonzero rise and fall times.
- Waveform “D” is the gate voltage VG 1 , which holds relatively steady at about 1.42 volts, but shows roughly 0.1 volts of variation.
- Waveform “F” is the gate voltage VG 2 which averages about 0.6 volts and shows about 0.4 volts of variation in each direction. This variation is in phase with the pad voltage, and may be due to the gate-cathode capacitance of diode 306 .
- FIG. 9 shows another embodiment of lower bias circuit 310 . It may include four transistors 902 , 904 , 906 , and 908 which may be MOSFETs.
- Transistor 902 may be coupled between a supply voltage VALT (which may be between the positive and negative voltage rails) and the gate of diode 306 , with the transistor gate coupled to the pad voltage (VPAD).
- Transistor 904 may be coupled between the pad and transistor 906 , with the gate of transistor 904 coupled to VALT.
- Transistor 906 may be coupled between transistor 904 and the gate of diode 306 , with the gate of transistor 906 coupled to the negative voltage rail.
- Transistor 906 may be complementary to transistor 904 .
- Transistor 908 may be coupled between the gate and cathode of diode 306 , with the gate of transistor 908 coupled to the negative voltage rail.
- transistor 902 When the pad voltage is above VALT (e.g., above 1.2 volts), transistor 902 may allow current to flow from VALT to the VG 2 , raising the voltage of the diode gate toward VALT, and transistor 904 may be off. When the pad voltage falls below VALT, transistor 902 may be off, and transistor 904 may turn on, allowing current flow from the diode gate towards VPAD, reducing the gate voltage VG 2 toward VPAD. Transistor 906 may be on at all times during these conditions. However, when a negative ESD event is applied to VPAD, transistors 902 and 906 may be off. In this case, transistor 908 turns on and may couple VG 2 to VPAD, effectively short circuiting the gate and cathode of diode 306 .
- VALT e.g., above 1.2 volts
Abstract
Description
|V GA |<V MAX and |V GK |<V MAX,
where VMAX is the design limit for a voltage drop across the gate insulator, VGA is the gate-anode voltage, and VGK is the gate-cathode voltage. It should be further noted variation of the intermediate voltages may exist and may be tolerated when the above conditions are satisfied. The intermediate voltages produced by the voltage dividers may be subject to variation from competing effects such as parasitic capacitances and/or partial turn-on of the transistors.
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US20060180868A1 (en) * | 2005-02-16 | 2006-08-17 | International Business Machines Corporation | Structure and method for improved diode ideality |
US7408751B1 (en) | 2005-09-15 | 2008-08-05 | Integrated Device Technology, Inc. | Self-biased electrostatic discharge protection method and circuit |
US20090009917A1 (en) * | 2007-07-03 | 2009-01-08 | Hynix Semiconductor, Inc. | Electrostatic discharge device |
US7609493B1 (en) * | 2005-01-03 | 2009-10-27 | Globalfoundries Inc. | ESD protection circuit and method for lowering capacitance of the ESD protection circuit |
US20100108958A1 (en) * | 2008-10-31 | 2010-05-06 | Cole James R | Calcium fluoride optics with improved laser durability |
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US20120176708A1 (en) * | 2011-01-06 | 2012-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Esd protection devices and methods for forming esd protection devices |
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