|Numéro de publication||US6987052 B2|
|Type de publication||Octroi|
|Numéro de demande||US 10/697,757|
|Date de publication||17 janv. 2006|
|Date de dépôt||30 oct. 2003|
|Date de priorité||30 oct. 2003|
|État de paiement des frais||Payé|
|Autre référence de publication||US20050093097|
|Numéro de publication||10697757, 697757, US 6987052 B2, US 6987052B2, US-B2-6987052, US6987052 B2, US6987052B2|
|Inventeurs||Frank A. Baiocchi, John Charles Desko, Bailey R. Jones, Sean Lian|
|Cessionnaire d'origine||Agere Systems Inc.|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (4), Référencé par (11), Classifications (19), Événements juridiques (7)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
The present invention relates generally to semiconductor devices, and more particularly relates to techniques for forming an improved substrate contact for use in a metal-oxide-semiconductor device.
Power MOS devices, including lateral diffused MOS (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. Radio frequency (RF) LDMOS devices are generally fabricated on a semiconductor wafer comprising a substrate that is typically formed of single crystal silicon which has been heavily doped with an impurity, such as, for example, boron, so as to form a low-resistivity substrate (e.g., about 1018 to about 1019 atoms per cubic centimeter). A lightly doped epitaxial layer (e.g., about 1014 to about 1015 atoms per cubic centimeter), typically about ten microns thick, is generally formed on the substrate.
One problem in fabricating the LDMOS device is providing a low-resistance electrical path from the device formed near an upper surface of the wafer, through the lightly-doped epitaxial layer to the more heavily-doped substrate below. Previous attempts to solve this problem typically involve forming a diffused sinker by doping the surface of the silicon with a heavy boron predeposition or implanting a relatively high dose ion implant, which is then driven at a high temperature (e.g., in excess of 1000 degrees Celsius) for a long duration (e.g., typically in excess of about 10 hours) through the epitaxial layer and down to the substrate. In driving the diffusion or implant down into the silicon, however, the dopant will out-diffuse on either side by a certain amount, typically about 8 microns. Thus, the formation of the diffused sinker consumes a substantially large area in the wafer. The requirement of a high-dose implant step can also result in excessive implant time for the wafer as well as unacceptable wafer heating.
The long period of time required for the high temperature drive-in process can undesirably result in a large up-diffusion of dopant from the heavily-doped substrate into the lightly-doped epitaxial layer which effectively thins the epitaxial layer, thereby lowering the junction breakdown voltage and increasing junction leakage. Additionally, an increase in the number of misfit dislocations can occur, generally originating from mismatches between the lattices of the epitaxial layer and substrate, from the epitaxial layer/substrate interface to the surface of the epitaxial layer. This often leads to reliability problems, among other disadvantages.
Other known attempts at providing a low-resistance path between the upper surface of the wafer and the substrate below have involved forming one or more conductive plugs in the epitaxial layer down to the substrate. This methodology involves first forming trenches (e.g., by a dry etching process) or v-grooves (e.g., by a wet etching process) through the epitaxial layer down to the substrate and depositing a conductive material, such as, for example, tungsten, metal or silicide, in the trenches or v-grooves, thereby establishing an electrical connection with the substrate. A primary disadvantage of this approach, however, is the inability to control a surface doping in the substrate and source silicon to produce acceptable contact resistance between the substrate/source silicon and deposited conductive layer. Another disadvantage with this approach is the need to precisely control the fill of the trench so as to ensure a substantially planar surface, which is essential for further processing, and a substantially void-free fill, typically a requirement in forming a sufficiently low-resistance contact.
There exists a need, therefore, for an enhanced substrate contact capable of improved performance and reliability that does not suffer from one or more of the above-noted deficiencies typically affecting conventional substrate contacts. Furthermore, it would be desirable if such a substrate contact was fully compatible with a conventional semiconductor process technology.
The present invention provides techniques for forming an improved low-resistance (e.g., less than about 10 ohms per square) substrate contact for use, for instance, in an MOS device. The improved substrate contact may be formed, in accordance with an illustrative embodiment of the invention, by heavily doping the sidewalls of one or more deep trenches, formed through an epitaxial layer of a semiconductor wafer, with an impurity predeposition, such as, for example, using boron, phosphorous or arsenic. In this manner, a low-resistance path can be formed between an upper surface of the semiconductor wafer and the substrate, without the need for an extensive high-temperature drive-in process and without relying on filling the trenches with a conductive material (e.g., metal, silicide, etc.) having a significant contact resistance associated therewith.
In accordance with one aspect of the invention, a method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The present invention will be described herein in the context of an illustrative MOS integrated circuit fabrication technology suitable for forming discrete RF LDMOS transistors, as well as other devices and/or circuits. It should be appreciated, however, that the present invention is not limited to the fabrication of this or any particular device or circuit. Rather, the invention is more generally applicable to techniques for forming a semiconductor structure capable of providing a low-resistance electrical connection between an upper surface of an epitaxial layer and a substrate associated with a semiconductor wafer. Moreover, although implementations of the present invention are described herein with specific reference to an LDMOS device and a complementary metal-oxide-semiconductor (CMOS) fabrication process, it is to be appreciated that the techniques of the present invention are similarly applicable to other fabrication processes (e.g., bipolar) and/or the formation of other devices, such as, but not limited to, an MOS field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a vertical diffused MOS (DMOS) device, an extended drain MOSFET device, etc., with or without modifications thereto, as will be understood by those skilled in the art. Other semiconductor devices, such as, but not limited to, monolithic capacitors, resistors, etc., may also benefit from the techniques of the present invention set forth herein.
The wafer 100 may include an epitaxial layer 104 formed on at least a portion of the substrate 102. The epitaxial layer 104 is preferably grown over the entire surface of the wafer 100, such as, for example, by using a conventional epitaxy process. Epitaxy is a well-known deposition technique during which additional silicon atoms can be deposited on a single-crystal silicon substrate, without changing the crystalline structure of the silicon wafer. During the epitaxial deposition, the single-crystal silicon substrate 102 can be extended by, for example, a vapor deposition of additional atomic layers of silicon. By controlling the deposition rates, and introducing selected types of impurities (e.g., boron, phosphorous, arsenic, etc.) into the carrier gases, the thickness and resistivity of the epitaxial layer 104 can be precisely controlled as desired. The thickness, tEPI, of the epitaxial layer 104 is typically about 6 to 10 microns. In a preferred embodiment of the invention, the epitaxial layer 104 is lightly doped compared to the substrate, e.g., about 5×1014 to about 1015 atoms percubic centimeter, with a p-type impurity (e.g., boron).
The term “semiconductor wafer,” or simply “wafer,” as may be used herein refers to the substrate 102, with or without an epitaxial layer 104, and preferably includes one or more other layers formed on the substrate. The term “wafer” is often used interchangeably with the term “silicon body,” since silicon is typically employed as the semiconductor material comprising the wafer. It should be appreciated that although the present invention is illustrated herein using a portion of a semiconductor wafer, the term “wafer” may include a multiple-die wafer, a single-die wafer, or any other arrangement of semiconductor material on which a semiconductor structure may be formed.
As apparent from the figure, one or more insulating layers may be formed on at least a portion of the epitaxial layer 104. The insulating layers preferably comprise an oxide, such as, for example, silicon dioxide (SiO2) and may therefore be referred to as oxide layers. The insulating layers may comprise alternative materials, such as, but not limited to, silicon nitride (SiN), etc. A first oxide layer 106 is preferably grown on the epitaxial layer 104, such as by using an oxidation (e.g., local oxidation) or surface passivation process. Oxidation, or surface passivation, may be achieved by exposing an upper surface of the silicon wafer 100 to an oxidizing agent, such as, but not limited to, oxygen gas, water vapor, etc., at a relatively high temperature (e.g., about 900 to about 1200 degrees Celsius). The first oxide layer 106 may be referred to as a thermal oxide layer. A second oxide (or nitride) layer 108 may be formed on at least a portion of the thermal oxide layer 106, such as, for example, by using low-pressure chemical vapor deposition (LPCVD), or an alternative deposition process. In a preferred embodiment of the invention, the second oxide layer 108 comprises low-pressure tetraethyloxysilane (LP-TEOS), and may therefore be referred to herein as a TEOS layer. The oxide layer(s) 106, 108, each of which may be about 0.5 microns thick for a 0.35-micron CMOS process, provide many benefits during the fabrication of an MOS device, some of which include protecting the wafer from external contamination and serving as a barrier to the diffusion of impurities into the silicon. Thus, by etching well-defined patterns in the oxide layer(s), one can accurately diffuse desired impurities into selected areas of the wafer 100.
As shown in
An important advantage of the techniques of the present invention is the elimination of the long duration high-temperature drive-in process required by conventional methodologies, thereby improving the performance and reliability of the device formed in the wafer 100, as well as significantly speeding up the fabrication process. As previously explained, in forming a conventional substrate contact comprising a diffused sinker, in order to distribute the impurity, which is typically diffused or implanted near the upper surface of the wafer, through the epitaxial layer and down to the substrate, an extensive high-temperature drive-in process is undesirably required. The duration of time required is generally proportional to the thickness of the epitaxial layer, since the rate of diffusion of the impurity is relatively constant for a given temperature and impurity type.
Forming openings 110 in the epitaxial layer 104 down to the substrate 102 advantageously enables the impurity 114 to be deposited, through the sidewalls of the trenches 112, in a substantially distributed manner between the upper surface of the epitaxial layer and the substrate. The deposition of the impurity 114 can be accomplished, for instance, by growing an impurity-rich oxide on the sidewalls of the trenches 112. Alternatively, the deposition may be accomplished using an implant step, especially where the sidewalls of the trenches are at least slightly sloped (e.g., v-shaped). Depositing the impurity 114 through the sidewalls of the trenches 112 enables the impurity to be placed in closer proximity to the substrate. Consequently, a significantly shorter drive-in process is needed, as compared to traditional approaches, in order to distribute the impurity through the epitaxial layer 104 as desired. The shorter drive-in period of the present invention beneficially decreases the likelihood that misfit dislocations from the epitaxial layer/substrate interface will diffuse to the surface of the epitaxial layer, thereby reducing device electrical leakage and reliability problems.
After the clean-up step, the trenches 112 are preferably filled with a filler material 116, such as, for instance, polysilicon. The polysilicon can be deposited using, for example, a LPCVD process, although alternative deposition techniques may also be employed, as will be known by those skilled in the art. The filler material 116 primarily provides planarization and structural support for the trenches 112 and thus need not have a substantially low resistivity associated therewith. Unlike a traditional conductive plug, which relies on the filler material being of low resistivity in order to provide the low-resistance electrical path between the upper surface of the wafer and the substrate, the substrate contact of the present invention relies on the doped sidewalls of the trenches 112 to provide the low-resistance electrical path. However, use of a filler material having a low resistivity (e.g., CVD tungsten, silicide, doped polysilicon, etc.) may even further lower the resistance of the substrate contact. In a preferred embodiment of the invention, doped polysilicon is used as the filler material 116. Since polysilicon characteristically behaves in a manner similar to silicon, the use of polysilicon as a filler material for the trenches provides a more homogeneous upper surface of the wafer 100, thereby making it easier to form active devices in the upper surface of the wafer, and is thus preferred.
Once the upper surface of the wafer has been made substantially planar, the thermal oxide layer 106 is preferably removed, such as by etching, and a thin oxide layer 118 and a silicon nitride layer 119 may be formed on the upper surface of the wafer 100, as shown in
A low-resistance (e.g., less than about 1 ohm per square) electrical path between the source region 806 and the substrate 802 is provided by forming one or more improved substrate contacts 810 through the epitaxial layer 804 of the wafer 800, such as in the manner previously described in connection with
It is to be appreciated that, in the case of forming a simple MOS device, because the MOS device is symmetrical in nature, and thus bidirectional, the assignment of source and drain designations in the MOS device is essentially arbitrary. Therefore, the source and drain regions may be referred to generally as first and second source/drain regions, respectively, where “source/drain” in this context denotes a source region or a drain region. In an LDMOS device, which is generally not bidirectional, such source and drain designations may not be arbitrarily assigned.
The exemplary LDMOS device may include a body region 818 formed in the epitaxial layer 804, such as by a conventional implant and diffusion process. The body region 818 is preferably formed adjacent to the source region 806 and extends laterally in a direction opposite the drain region 808. The body region 818 is preferably doped, such as by a conventional implant step, with an impurity of a known concentration level to selectively change the conductivity of the material as desired. Preferably, the body region 818 has a conductivity type associated therewith which is opposite a conductivity type of the source region 806. In a preferred embodiment of the invention, the body region 818 is of p-type conductivity, and is therefore referred to as a p-body.
A channel region 820 and a drift region, which may comprise a first LDD region 822 and a second LDD region 824, is formed proximate an upper surface of the exemplary LDMOS device, just beneath an interface between the silicon epitaxial layer 804 and an insulating layer 826, which in a preferred embodiment is formed of an oxide (e.g., silicon dioxide (SiO2), etc.). This interface may thus be referred to as a silicon/oxide interface. The channel region 820 is formed at least partially below and adjacent to the source region 806 while the drift region extends laterally between the channel region 820 and the drain region 808 in the LDMOS device. The channel region 820 may be formed of a material having the same conductivity type as the substrate, preferably p-type in the exemplary device, and may therefore be referred to as a p-channel.
The exemplary LDMOS device further includes a gate 828 formed above at least a portion of the channel region 820 and proximate the silicon/oxide interface of the wafer 800. The gate 828 may be formed of, for example, polysilicon material, although alternative suitable materials (e.g., metal, etc.) may be similarly employed.
A source contact 830 and a drain contact 832 may be formed on an upper surface of the insulating layer 826, such as, for example, by forming openings in the insulating layer (e.g., by photolithographic patterning and etching) to expose the silicide layer 812 and drain region 808, respectively, and filling the openings with an electrically conductive material (e.g., aluminum, gold, etc.), as will be understood by those skilled in the art. The silicide layer 812 facilitates electrical connection with the source region 808, since it would otherwise be difficult to form a metal layer directly on the silicon source region 806. Connection to the source region 806 may also be made through a bottom surface of the substrate, since the substrate contacts 810 provide a substantially low-resistance electrical path between the source region 806 and the substrate 802, as previously explained. A gate contact (not shown) may also be formed on the upper surface of the insulating layer 826, or in an alternative location, for providing an electrical connection to the gate 828.
It is to be appreciated that although the exemplary substrate contact shown in the accompanying figures includes two trenches, the number and/or geometrical dimensions and shapes of the trenches are not limited in any way to the precise embodiment shown. Rather, the present invention contemplates that any number, shape and/or size of the trenches may be used to form the substrate contact. For instance, the substrate contact may comprise a single trench, or more than two trenches. Moreover, although all of the sidewalls and bottom wall of the trenches are preferably heavily doped, this is not a requirement of the invention. For example, only one sidewall, or a sidewall and bottom wall may be doped, so as to provide a sufficient distribution of impurity between the substrate and upper surface of the wafer.
Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.
|Brevet cité||Date de dépôt||Date de publication||Déposant||Titre|
|US5856700 *||8 mai 1996||5 janv. 1999||Harris Corporation||Semiconductor device with doped semiconductor and dielectric trench sidewall layers|
|US6333234 *||13 mars 2001||25 déc. 2001||United Microelectronics Corp.||Method for making a HVMOS transistor|
|US6482714 *||24 févr. 2000||19 nov. 2002||Kabushiki Kaisha Toshiba||Semiconductor device and method of manufacturing the same|
|US6828628 *||5 mars 2003||7 déc. 2004||Agere Systems, Inc.||Diffused MOS devices with strained silicon portions and methods for forming same|
|Brevet citant||Date de dépôt||Date de publication||Déposant||Titre|
|US7541249 *||31 mars 2005||2 juin 2009||Atmel Germany Gmbh||Process for producing a base connection of a bipolar transistor|
|US7547618 *||26 juil. 2007||16 juin 2009||National Semiconductor Corporation||System and method for providing a deep connection to a substrate or buried layer of a semiconductor device|
|US8129778 *||2 déc. 2009||6 mars 2012||Fairchild Semiconductor Corporation||Semiconductor devices and methods for making the same|
|US8198154 *||27 sept. 2010||12 juin 2012||Alpha And Omega Semiconductor Incorporated||Method of forming bottom-drain LDMOS power MOSFET structure having a top drain strap|
|US20050221570 *||31 mars 2005||6 oct. 2005||Christoph Bromberger||Process for producing a base connection of a bipolar transistor|
|US20110014766 *||27 sept. 2010||20 janv. 2011||Alpha And Omega Semiconductor Incorporated||Bottom-drain ldmos power mosfet structure having a top drain strap|
|US20110127601 *||2 déc. 2009||2 juin 2011||Suku Kim||Semiconductor Devices and Methods for Making the Same|
|US20110198689 *||17 févr. 2010||18 août 2011||Suku Kim||Semiconductor devices containing trench mosfets with superjunctions|
|CN102254913A *||20 mai 2010||23 nov. 2011||上海华虹Nec电子有限公司||Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device structure and preparation method thereof|
|CN102456614A *||1 nov. 2010||16 mai 2012||上海华虹Nec电子有限公司||Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus|
|CN102456614B||1 nov. 2010||24 juil. 2013||上海华虹Nec电子有限公司||Realization method for metal source-substrate passage in radio-frequency LDMOS (laterally-diffused metal oxide semiconductor) apparatus|
|Classification aux États-Unis||438/343, 257/E21.427, 257/E29.119, 257/E21.538, 257/E29.268, 438/307|
|Classification internationale||H01L21/336, H01L21/74, H01L21/331, H01L29/417, H01L29/78|
|Classification coopérative||H01L21/743, H01L29/66659, H01L29/7835, H01L29/4175|
|Classification européenne||H01L29/66M6T6F11H, H01L21/74B, H01L29/78F3, H01L29/417D6|
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