US6999464B2 - Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor - Google Patents
Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor Download PDFInfo
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- US6999464B2 US6999464B2 US09/941,144 US94114401A US6999464B2 US 6999464 B2 US6999464 B2 US 6999464B2 US 94114401 A US94114401 A US 94114401A US 6999464 B2 US6999464 B2 US 6999464B2
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 230000000903 blocking effect Effects 0.000 title claims abstract description 11
- 239000000872 buffer Substances 0.000 claims description 17
- 230000003139 buffering effect Effects 0.000 claims description 9
- 238000009825 accumulation Methods 0.000 claims description 3
- 238000004220 aggregation Methods 0.000 claims description 3
- 230000002776 aggregation Effects 0.000 claims description 3
- 238000003860 storage Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
- H04L49/105—ATM switching elements
- H04L49/108—ATM switching elements using shared central buffer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5603—Access techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Definitions
- the present invention relates to communication data switching between pluralities of input and output ports, and, more particularly, to problems and limitations of present-day generally input-buffering system architectures and the like for the switching of variable-length data packets—limitations in the available number of ports for current data switching “speeds” and “feeds”; limitations with current data transmission delays, and in current available quality of service, including multiplexing jitter, interruptions, and in bandwidth, latency guarantees for particular data transmission services, and in obviating deleterious head-of-the-line blocking and non-scalability of architecture.
- the usual “feed” today is 8 to 12 ports, but this can go up as time goes by.
- the “speed” today is, say, OC192 (which is 10 gigabytes), but it can also go to OC768 which is 40 gigabytes, and then beyond.
- the prior art has most commonly taken the before-described input buffering approach, wherein the input data is locally buffered on an input port that has no “knowledge” of what input data may also be present at other input ports and contending for the same output port destination.
- the input port merely blindly makes the request of the input buffered switch to direct its data to the particular output port; and this prior architecture thus has had to live with its classic problems of potential head-of-the-line (HOL) blocking and inability to guarantee delay and jitter in quality of service.
- HOL head-of-the-line
- the input-buffered systems accordingly, have to put up with sometimes even unrealistic periods of time before data can make its way to the switch for enabling transmission to destination output ports.
- the particular output-buffered approach of the invention uses a central shared memory architecture comprised of a plurality of similar successive data memory channels defining a memory space, with fixed limited times of data distribution from the input ports successively into the successive memory cells of the successive memory channels, and in striped fashion across the memory space.
- This enables non-blocking shared memory output-buffered data switching, with the data stored across the memory channels uniformly.
- the invention embraces a method of receiving and outputting a plurality m of queues of data traffic streams to be switched from data traffic line card input ports to output ports, that comprises, providing a plurality n of similar successive data memory channels each having a number of memory cells defining a shared memory space assigned to the m queues; providing buffering for m memory cells, in front of each memory channel to receive and buffer data switched thereto from line card traffic streams, and providing sufficient buffering to absorb a burst from up to n line cards; and distributing successive data in each of the queues during fixed limited times only to corresponding successive cells of each of the successive memory channels and in striped fashion across the memory space, thereby providing non-blocking shared memory output-buffered data switching.
- FIG. 1 is a combined generalized block and circuit diagram of a preferred architecture for practicing the data write-path method of the invention.
- FIG. 2 is a similar diagram of read-out from the shared memory channel system of FIG. 1 .
- an illustrative preferred memory architecture for practicing the invention having, for the write path, a plurality n of similar successive data memory channels or banks (say, for 256 megabytes times n storage channels), labeled Memory Channel o through memory channel n-1 for storing and outputting m queues of variable length data traffic streams Queue o through Queue m-1 from respective data traffic line cards Line Card o through Line Card n-1 at input ports I, with, say, 10 Gigabits/sec.of bandwidth, and stored in the memory channels.
- Each of the n data memory channels is provided with a buffer having m memory cells, with the memory channels defining a shared memory space assigned to the m queues.
- the buffers are shown connected in front of each memory channel and are illustrated as in the form of first-in-first-out buffers FIFO o , FIFO 1 , . . . FIFO n-1 to receive and buffer data switched thereto at SW from the line cards.
- the buffers are designed to provide sufficient buffering to absorb a burst of data from up to n line cards; i.e. big enough to store data for m cells and to absorb a burst of, for example, OC192 traffic of variable length data packets from the line cards at the input ports I. [Example: 64 OC192 or 16 OC768 ports.]
- the maximum depth of each FIFO at the front of each memory channel is thus made equal to the number m of queues in the system.
- the data of the variable-length queues is applied or distributed only for fixed limited time(s) to corresponding successive cells of each of the successive memory channels so as to distribute these time-bounded inputs in striped fashion across the memory space of the channels.
- every memory channel or bank receives data in about the same number of data cells, though arrival time is traffic dependent; and this, whether there is a data burst or the data is distributed equally throughout the period.
- Two exemplary (and extreme condition) traffic scenarios may be considered.
- all traffic streams from the line cards may be destined to one queue. Since the cell addresses are assigned continually, all the memory channels will absorb a data burst. There will be no accumulation in any FIFO, provided the aggregation of bandwidth to memory is made to match the input bandwidth.
- all the cells may happen to end on the same memory channel.
- the FIFO at the front of that memory channel will absorb the burst; and the next burst to come along, will move to the next memory channel.
- the depth of the FIFOs is set at about the number of queues supported by the system, and the aggregated bandwidth between the FIFOs in the memory channels is adjusted, as indicated previously, at least to match the input bandwidth.
- the bandwidth can be assigned and guaranteed to designated users. If a predetermined assigned depth is exceeded by a user, such excess is stored in available unoccupied shared memory and may be additionally charged for, to that user.
- FIG. 2 illustrates the read path architecture of the invention for use with the write path system of FIG. 1 , providing for every line card, a corresponding FIFO that is able to draw from the shared memory and at the full bandwidth of the shared memory in a TDM type fashion.
Abstract
Description
Claims (24)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/941,144 US6999464B2 (en) | 2001-08-28 | 2001-08-28 | Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor |
CA002459001A CA2459001A1 (en) | 2001-08-28 | 2002-07-04 | Shared memory data switching |
PCT/IB2002/002751 WO2003024033A1 (en) | 2001-08-28 | 2002-07-04 | Shared memory data switching |
IL16064402A IL160644A0 (en) | 2001-08-28 | 2002-07-04 | Shared memory data switching |
JP2003527955A JP2005503071A (en) | 2001-08-28 | 2002-07-04 | Shared memory data exchange |
KR10-2004-7003059A KR20040044519A (en) | 2001-08-28 | 2002-07-04 | Shared memory data switching |
CNA02817058XA CN1550091A (en) | 2001-08-28 | 2002-07-04 | Shared memory data switching |
EP02743529A EP1423942A1 (en) | 2001-08-28 | 2002-07-04 | Shared memory data switching |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/941,144 US6999464B2 (en) | 2001-08-28 | 2001-08-28 | Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030043828A1 US20030043828A1 (en) | 2003-03-06 |
US6999464B2 true US6999464B2 (en) | 2006-02-14 |
Family
ID=25475994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/941,144 Expired - Lifetime US6999464B2 (en) | 2001-08-28 | 2001-08-28 | Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor |
Country Status (8)
Country | Link |
---|---|
US (1) | US6999464B2 (en) |
EP (1) | EP1423942A1 (en) |
JP (1) | JP2005503071A (en) |
KR (1) | KR20040044519A (en) |
CN (1) | CN1550091A (en) |
CA (1) | CA2459001A1 (en) |
IL (1) | IL160644A0 (en) |
WO (1) | WO2003024033A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012512215A (en) * | 2008-12-17 | 2012-05-31 | ロレアル | Cosmetic method and composition for controlling skin browning induced by UV irradiation |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080028157A1 (en) * | 2003-01-13 | 2008-01-31 | Steinmetz Joseph H | Global shared memory switch |
WO2005101763A1 (en) * | 2004-04-12 | 2005-10-27 | Integrated Device Technology, Inc. | Method and apparatus for forwarding bursty data |
US7940662B2 (en) * | 2004-04-12 | 2011-05-10 | Integrated Device Technology, Inc. | Method and apparatus for forwarding bursty data |
US20060039284A1 (en) * | 2004-04-12 | 2006-02-23 | Integrated Device Technology, Inc. | Method and apparatus for processing a complete burst of data |
US7983295B2 (en) * | 2005-10-28 | 2011-07-19 | Broadcom Corporation | Optimizing packet queues for channel bonding over a plurality of downstream channels of a communications management system |
US8644140B2 (en) | 2009-09-09 | 2014-02-04 | Mellanox Technologies Ltd. | Data switch with shared port buffers |
CN101741720B (en) * | 2009-11-06 | 2013-01-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
US8699491B2 (en) | 2011-07-25 | 2014-04-15 | Mellanox Technologies Ltd. | Network element with shared buffers |
US9130885B1 (en) | 2012-09-11 | 2015-09-08 | Mellanox Technologies Ltd. | End-to-end cache for network elements |
US9582440B2 (en) | 2013-02-10 | 2017-02-28 | Mellanox Technologies Ltd. | Credit based low-latency arbitration with data transfer |
US8989011B2 (en) | 2013-03-14 | 2015-03-24 | Mellanox Technologies Ltd. | Communication over multiple virtual lanes using a shared buffer |
US8966164B1 (en) * | 2013-09-27 | 2015-02-24 | Avalanche Technology, Inc. | Storage processor managing NVME logically addressed solid state disk array |
WO2014146302A1 (en) * | 2013-03-22 | 2014-09-25 | 华为技术有限公司 | Uplink data transmission method and apparatus |
US9641465B1 (en) | 2013-08-22 | 2017-05-02 | Mellanox Technologies, Ltd | Packet switch with reduced latency |
US9548960B2 (en) | 2013-10-06 | 2017-01-17 | Mellanox Technologies Ltd. | Simplified packet routing |
US9325641B2 (en) * | 2014-03-13 | 2016-04-26 | Mellanox Technologies Ltd. | Buffering schemes for communication over long haul links |
US9584429B2 (en) | 2014-07-21 | 2017-02-28 | Mellanox Technologies Ltd. | Credit based flow control for long-haul links |
JP2016100674A (en) * | 2014-11-19 | 2016-05-30 | 富士通株式会社 | Transmission device |
CN109062661B (en) * | 2018-07-10 | 2021-10-26 | 中国电子科技集团公司第三十八研究所 | Multi-channel arbitration circuit of online simulation debugger and scheduling method thereof |
US10951549B2 (en) | 2019-03-07 | 2021-03-16 | Mellanox Technologies Tlv Ltd. | Reusing switch ports for external buffer network |
CN111078150A (en) * | 2019-12-18 | 2020-04-28 | 成都定为电子技术有限公司 | High-speed storage equipment and uninterrupted capacity expansion method |
US11558316B2 (en) | 2021-02-15 | 2023-01-17 | Mellanox Technologies, Ltd. | Zero-copy buffering of traffic of long-haul links |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4644529A (en) * | 1985-08-02 | 1987-02-17 | Gte Laboratories Incorporated | High-speed switching processor for a burst-switching communications system |
US4748618A (en) * | 1986-05-21 | 1988-05-31 | Bell Communications Research, Inc. | Telecommunications interface |
US6622232B2 (en) * | 2001-05-18 | 2003-09-16 | Intel Corporation | Apparatus and method for performing non-aligned memory accesses |
US6621828B1 (en) * | 1999-12-01 | 2003-09-16 | Cisco Technology, Inc. | Fused switch core and method for a telecommunications node |
US6822960B1 (en) * | 1999-12-01 | 2004-11-23 | Cisco Technology, Inc. | Asynchronous transfer mode (ATM) switch and method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69021213T2 (en) * | 1990-12-20 | 1996-02-29 | Ibm | Modular buffer storage for a packet switched network. |
DE69841486D1 (en) * | 1997-05-31 | 2010-03-25 | Texas Instruments Inc | Improved packet switching |
-
2001
- 2001-08-28 US US09/941,144 patent/US6999464B2/en not_active Expired - Lifetime
-
2002
- 2002-07-04 JP JP2003527955A patent/JP2005503071A/en active Pending
- 2002-07-04 CN CNA02817058XA patent/CN1550091A/en active Pending
- 2002-07-04 WO PCT/IB2002/002751 patent/WO2003024033A1/en active Search and Examination
- 2002-07-04 EP EP02743529A patent/EP1423942A1/en not_active Withdrawn
- 2002-07-04 IL IL16064402A patent/IL160644A0/en unknown
- 2002-07-04 KR KR10-2004-7003059A patent/KR20040044519A/en not_active Application Discontinuation
- 2002-07-04 CA CA002459001A patent/CA2459001A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4644529A (en) * | 1985-08-02 | 1987-02-17 | Gte Laboratories Incorporated | High-speed switching processor for a burst-switching communications system |
US4748618A (en) * | 1986-05-21 | 1988-05-31 | Bell Communications Research, Inc. | Telecommunications interface |
US6621828B1 (en) * | 1999-12-01 | 2003-09-16 | Cisco Technology, Inc. | Fused switch core and method for a telecommunications node |
US6822960B1 (en) * | 1999-12-01 | 2004-11-23 | Cisco Technology, Inc. | Asynchronous transfer mode (ATM) switch and method |
US6622232B2 (en) * | 2001-05-18 | 2003-09-16 | Intel Corporation | Apparatus and method for performing non-aligned memory accesses |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012512215A (en) * | 2008-12-17 | 2012-05-31 | ロレアル | Cosmetic method and composition for controlling skin browning induced by UV irradiation |
Also Published As
Publication number | Publication date |
---|---|
JP2005503071A (en) | 2005-01-27 |
CA2459001A1 (en) | 2003-03-20 |
IL160644A0 (en) | 2004-07-25 |
US20030043828A1 (en) | 2003-03-06 |
KR20040044519A (en) | 2004-05-28 |
EP1423942A1 (en) | 2004-06-02 |
WO2003024033A1 (en) | 2003-03-20 |
CN1550091A (en) | 2004-11-24 |
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