US7047470B2 - Flexible and extensible implementation of sharing test pins in ASIC - Google Patents
Flexible and extensible implementation of sharing test pins in ASIC Download PDFInfo
- Publication number
- US7047470B2 US7047470B2 US10/441,000 US44100003A US7047470B2 US 7047470 B2 US7047470 B2 US 7047470B2 US 44100003 A US44100003 A US 44100003A US 7047470 B2 US7047470 B2 US 7047470B2
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- US
- United States
- Prior art keywords
- cambist
- library
- test
- unknown
- asic
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- Expired - Fee Related, expires
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Definitions
- the present invention relates generally to the design of application specific integrated circuits (ASIC).
- LSI Logic the Assignee of the present invention, provides a design system called “FlexStream” (which is a registered trademark of LSI Logic (all rights reserved)).
- the FlexStream® design system is configured such that an ASIC designer uses certain third party tools (i.e., implementation, verification and manufacturing test tools) to design an ASIC, and uses LSI Logic's Flex Stream® design system to analyze the design.
- the FlexStream® design system is a fully integrated environment for complex ASIC and System-on-Chip (SoC) design. It provides a complete system-to-silicon methodology that enables first-pass silicon success to meet tight time-to-market windows.
- SoC System-on-Chip
- the FlexStream® design system is an integration of best-in-class LSI Logic and third party EDA tools. This approach provides an ASIC designer with the flexibility to use their preferred tools. The ASIC designer designs with efficiency and confidence because LSI Logic's strong partnerships with EDA vendors assure that third party tools are well-integrated into the FlexStream® environment.
- the FlexStream® design system provides a link between all the design components—process technology, libraries, memories, CoreWare functions, advance packaging solutions, and manufacturing, test and assembly. While the FlexStream® design system which is currently available provides many advantages, it does not define a system or provide the necessary guidelines or information needed to effectively verify new test structures of an ASIC.
- test structures which can be introduced in a design. Each test structure has its own set of controls for testing. Each time a new test structure is introduced, a great amount of development and verification must occur before the test structure can be made available to the public. If the introduction of new test structures continues to grow at the current pace, the solutions for testing these test structures will become obsolete and virtually impossible to use.
- Each test structure includes test pins (input and output) which need to be controlled or observed from the top level functional pins during manufacturing tests. Thus, the test pins and functional pins are shared. In order to accomplish sharing of the test pins and functional pins, certain structures, for example, boundary scan cells must be controlled. Another problem encountered is that with the growing number to test pins, a sufficient number of functional ports may not exist for sharing. Each test pin is associated with one or more control pin(s).
- test structures are designed through the use of software.
- using software to design the test structures requires a massive amount of development and is very error prone.
- Another problem encountered is that, if a designer creates his own test structures, it is almost impossible to verify the custom test structures along with standard test structures.
- Such testing of the controls would require communication between the development organization and users. Generally, the time needed for this communication is very lengthy and users do not receive the information they need in a timely fashion.
- test pins need to be combined for test purposes. With approximately 40 different types of test pins, implementing the combinations of test pins would be overwhelming.
- An object of an embodiment of the present invention is to allow changes to the controls and definitions of the existing test structures.
- Another object of an embodiment of the present invention to provide a library with information regarding which test pins can be combined for sharing with a functional port for testing.
- Yet another object of an embodiment of the present invention is to provide the customer with information regarding the optimization of the number of functional ports for sharing test pins.
- a further object of an embodiment of the present invention is to allow customized test structures to be easily introduced.
- Still a further object of an embodiment of the present invention is to reduce the amount of time required to develop and verify an ASIC test structure.
- an embodiment of the present invention provides a library which can be used to verify test structures of an ASIC.
- the library allows changes to the controls of the test structures and provides information regarding which test pins can be combined for sharing with a functional port for verification.
- the library allows a user to modify the library by either adding library information or rewriting library information so as to create a custom test structure.
- FIG. 1 illustrates LSI Logic's FlexStream® design system and its association with third party tools
- FIG. 2 illustrates a library which is in accordance with an embodiment of the present invention.
- FIG. 3 illustrates a method which is in accordance with an embodiment of the present invention.
- the embodiment provides a library 10 which includes the different types of information.
- the library 10 includes control information 12 .
- the control information relates to standard test structures. This information can be easily changed by the library's user.
- the library includes pin combination information 14 which specifies how different types and similar types of test pins can be combined.
- the library 10 also includes port sharing information 16 which specifies what kind of ports can not be shared for certain test pins and thus assists the user in optimizing the number of functional ports for sharing test pins.
- the library 10 includes customer/user information 18 .
- the customer/user information 18 defines customer test structures added to the library by the user.
- the library 10 is built into the software tool, such as, for example, LSIVEGA.
- the library is provided within a design system. For example, it may be provided as a library in LSI Logic's FlexStream® design system (see FIG. 1 ).
- FIG. 3 A method in accordance with an embodiment of the present invention is shown in FIG. 3 and includes the step 60 of reading the library 10 (illustrated in FIG. 2 ).
- the library 10 can then be used to determine the test structure controls and change the controls if desired as represented by step 62 , FIG. 3 .
- the library is then used to determine which test pins can be combined for sharing with a common functional port for verification of the test structure as represented by step 64 of FIG. 3 .
- the library is then used to determine which ports can be shared, as represented by step 66 of FIG. 3 .
- the user can add a custom test structure to the library, as represented by step 68 , FIG. 3 .
- the test structure is verified as represented by step 70 , FIG. 3 .
- the invention also provides the ability to easily change the controls and other definitions of the existing test structure in the test mode.
- the invention provides a flexible way to combine different types or similar types of test pins together for sharing with a common functional port for testing purposes. The manner in which different types and similar types of pins can be combined is easily specified and optimization of the number of functional ports for sharing test pins is also easily specified.
- the invention provides the ability to easily add new structures for testing. Portions of the library (vega.init) can be overwritten or new data can be added to the library when the tool is being run at the customer's site. For each type of test pin, approximately 5–10 lines of text need to be written in the format of the vega.init file. An example of that format is listed below with some sample examples for custom test structures.
- the new test structures can be tested without requesting changes in tools and therefore is easily accomplished by the various organizations simply by creating a custom library file, by adding lines of code in the library format, and running the existing tools within the test framework(FAST).
- the invention allows for the introduction of new test structures with out requiring months of development as typically required in previous methods. In the event custom test structures are added to the design, the amount of time spent in verification is shifted from development team to the customer.
Abstract
Description
technology_token { |
cambist_buf_sel_pin | unknown “LSI_CAMBIST_BUF_SEL” | |
cambist_clk_pin | unknown “LSI_CAMBIST_CLK” | |
cambist_monitor_sel_pin | unknown “LSI_CAMBIST_MONITOR_SEL” | |
cambist_rst_pin | unknown “LSI_CAMBIST_RST” | |
cambist_sel_pin | unknown “LSI_CAMBIST_SEL” | |
cambist_test_seq_pin | unknown “LSI_CAMBIST_TEST_SEQ” | |
cambist_done_pin | unknown “LSI_CAMBIST_DONE” | |
cambist_error_pin | unknown “LSI_CAMBIST_ERROR” | |
cambist_monitor_pin | unknown “LSI_CAMBIST_MONITOR” | |
cambist_test_done_pin | unknown “LSI_CAMBIST_TEST_DONE” | |
cambist_en_pin | unknown “LSI_CAMBIST_EN” | |
cambist_en_net | unknown “net_LSI_CAMBIST_EN” | |
iogen_shared_pin_by_name | unknown { scan_clock scan_in scan_out scan_set |
scan_reset scan_setreset scan_setn | |
scan_resetn scan_setresetn | |
bz_clock bz_resetn | |
pll_ref_clk pll_resetn pll_t0 pll_t1 | |
pll_lock pll_f0 pll_f1 | |
lbram_scan_clock lbram_scan_in | |
lbram_scan_out | |
mbisrc_flarescan_in mbisr_scan_in | |
mbisr_scan_out mbist_cmp_stat | |
test_cw_in mbistc_clock | |
cambist_buf_sel cambist_clk | |
cambist_monitor_sel cambist_rst | |
cambist_sel cambist_test_seq | |
cambist_done cambist_error | |
cambist_monitor cambist_test_done } |
iogen_shared_types_pins | unknown { poweron_clk scan_clock bz_clock |
pll_ref_clk lbram_scan_clock | |
mbistc_clock mbist_clock |
scan_set scan_reset scan_setreset | |
scan_setn scan_resetn scan_setresetn | |
bz_resetn pll_resetn | |
cw_tap_tdi cw_tap_tck cw_tap_tms | |
cw_tap_trstn |
pll_t0 pll_t1 pll_f0 pll_f1 |
pll_lock scan_in scan_out fuse_scan_in | |
fuse_scan_out mbisr_scan_in | |
mbisr_scan_out lbram_scan_in | |
lbram_scan_out mbisrc_flarescan_in | |
mbisr_flarescanout mbist_cmp_stat | |
test_cw_in test_cw_out |
cambist_buf_sel cambist_clk | |
cambist_monitor_sel cambist_rst | |
cambist_sel cambist_test_seq | |
cambist_done cambist_error | |
cambist_monitor cambist_test_done } |
cambist_buf_sel_dir | unknown “IN” | |
cambist_clk_dir | unknown “IN” | |
cambist_monitor_sel_dir | unknown “IN” | |
cambist_rst_dir | unknown “IN” | |
cambist_sel_dir | unknown “IN” | |
cambist_test_seq_dir | unknown “IN” | |
cambist_done_dir | unknown “OUT” | |
cambist_error_dir | unknown “OUT” | |
cambist_monitor_dir | unknown “OUT” | |
cambist_test_done_dir | unknown “OUT” | |
cambist_buf_sel_order | unknown “35” | |
cambist_clk_order | unknown “36” | |
cambist_monitor_sel_order | unknown “37” | |
cambist_rst_order | unknown “38” | |
cambist_sel_order | unknown “39” | |
cambist_test_seq_order | unknown “40” | |
cambist_done_order | unknown “41” | |
cambist_error_order | unknown “42” | |
cambist_monitor_order | unknown “43” | |
cambist_test_done_order | unknown “44” | |
cambist_buf_sel_direction | unknown { IN INOUT } | |
cambist_clk_direction | unknown { IN INOUT } | |
cambist_monitor_sel_direction | unknown { IN INOUT } | |
cambist_rst_direction | unknown { IN INOUT } | |
cambist_sel_direction | unknown { IN INOUT } | |
cambist_test_seq_direction | unknown { IN INOUT } | |
cambist_done_direction | unknown { OUT INOUT } | |
cambist_error_direction | unknown { OUT INOUT } | |
cambist_monitor_direction | unknown { OUT INOUT } | |
cambist_test_done_direction | unknown { OUT INOUT } | |
cambist_buf_sel_default_combine | gflxp { } | |
cambist_clk_default_combine | gflxp { } | |
cambist_monitor_sel_default_combine | gflxp { } | |
cambist_rst_default_combine | gflxp { } | |
cambist_sel_default_combine | gflxp { } | |
cambist_test_seq_default_combine | gflxp { } | |
cambist_done_default_combine | gflxp { } | |
cambist_error_default_combine | gflxp { } | |
cambist_monitor_default_combine | gflxp { } | |
cambist_test_done_default_combine | gflxp { } | |
cambist_buf_sel_combine | gflxp { } | |
cambist_clk_combine | gflxp { } | |
cambist_monitor_sel_combine | gflxp { } | |
cambist_rst_combine | gflxp { } | |
cambist_sel_combine | gflxp { } | |
cambist_test_seq_combine | gflxp { } | |
cambist_done_combine | gflxp { } | |
cambist_error_combine | gflxp { } | |
cambist_monitor_combine | gflxp { } | |
cambist_test_done_combine | gflxp { } | |
cambist_buf_sel_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_clk_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_monitor_sel_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_rst_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_sel_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_test_seq_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_done_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_error_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_monitor_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_test_done_port_conflict | unknown { CLOCK ASYNC_SETN ASYNC_SET |
ASYNC_RESET ASYNC_RESETN } |
cambist_buf_sel_testdef | unknown { } | |
cambist_clk_testdef | unknown { } | |
cambist_monitor_sel_testdef | unknown { } | |
cambist_rst_testdef | unknown { } | |
cambist_sel_testdef | unknown { } | |
cambist_test_seq_testdef | unknown { } | |
cambist_done_testdef | unknown { } | |
cambist_error_testdef | unknown { } | |
cambist_monitor_testdef | unknown { } | |
cambist_test_done_testdef | unknown { } |
cambist_buf_sel_in_or_cntrl | unknown “cambist_en” | |
cambist_clk_in_or_cntrl | unknown “cambist_en” | |
cambist_monitor_sel_in_or_cntrl | unknown “cambist_en” | |
cambist_rst_in_or_cntrl | unknown “cambist_en” | |
cambist_sel_in_or_cntrl | unknown “cambist_en” | |
cambist_test_seq_in_or_cntrl | unknown “cambist_en” | |
cambist_done_in_or_cntrl | unknown “cambist_en” | |
cambist_error_in_or_cntrl | unknown “cambist_en” | |
cambist_monitor_in_or_cntrl | unknown “cambist_en” | |
cambist_test_done_in_or_cntrl | unknown “cambist_en” | |
cambist_buf_sel_out_or_cntrl | unknown “cambist_en” | |
cambist_clk_out_or_cntrl | unknown “” | |
cambist_monitor_sel_out_or_cntrl | unknown “cambist_en” | |
cambist_rst_out_or_cntrl | unknown “” | |
cambist_sel_out_or_cntrl | unknown “cambist_en” | |
cambist_test_seq_out_or_cntrl | unknown “cambist_en” |
cambist_done_out_or_cntrl | unknown “cambist_en” | |
cambist_error_out_or_cntrl | unknown “cambist_en” | |
cambist_monitor_out_or_cntrl | unknown “cambist_en” | |
cambist_test_done_out_or_cntrl | unknown “cambist_en” | |
cambist_buf_sel_out_and_cntrl | unknown “cambist_en” | |
cambist_clk_out_and_cntrl | unknown “” | |
cambist_monitor_sel_out_and_cntrl | unknown “cambist_en” | |
cambist_rst_out_and_cntrl | unknown “” | |
cambist_sel_out_and_cntrl | unknown “cambist_en” | |
cambist_test_seq_out_and_cntrl | unknown “cambist_en” | |
cambist_done_out_and_cntrl | unknown “cambist_en” | |
cambist_error_out_and_cntrl | unknown “cambist_en” | |
cambist_monitor_out_and_cntrl | unknown “cambist_en” | |
cambist_test_done_out_and_cntrl | unknown “cambist_en” |
cambist_buf_sel_input_enable_or_cntrl | unknown “1” | |
cambist_clk_input_enable_or_cntrl | unknown “” | |
cambist_monitor_sel_input_enable_or_cntrl | unknown “1” | |
cambist_rst_input_enable_or_cntrl | unknown “” | |
cambist_sel_input_enable_or_cntrl | unknown “1” | |
cambist_test_seq_input_enable_or_cntrl | unknown “1” | |
cambist_buf_sel_tn_and_gate_control | unknown “” | |
cambist_clk_tn_and_gate_control | unknown “cambist_en” | |
cambist_monitor_sel_tn_and_gate_control | unknown “” | |
cambist_rst_tn_and_gate_control | unknown “cambist_en” | |
cambist_sel_tn_and_gate_control | unknown “” | |
cambist_test_seq_tn_and_gate_control | unknown “” | |
cambist_buf_sel_fc_gain_mux_control | unknown “” | |
cambist_clk_fc_gain_mux_control | unknown “cambist_en” | |
cambist_monitor_sel_fc_gain_mux_control | unknown “” | |
cambist_rst_fc_gain_mux_control | unknown “cambist_en” | |
cambist_sel_fc_gain_mux_control | unknown “” | |
cambist_test_seq_fc_gain_mux_control | unknown “” | |
cambist_done_output_enable_or_cntrl | unknown “1” | |
cambist_error_output_enable_or_cntrl | unknown “1” | |
cambist_monitor_output_enable_or_cntrl | unknown “1” | |
cambist_test_done_output_enable_or_cntrl | unknown “1” | |
cambist_done_tn_or_gate_cntrl | unknown “cambist_en” | |
cambist_error_tn_or_gate_cntrl | unknown “cambist_en” | |
cambist_monitor_tn_or_gate_cntrl | unknown “cambist_en” | |
cambist_test_done_tn_or_gate_cntrl | unknown “cambist_en” |
} |
Test structures come from a variety of organizations and implementation of the test structures can be accomplished in a matter of minutes. The new test structures can be tested without requesting changes in tools and therefore is easily accomplished by the various organizations simply by creating a custom library file, by adding lines of code in the library format, and running the existing tools within the test framework(FAST). Thus, the invention allows for the introduction of new test structures with out requiring months of development as typically required in previous methods. In the event custom test structures are added to the design, the amount of time spent in verification is shifted from development team to the customer.
Claims (16)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/441,000 US7047470B2 (en) | 2003-04-16 | 2003-05-19 | Flexible and extensible implementation of sharing test pins in ASIC |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/417,007 US7284211B2 (en) | 2003-04-16 | 2003-04-16 | Extensible IO testing implementation |
US10/441,000 US7047470B2 (en) | 2003-04-16 | 2003-05-19 | Flexible and extensible implementation of sharing test pins in ASIC |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/417,007 Continuation-In-Part US7284211B2 (en) | 2003-04-16 | 2003-04-16 | Extensible IO testing implementation |
Publications (2)
Publication Number | Publication Date |
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US20040210806A1 US20040210806A1 (en) | 2004-10-21 |
US7047470B2 true US7047470B2 (en) | 2006-05-16 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/441,000 Expired - Fee Related US7047470B2 (en) | 2003-04-16 | 2003-05-19 | Flexible and extensible implementation of sharing test pins in ASIC |
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US (1) | US7047470B2 (en) |
Families Citing this family (1)
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US7490307B2 (en) * | 2006-06-29 | 2009-02-10 | Lsi Corporation | Automatic generating of timing constraints for the validation/signoff of test structures |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6499125B1 (en) * | 1998-11-24 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Method for inserting test circuit and method for converting test data |
US6557153B1 (en) * | 2000-11-15 | 2003-04-29 | Reshape, Inc. | Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist |
US6678875B2 (en) * | 2002-01-25 | 2004-01-13 | Logicvision, Inc. | Self-contained embedded test design environment and environment setup utility |
US6836872B2 (en) * | 2002-09-24 | 2004-12-28 | Intel Corporation | On-chip testing of integrated circuits |
-
2003
- 2003-05-19 US US10/441,000 patent/US7047470B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6499125B1 (en) * | 1998-11-24 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Method for inserting test circuit and method for converting test data |
US6557153B1 (en) * | 2000-11-15 | 2003-04-29 | Reshape, Inc. | Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist |
US6564363B1 (en) * | 2000-11-15 | 2003-05-13 | Reshape, Inc. | Method and system for implementing a graphical user interface for defining and linking multiple attach points for multiple blocks of an integrated circuit netlist |
US6678875B2 (en) * | 2002-01-25 | 2004-01-13 | Logicvision, Inc. | Self-contained embedded test design environment and environment setup utility |
US6836872B2 (en) * | 2002-09-24 | 2004-12-28 | Intel Corporation | On-chip testing of integrated circuits |
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Publication number | Publication date |
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US20040210806A1 (en) | 2004-10-21 |
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Legal Events
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