US7082557B2 - High speed serial interface test - Google Patents
High speed serial interface test Download PDFInfo
- Publication number
- US7082557B2 US7082557B2 US10/457,850 US45785003A US7082557B2 US 7082557 B2 US7082557 B2 US 7082557B2 US 45785003 A US45785003 A US 45785003A US 7082557 B2 US7082557 B2 US 7082557B2
- Authority
- US
- United States
- Prior art keywords
- output stream
- output
- pseudo
- serial interface
- scrambler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
Definitions
- the present invention pertains to communication devices and specifically to serial communications devices with scramblers and de-scramblers.
- High speed serial communications protocols are operating at higher and higher speeds. It may become very difficult for test equipment to effectively test a serial communications device when the device is operating at full speed for a number of reasons, including the difficulty of providing an input stream and analyzing the stream at a speed that approaches the normal operating speed of the serial interface.
- the present invention overcomes the disadvantages and limitations of the prior art by providing a system and method for testing a high speed, two-way serial interface using a series of pseudo-random characters that is generated by a portion of the serial interface itself.
- the input word is then repeatedly input into a scrambler that creates a pseudo-random number from the input word.
- the pseudo-random number is encoded and sent to a transceiver wherein the pseudo-random number is looped back through a decoder and a de-scrambler.
- the resultant word is compared to the input word to determine if an error has occurred in the transmission.
- the testing may occur at the full speed of the interface and the interface itself may have the capability of comparing the sent and received words without employing external test equipment.
- two or more input words may be stored in various registers and sequentially or separately sent through the interface.
- Various portions of the serial interface may be turned on and off to facilitate debugging and testing of the interface.
- the present invention may therefore comprise a method of testing a serial interface comprising: storing an output word into a first register; creating an output stream by repeatedly recalling the output word from the first register; passing the output stream through a scrambler to create a first pseudo-random sequence within the output stream; passing the output stream through a transmitter; looping the output stream back into a receiver; passing the output stream through a descrambler to descramble the first pseudo-random sequence within the output stream to generate multiple input words; comparing each of the multiple input words to the output word in the first register to determine any errors; storing the errors into an error register; and evaluating the performance of the serial interface by at least in part evaluating the errors in the error register.
- the present invention may further comprise a serial interface with internal testing comprising: a register capable of storing an output word; a sequencer capable of recalling the output word from the register to create an output stream; a scrambler capable of receiving the output stream and scrambling the output stream to create a pseudo-random sequence within the output stream; a transmitter capable of transmitting the output stream on an output line; a receiver capable of receiving the output stream on an input line; a loop back path capable of switching the output line to the input line such that the transmitter and the receiver are in communication; a descrambler capable of receiving the output stream and descrambling the pseudo-random sequence to generate multiple input words; and a comparator capable of comparing each of the multiple input words with the output word stored in the register, the comparator further capable of detecting an error if one of the input words is not the same as the output word and logging the error.
- a serial interface with internal testing comprising: a register capable of storing an output word; a sequencer capable of recalling the output word
- the advantages of the present invention are that high speed testing of complex serial interfaces may be performed with no external test equipment or external sources of data. Because no external test equipment is required, no performance degradation or other adverse effects prohibit full speed operation of the interface.
- FIG. 1 is an illustration of an embodiment of the present invention showing a serial interface with a built in self-test.
- FIG. 2 is an illustration of an embodiment of the present invention showing a serial interface with a built in self test, with more detail than in FIG. 1 .
- FIG. 3 is an illustration of an embodiment of the present invention showing a method for testing a serial interface.
- FIG. 1 illustrates an embodiment 100 of the present invention showing a serial interface with a built-in self-test apparatus.
- a controller 102 communicates with a set of registers 104 to retrieve a word or set of words.
- the controller 102 may send those words repeatedly through a transmit path 106 , a switchable loopback path 108 , and a receive path 114 to a comparator 116 .
- the comparator 116 may compare the received series of words with the initial words found in the registers 104 .
- the embodiment 100 enables a repeated set of words to exercise all of the transmit and receive portions of the interface at the highest speed possible because no external test equipment is required.
- the exercising of an interface may require a long string of data that is supplied at one end of the interface and transmitted through the interface.
- the present invention only uses a series of repeated words that are stored in the register 104 , thus severely eliminating the amount of data required to exercise the interface and making the comparator 116 much simpler.
- Some standardized serial interfaces, such as Serial ATA and Serial Attached SCSI have an internal scrambler and descrambler capability. In such interfaces, the transmitted stream undergoes a polynomial scrambling algorithm that is synchronized with a descrambler on the receiving end.
- One benefit of such a scramble/descramble system is that repeated data may not cause resonance or other noise problems when transmitted.
- the scrambler/descrambler system may allow a pseudo-random data stream to be generated from a simple input that is repeated.
- the pseudo-random data stream has the benefit that it is repeatable in that the same data stream may be repeated to duplicate a previous test, for example.
- the descrambled data is merely a repeated word that should be identical to the input word stored in the register 104 . This allows the comparator 116 to be a very simple operation.
- FIG. 2 illustrates a more detailed embodiment 200 of the present invention showing a serial interface with a built in self test.
- a controller 202 communicates with the registers 204 to receive a word or set of words to create a repeating output stream 206 .
- the output stream 206 is fed into the transmit path 208 that is composed of a scrambler 210 with a scrambler bypass 212 , an encoder 214 and an encoder bypass 216 , and a transmitter 218 .
- the output signal passes through a switched loopback path 224 or may optionally be sent via the normal transmit line 220 and received via the normal receive line 222 .
- the switched loopback path 224 sends the transmitted signal back into the receive path 226 of the serial interface 200 .
- the receive path 226 is comprised of a receiver 228 , a decoder 230 and a decoder bypass 232 , a descrambler 234 and a descrambler bypass 236 .
- the resultant signal is passed through a comparator 238 that compares the incoming, decoded signal with the words contained in the registers 204 .
- the results 240 of the comparator may be read by the controller 202 .
- the embodiment 200 may use the function of the scrambler 210 and descrambler 234 to create a pseudo-random sequence of data that may be sent out the transmit path 208 and received by the receive path 226 at the full speed of the interface 200 . In this manner, each component that may be necessary to transmit and receive data may be fully exercised and thereby tested.
- Various bypass switches 212 , 216 , 232 , and 236 allow some functionality to be switched in and out of the device to aid troubleshooting.
- the circuitry for the serial interface 200 may be constructed on a single integrated circuit chip.
- the switched loopback paths 224 may be switchable circuits within the chip that allow the chip to perform a self test without any external signal paths.
- the switched loopback paths 224 may be an external loopback that is mechanically attached to a device such as a computer or peripheral device for the purposes of performing a loopback test.
- the switched loopback paths 224 may be implemented as an electronically switchable path that is implemented on a printed circuit board.
- the scrambler 210 and descrambler 234 may be synchronized by sending a primitive or other command from the transmit path 208 to the receive path 226 .
- the primitive may cause both the scrambler 210 and descrambler 234 to synchronize such that the scrambled output signals may be correctly descrambled when received. Further, the primitive may allow the encoder 214 and decoder 230 to similarly synchronize.
- the scrambler 210 may be fed an output stream 206 that consists of repeated words contained in the registers 204 .
- the scrambler 210 may then create a sequence of data that does not repeat with the same frequency as the input stream. For example, the scrambler 210 may multiply the input word by a number that is generated by a polynomial expression wherein the input to the polynomial is incremented for each new word. In such a manner, the input word is changed into an output stream that does not have a very high frequency of repetition.
- the series is a pseudo-random sequence and affords the testing engineer the opportunity to subject the serial interface 200 to a thorough test.
- the output stream is a repeating sequence of the input words stored in the register 204 .
- the comparator 238 is only required to compare each received word with the transmitted word and does not necessarily need the ability to compare two long streams of data, as may be needed by other forms of testing the serial interface 200 . In this manner, the comparator 238 may be significantly more simple than would be required for other forms of testing while providing a much more complex and robust testing method.
- the controller 202 may be capable of sending several different words from the registers 204 .
- the controller 202 may be capable of sending the various words from the registers 204 in sequence. For example, a single word may be repeated over and over in one test. Four words may be sent in sequence and then the four word sequence may be repeated over and over in another test.
- the number of words used as a base sequence for the output stream 206 may be limited by the amount of storage in the registers 204 and the capability of the comparator 238 to perform the analysis.
- the results 240 may be sent to the controller 202 in several different forms.
- the comparator 238 may transmit a pass or fail signal for each word that is analyzed.
- the comparator 238 may transmit only a fail signal when an error occurs.
- the comparator 238 may transmit the entire failed word.
- Different forms of the output results 240 may be created by those skilled in the arts based on the specific methods of analysis, personal preferences, or other requirements while keeping within the spirit and intent of the present invention.
- FIG. 3 illustrates an embodiment 300 of the present invention showing a method for testing a serial interface.
- the process begins in block 302 .
- a primitive is sent between the scrambler and descrambler to synchronize those elements in block 304 .
- Words are read from the register and a repeating stream is created in block 306 .
- the stream is scrambled in block 308 and encoded in block 310 before being transmitted in block 312 and received in block 314 .
- the received stream is decoded in block 316 and descrambled in block 318 .
- the descrambled output stream is compared to the repeated input words in block 320 . If an error occurred in block 322 , the error is counted in block 324 and the process repeats in block 306 .
- the embodiment 300 illustrates a method wherein a pseudo-random testing sequence may be generated by using only one or more words stored in a register.
- the words are used to create a scrambled and encoded output that is pseudo-random and may thereby more fully exercise the serial interface at full speed. Not only are the transmit and receive functions of the interface are tested at full speed, but the scrambler and descrambler, and the encoder and decoder portions of the interface are tested at full speed.
- the steps of encoding and decoding the stream may not be included or may be switched out of the process.
- steps of encoding and decoding the stream may be temporarily switched off for troubleshooting or other testing that may be desired.
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/457,850 US7082557B2 (en) | 2003-06-09 | 2003-06-09 | High speed serial interface test |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/457,850 US7082557B2 (en) | 2003-06-09 | 2003-06-09 | High speed serial interface test |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040250187A1 US20040250187A1 (en) | 2004-12-09 |
US7082557B2 true US7082557B2 (en) | 2006-07-25 |
Family
ID=33490399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/457,850 Expired - Fee Related US7082557B2 (en) | 2003-06-09 | 2003-06-09 | High speed serial interface test |
Country Status (1)
Country | Link |
---|---|
US (1) | US7082557B2 (en) |
Cited By (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060107154A1 (en) * | 2004-10-29 | 2006-05-18 | Akash Bansal | Through-core self-test with multiple loopbacks |
US7301327B1 (en) * | 2003-05-23 | 2007-11-27 | Xilinx, Inc. | Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces |
US20100135309A1 (en) * | 2004-06-02 | 2010-06-03 | Standard Microsystems Corporation | System and Method for Transferring Non-Compliant Packetized and Streaming Data Into and From a Multimedia Device Coupled to a Network Across Which Compliant Data is Sent |
US8144606B1 (en) * | 2007-11-15 | 2012-03-27 | Marvell International Ltd. | Interfacing messages between a host and a network |
US20140344654A1 (en) * | 2013-05-20 | 2014-11-20 | SK Hynix Inc. | Semiconductor system |
US9547550B1 (en) * | 2015-07-07 | 2017-01-17 | Tidal Systems, Inc. | System and method for improved data maintenance in a flash drive |
US9692555B2 (en) | 2010-05-20 | 2017-06-27 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
US9806761B1 (en) | 2014-01-31 | 2017-10-31 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
US9819522B2 (en) | 2010-05-20 | 2017-11-14 | Kandou Labs, S.A. | Circuits for efficient detection of vector signaling codes for chip-to-chip communication |
US9832046B2 (en) | 2015-06-26 | 2017-11-28 | Kandou Labs, S.A. | High speed communications system |
US9838017B2 (en) | 2010-05-20 | 2017-12-05 | Kandou Labs, S.A. | Methods and systems for high bandwidth chip-to-chip communcations interface |
US9838234B2 (en) | 2014-08-01 | 2017-12-05 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US9852806B2 (en) | 2014-06-20 | 2017-12-26 | Kandou Labs, S.A. | System for generating a test pattern to detect and isolate stuck faults for an interface using transition coding |
US9893911B2 (en) | 2014-07-21 | 2018-02-13 | Kandou Labs, S.A. | Multidrop data transfer |
US9900186B2 (en) | 2014-07-10 | 2018-02-20 | Kandou Labs, S.A. | Vector signaling codes with increased signal to noise characteristics |
US9906358B1 (en) | 2016-08-31 | 2018-02-27 | Kandou Labs, S.A. | Lock detector for phase lock loop |
US9917711B2 (en) | 2014-06-25 | 2018-03-13 | Kandou Labs, S.A. | Multilevel driver for high speed chip-to-chip communications |
US9929818B2 (en) | 2010-05-20 | 2018-03-27 | Kandou Bus, S.A. | Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication |
CN107968732A (en) * | 2016-10-20 | 2018-04-27 | 联发科技股份有限公司 | Method and uniform protocol device from functional test is performed to uniform protocol device |
US9985634B2 (en) | 2010-05-20 | 2018-05-29 | Kandou Labs, S.A. | Data-driven voltage regulator |
US9985745B2 (en) | 2013-06-25 | 2018-05-29 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
US10003454B2 (en) | 2016-04-22 | 2018-06-19 | Kandou Labs, S.A. | Sampler with low input kickback |
US10003424B2 (en) | 2014-07-17 | 2018-06-19 | Kandou Labs, S.A. | Bus reversible orthogonal differential vector signaling codes |
US10003315B2 (en) | 2016-01-25 | 2018-06-19 | Kandou Labs S.A. | Voltage sampler driver with enhanced high-frequency gain |
US10020966B2 (en) | 2014-02-28 | 2018-07-10 | Kandou Labs, S.A. | Vector signaling codes with high pin-efficiency for chip-to-chip communication and storage |
US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US10057049B2 (en) | 2016-04-22 | 2018-08-21 | Kandou Labs, S.A. | High performance phase locked loop |
US10056903B2 (en) | 2016-04-28 | 2018-08-21 | Kandou Labs, S.A. | Low power multilevel driver |
US10091035B2 (en) | 2013-04-16 | 2018-10-02 | Kandou Labs, S.A. | Methods and systems for high bandwidth communications interface |
US10116468B1 (en) | 2017-06-28 | 2018-10-30 | Kandou Labs, S.A. | Low power chip-to-chip bidirectional communications |
US10153591B2 (en) | 2016-04-28 | 2018-12-11 | Kandou Labs, S.A. | Skew-resistant multi-wire channel |
US10200218B2 (en) | 2016-10-24 | 2019-02-05 | Kandou Labs, S.A. | Multi-stage sampler with increased gain |
US10200188B2 (en) | 2016-10-21 | 2019-02-05 | Kandou Labs, S.A. | Quadrature and duty cycle error correction in matrix phase lock loop |
US10203226B1 (en) | 2017-08-11 | 2019-02-12 | Kandou Labs, S.A. | Phase interpolation circuit |
US10243765B2 (en) | 2014-10-22 | 2019-03-26 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
US10277431B2 (en) | 2016-09-16 | 2019-04-30 | Kandou Labs, S.A. | Phase rotation circuit for eye scope measurements |
US10326623B1 (en) | 2017-12-08 | 2019-06-18 | Kandou Labs, S.A. | Methods and systems for providing multi-stage distributed decision feedback equalization |
US10333741B2 (en) | 2016-04-28 | 2019-06-25 | Kandou Labs, S.A. | Vector signaling codes for densely-routed wire groups |
US10333749B2 (en) | 2014-05-13 | 2019-06-25 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
US10348436B2 (en) | 2014-02-02 | 2019-07-09 | Kandou Labs, S.A. | Method and apparatus for low power chip-to-chip communications with constrained ISI ratio |
US10355756B2 (en) | 2010-04-30 | 2019-07-16 | ECOLE POLYTECHNIQUE FéDéRALE DE LAUSANNE | Orthogonal differential vector signaling |
US10372665B2 (en) | 2016-10-24 | 2019-08-06 | Kandou Labs, S.A. | Multiphase data receiver with distributed DFE |
US10468078B2 (en) | 2010-05-20 | 2019-11-05 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication |
US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
US10638148B2 (en) | 2015-01-07 | 2020-04-28 | Renesas Electronics Corporation | Video encoding/decoding system and diagnosis method thereof |
US10666297B2 (en) | 2017-04-14 | 2020-05-26 | Kandou Labs, S.A. | Pipelined forward error correction for vector signaling code channel |
US10686583B2 (en) | 2017-07-04 | 2020-06-16 | Kandou Labs, S.A. | Method for measuring and correcting multi-wire skew |
US10693587B2 (en) | 2017-07-10 | 2020-06-23 | Kandou Labs, S.A. | Multi-wire permuted forward error correction |
US11356197B1 (en) | 2021-03-19 | 2022-06-07 | Kandou Labs SA | Error-tolerant forward error correction ordered set message decoder |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3446124B2 (en) * | 2001-12-04 | 2003-09-16 | 科学技術振興事業団 | Test method and test apparatus for semiconductor integrated circuit device having high-speed input / output device |
JP4273312B2 (en) * | 2003-06-18 | 2009-06-03 | 日本電気株式会社 | SIGNAL RELAYER, SWITCHING DEVICE AND METHOD FOR DETECTING CONNECTION RELATIONSHIP BETWEEN |
JP5179726B2 (en) * | 2006-06-27 | 2013-04-10 | マーベル ワールド トレード リミテッド | Semiconductor device |
US8386867B2 (en) | 2009-07-02 | 2013-02-26 | Silicon Image, Inc. | Computer memory test structure |
US8543873B2 (en) | 2010-01-06 | 2013-09-24 | Silicon Image, Inc. | Multi-site testing of computer memory devices and serial IO ports |
US8593305B1 (en) | 2011-07-05 | 2013-11-26 | Kandou Labs, S.A. | Efficient processing and detection of balanced codes |
US10587437B2 (en) * | 2013-06-10 | 2020-03-10 | Texas Instruments Incorporated | Link aggregator with universal packet scrambler apparatus and method |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4449247A (en) * | 1980-07-30 | 1984-05-15 | Harris Corporation | Local orderwire facility for fiber optic communication system |
US5031129A (en) * | 1989-05-12 | 1991-07-09 | Alcatel Na Network Systems Corp. | Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same |
US5539733A (en) * | 1993-11-15 | 1996-07-23 | Motorola, Inc. | Method for switching data flow in a fiber distributed interface (FDDI) system |
US20010043603A1 (en) * | 1999-07-27 | 2001-11-22 | Shaohua Yu | Interfacing apparatus and method for adapting Ethernet directly to physical channel |
US6542538B2 (en) * | 2000-01-10 | 2003-04-01 | Qualcomm Incorporated | Method and apparatus for testing wireless communication channels |
US20040030968A1 (en) * | 2002-08-07 | 2004-02-12 | Nong Fan | System and method for determining on-chip bit error rate (BER) in a communication system |
US20040068683A1 (en) * | 2002-10-02 | 2004-04-08 | Hoang Tuan M. | On-chip standalone self-test system and method |
US6961348B2 (en) * | 1999-07-14 | 2005-11-01 | Wuhan Research Institute Of Post And Telecommunications, M.I.I. | Data transmission apparatus and method for transmitting data between physical layer side device and network layer device |
US7007212B2 (en) * | 2002-03-14 | 2006-02-28 | Matsushita Electric Industrial Co., Ltd. | Transmission device, reception device, test circuit, and test method |
-
2003
- 2003-06-09 US US10/457,850 patent/US7082557B2/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4449247A (en) * | 1980-07-30 | 1984-05-15 | Harris Corporation | Local orderwire facility for fiber optic communication system |
US5031129A (en) * | 1989-05-12 | 1991-07-09 | Alcatel Na Network Systems Corp. | Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same |
US5539733A (en) * | 1993-11-15 | 1996-07-23 | Motorola, Inc. | Method for switching data flow in a fiber distributed interface (FDDI) system |
US6961348B2 (en) * | 1999-07-14 | 2005-11-01 | Wuhan Research Institute Of Post And Telecommunications, M.I.I. | Data transmission apparatus and method for transmitting data between physical layer side device and network layer device |
US20010043603A1 (en) * | 1999-07-27 | 2001-11-22 | Shaohua Yu | Interfacing apparatus and method for adapting Ethernet directly to physical channel |
US6542538B2 (en) * | 2000-01-10 | 2003-04-01 | Qualcomm Incorporated | Method and apparatus for testing wireless communication channels |
US20030131297A1 (en) * | 2000-01-10 | 2003-07-10 | Fischel Scott Eduard | Method and apparatus for testing wireless communication channels |
US7007212B2 (en) * | 2002-03-14 | 2006-02-28 | Matsushita Electric Industrial Co., Ltd. | Transmission device, reception device, test circuit, and test method |
US20040030968A1 (en) * | 2002-08-07 | 2004-02-12 | Nong Fan | System and method for determining on-chip bit error rate (BER) in a communication system |
US20040068683A1 (en) * | 2002-10-02 | 2004-04-08 | Hoang Tuan M. | On-chip standalone self-test system and method |
Cited By (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7301327B1 (en) * | 2003-05-23 | 2007-11-27 | Xilinx, Inc. | Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces |
US7420384B1 (en) | 2003-05-23 | 2008-09-02 | Xilinx, Inc. | Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces |
US20100135309A1 (en) * | 2004-06-02 | 2010-06-03 | Standard Microsystems Corporation | System and Method for Transferring Non-Compliant Packetized and Streaming Data Into and From a Multimedia Device Coupled to a Network Across Which Compliant Data is Sent |
US8606382B2 (en) * | 2004-06-02 | 2013-12-10 | Standard Microsystems Corporation | System and method for transferring non-compliant packetized and streaming data into and from a multimedia device coupled to a network across which compliant data is sent |
US7346819B2 (en) * | 2004-10-29 | 2008-03-18 | Rambus Inc. | Through-core self-test with multiple loopbacks |
US20060107154A1 (en) * | 2004-10-29 | 2006-05-18 | Akash Bansal | Through-core self-test with multiple loopbacks |
US8144606B1 (en) * | 2007-11-15 | 2012-03-27 | Marvell International Ltd. | Interfacing messages between a host and a network |
US10355756B2 (en) | 2010-04-30 | 2019-07-16 | ECOLE POLYTECHNIQUE FéDéRALE DE LAUSANNE | Orthogonal differential vector signaling |
US9819522B2 (en) | 2010-05-20 | 2017-11-14 | Kandou Labs, S.A. | Circuits for efficient detection of vector signaling codes for chip-to-chip communication |
US9692555B2 (en) | 2010-05-20 | 2017-06-27 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
US10044452B2 (en) | 2010-05-20 | 2018-08-07 | Kandou Labs, S.A. | Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication |
US9985634B2 (en) | 2010-05-20 | 2018-05-29 | Kandou Labs, S.A. | Data-driven voltage regulator |
US10468078B2 (en) | 2010-05-20 | 2019-11-05 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication |
US9838017B2 (en) | 2010-05-20 | 2017-12-05 | Kandou Labs, S.A. | Methods and systems for high bandwidth chip-to-chip communcations interface |
US9929818B2 (en) | 2010-05-20 | 2018-03-27 | Kandou Bus, S.A. | Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication |
US10164809B2 (en) | 2010-12-30 | 2018-12-25 | Kandou Labs, S.A. | Circuits for efficient detection of vector signaling codes for chip-to-chip communication |
US10091035B2 (en) | 2013-04-16 | 2018-10-02 | Kandou Labs, S.A. | Methods and systems for high bandwidth communications interface |
US9239752B2 (en) * | 2013-05-20 | 2016-01-19 | SK Hynix Inc. | Semiconductor system with error detection |
US20140344654A1 (en) * | 2013-05-20 | 2014-11-20 | SK Hynix Inc. | Semiconductor system |
US9985745B2 (en) | 2013-06-25 | 2018-05-29 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
US10177812B2 (en) | 2014-01-31 | 2019-01-08 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
US9806761B1 (en) | 2014-01-31 | 2017-10-31 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
US10348436B2 (en) | 2014-02-02 | 2019-07-09 | Kandou Labs, S.A. | Method and apparatus for low power chip-to-chip communications with constrained ISI ratio |
US10020966B2 (en) | 2014-02-28 | 2018-07-10 | Kandou Labs, S.A. | Vector signaling codes with high pin-efficiency for chip-to-chip communication and storage |
US10333749B2 (en) | 2014-05-13 | 2019-06-25 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
US9852806B2 (en) | 2014-06-20 | 2017-12-26 | Kandou Labs, S.A. | System for generating a test pattern to detect and isolate stuck faults for an interface using transition coding |
US10091033B2 (en) | 2014-06-25 | 2018-10-02 | Kandou Labs, S.A. | Multilevel driver for high speed chip-to-chip communications |
US9917711B2 (en) | 2014-06-25 | 2018-03-13 | Kandou Labs, S.A. | Multilevel driver for high speed chip-to-chip communications |
US9900186B2 (en) | 2014-07-10 | 2018-02-20 | Kandou Labs, S.A. | Vector signaling codes with increased signal to noise characteristics |
US10320588B2 (en) | 2014-07-10 | 2019-06-11 | Kandou Labs, S.A. | Vector signaling codes with increased signal to noise characteristics |
US10003424B2 (en) | 2014-07-17 | 2018-06-19 | Kandou Labs, S.A. | Bus reversible orthogonal differential vector signaling codes |
US10404394B2 (en) | 2014-07-17 | 2019-09-03 | Kandou Labs, S.A. | Bus reversible orthogonal differential vector signaling codes |
US9893911B2 (en) | 2014-07-21 | 2018-02-13 | Kandou Labs, S.A. | Multidrop data transfer |
US10230549B2 (en) | 2014-07-21 | 2019-03-12 | Kandou Labs, S.A. | Multidrop data transfer |
US10999106B2 (en) | 2014-07-21 | 2021-05-04 | Kandou Labs, S.A. | Multidrop data transfer |
US9838234B2 (en) | 2014-08-01 | 2017-12-05 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US10122561B2 (en) | 2014-08-01 | 2018-11-06 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US10243765B2 (en) | 2014-10-22 | 2019-03-26 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
EP3043562B1 (en) * | 2015-01-07 | 2021-05-19 | Renesas Electronics Corporation | Video encoding/decoding system and diagnosis method thereof |
US10638148B2 (en) | 2015-01-07 | 2020-04-28 | Renesas Electronics Corporation | Video encoding/decoding system and diagnosis method thereof |
US9832046B2 (en) | 2015-06-26 | 2017-11-28 | Kandou Labs, S.A. | High speed communications system |
US10116472B2 (en) | 2015-06-26 | 2018-10-30 | Kandou Labs, S.A. | High speed communications system |
US9547550B1 (en) * | 2015-07-07 | 2017-01-17 | Tidal Systems, Inc. | System and method for improved data maintenance in a flash drive |
US10324876B2 (en) | 2015-11-25 | 2019-06-18 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
US10003315B2 (en) | 2016-01-25 | 2018-06-19 | Kandou Labs S.A. | Voltage sampler driver with enhanced high-frequency gain |
US10057049B2 (en) | 2016-04-22 | 2018-08-21 | Kandou Labs, S.A. | High performance phase locked loop |
US10003454B2 (en) | 2016-04-22 | 2018-06-19 | Kandou Labs, S.A. | Sampler with low input kickback |
US10153591B2 (en) | 2016-04-28 | 2018-12-11 | Kandou Labs, S.A. | Skew-resistant multi-wire channel |
US10056903B2 (en) | 2016-04-28 | 2018-08-21 | Kandou Labs, S.A. | Low power multilevel driver |
US10333741B2 (en) | 2016-04-28 | 2019-06-25 | Kandou Labs, S.A. | Vector signaling codes for densely-routed wire groups |
US10355852B2 (en) | 2016-08-31 | 2019-07-16 | Kandou Labs, S.A. | Lock detector for phase lock loop |
US9906358B1 (en) | 2016-08-31 | 2018-02-27 | Kandou Labs, S.A. | Lock detector for phase lock loop |
US10277431B2 (en) | 2016-09-16 | 2019-04-30 | Kandou Labs, S.A. | Phase rotation circuit for eye scope measurements |
CN107968732A (en) * | 2016-10-20 | 2018-04-27 | 联发科技股份有限公司 | Method and uniform protocol device from functional test is performed to uniform protocol device |
US10200188B2 (en) | 2016-10-21 | 2019-02-05 | Kandou Labs, S.A. | Quadrature and duty cycle error correction in matrix phase lock loop |
US10200218B2 (en) | 2016-10-24 | 2019-02-05 | Kandou Labs, S.A. | Multi-stage sampler with increased gain |
US10372665B2 (en) | 2016-10-24 | 2019-08-06 | Kandou Labs, S.A. | Multiphase data receiver with distributed DFE |
US10666297B2 (en) | 2017-04-14 | 2020-05-26 | Kandou Labs, S.A. | Pipelined forward error correction for vector signaling code channel |
US11336302B2 (en) | 2017-04-14 | 2022-05-17 | Kandou Labs, S.A. | Pipelined forward error correction for vector signaling code channel |
US11804855B2 (en) | 2017-04-14 | 2023-10-31 | Kandou Labs, S.A. | Pipelined forward error correction for vector signaling code channel |
US10116468B1 (en) | 2017-06-28 | 2018-10-30 | Kandou Labs, S.A. | Low power chip-to-chip bidirectional communications |
US10686583B2 (en) | 2017-07-04 | 2020-06-16 | Kandou Labs, S.A. | Method for measuring and correcting multi-wire skew |
US10693587B2 (en) | 2017-07-10 | 2020-06-23 | Kandou Labs, S.A. | Multi-wire permuted forward error correction |
US11368247B2 (en) | 2017-07-10 | 2022-06-21 | Kandou Labs, S.A. | Multi-wire permuted forward error correction |
US11894926B2 (en) | 2017-07-10 | 2024-02-06 | Kandou Labs, S.A. | Interleaved forward error correction over multiple transport channels |
US10203226B1 (en) | 2017-08-11 | 2019-02-12 | Kandou Labs, S.A. | Phase interpolation circuit |
US10326623B1 (en) | 2017-12-08 | 2019-06-18 | Kandou Labs, S.A. | Methods and systems for providing multi-stage distributed decision feedback equalization |
US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
US11356197B1 (en) | 2021-03-19 | 2022-06-07 | Kandou Labs SA | Error-tolerant forward error correction ordered set message decoder |
US11658771B2 (en) | 2021-03-19 | 2023-05-23 | Kandou Labs SA | Error-tolerant forward error correction ordered set message decoder |
Also Published As
Publication number | Publication date |
---|---|
US20040250187A1 (en) | 2004-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7082557B2 (en) | High speed serial interface test | |
US5228042A (en) | Method and circuit for testing transmission paths | |
US6977960B2 (en) | Self test circuit for evaluating a high-speed serial interface | |
US7788562B2 (en) | Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data | |
US7346819B2 (en) | Through-core self-test with multiple loopbacks | |
US7669095B2 (en) | Methods and apparatus for error injection | |
US20050154946A1 (en) | Programmable measurement mode for a serial point to point link | |
US7191371B2 (en) | System and method for sequential testing of high speed serial link core | |
US8619599B1 (en) | Packet processor verification methods and systems | |
US6385236B1 (en) | Method and Circuit for testing devices with serial data links | |
US7620858B2 (en) | Fabric-based high speed serial crossbar switch for ATE | |
US7984369B2 (en) | Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features | |
US7852162B2 (en) | Pseudo random noise device based on a random frequency modulated oscillator | |
JP2810671B2 (en) | Pseudorandom word sequence synchronizer | |
KR20080044199A (en) | Interface test circuitry and methods | |
KR20050120661A (en) | A high performance serial bus testing methodology | |
US20070089006A1 (en) | IO self test method and apparatus for memory | |
US20180234177A1 (en) | Programmable photonic-electronic integrated circuit for optical testing | |
US7958404B2 (en) | Enabling resynchronization of a logic analyzer | |
US7627793B2 (en) | Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems | |
JP2006313159A (en) | Offset test pattern device and method | |
US7774669B2 (en) | Complex pattern generator for analysis of high speed serial streams | |
EP1814234B1 (en) | Concurrent code checker and hardware efficient high- speed I/O having built- in self- test and debug features | |
US7409618B2 (en) | Self verifying communications testing | |
US20040193975A1 (en) | Method and an apparatus for transmit phase select |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LSI LOGIC CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHAUER, STEVEN;CAMPBELL, KEVIN;REEL/FRAME:014900/0938 Effective date: 20030609 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: NETAPP, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:026661/0205 Effective date: 20110506 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.) |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20180725 |