US7087506B2 - Method of forming freestanding semiconductor layer - Google Patents

Method of forming freestanding semiconductor layer Download PDF

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Publication number
US7087506B2
US7087506B2 US10/604,116 US60411603A US7087506B2 US 7087506 B2 US7087506 B2 US 7087506B2 US 60411603 A US60411603 A US 60411603A US 7087506 B2 US7087506 B2 US 7087506B2
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Prior art keywords
semiconductor layer
base structure
mandrel
forming
polycrystalline semiconductor
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US20050009305A1 (en
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Brent A Anderson
Edward J Nowak
BethAnn Rainey
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GlobalFoundries Inc
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International Business Machines Corp
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Priority to US10/604,116 priority Critical patent/US7087506B2/en
Priority to CNB200480024191XA priority patent/CN100466175C/en
Priority to EP04777136A priority patent/EP1644968A4/en
Priority to KR1020057022449A priority patent/KR100781618B1/en
Priority to PCT/US2004/020552 priority patent/WO2005001904A2/en
Publication of US20050009305A1 publication Critical patent/US20050009305A1/en
Priority to US11/426,698 priority patent/US7709892B2/en
Publication of US7087506B2 publication Critical patent/US7087506B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the invention relates generally to semiconductor devices and more specifically to a freestanding semiconductor layer formed on a semiconductor device.
  • CMOS technologies such as in the design and fabrication of field effect transistors (FETs)
  • FETs field effect transistors
  • integrated circuit density has grown and continues to increase at a significant rate.
  • new methods are constantly needed to allow the feature size of these semiconductor devices to be reduced.
  • Fin FET is currently considered a leading candidate for CMOS technology beyond the 65 nanometer (nm) range.
  • Methods to produce fins, also known as freestanding semiconductor layers, for FinFETs have generally centered around using some form of a mask or etch stop, either e-beam, conventional lithography, or sidewall-image transfer, with which to etch thin silicon freestanding semiconductor layers from a silicon-on-insulator (SOI) or bulk-substrate silicon crystal.
  • SOI silicon-on-insulator
  • the traditional material used for forming a freestanding semiconductor layer and the masking process thereof may be expensive and may still not be accurate enough to provide a uniformity of thickness of the freestanding semiconductor layer, which is important in fabricating an FET with dependable and accurate performance.
  • a challenge of this technology is to provide a very thin silicon freestanding semiconductor layer with a high degree of control of the thickness thereof. Another challenge is to maintain uniformity of thickness from the top to the bottom of the freestanding semiconductor layer. Furthermore, a challenge of this technology is to provide for a precise and inexpensive method of forming a thin, uniform freestanding semiconductor layer on conventional SOI or bulk-substrate silicon devices.
  • a need has developed in the art for a method of forming a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device that will provide a high degree of control of the thickness and height thereof and maintain uniformity of thickness from the top to the bottom of the freestanding semiconductor layer.
  • the present invention provides a method for forming a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device that will provide a high degree of control of the thickness and height thereof and maintain uniformity of thickness of the freestanding semiconductor layer.
  • a first aspect of the present invention is directed to a method of forming a freestanding semiconductor layer, comprising the steps of: forming a non-monocrystalline mandrel on a monocrystalline base structure; forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure; and recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure.
  • a second aspect of the present invention provides a semiconductor device comprising a monocrystalline base structure; and a conformal monocrystalline freestanding semiconductor layer contacting the monocrystalline base structure, the freestanding semiconductor layer having a crystallinity substantially similar to that of the base structure.
  • the present invention also provides a method of forming a field-effect transistor having at least one freestanding semiconductor layer comprising the steps of: forming a non-monocrystalline mandrel on a monocrystalline base structure; forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure; recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure; removing the mandrel; and forming a gate structure on the semiconductor layer.
  • FIGS. 1 , 2 , 3 , 4 , and 5 are cross-sectional views of a bulk-substrate silicon semiconductor wafer illustrating one set of steps that may be used to form a freestanding semiconductor layer in accordance with a first embodiment of the present invention
  • FIG. 6 is a plan view of FIG. 5 ;
  • FIGS. 7 , 8 , 9 , and 10 are cross-sectional views of a silicon-on-insulator (SOI) semiconductor wafer illustrating a second set of steps that may be used to form a freestanding semiconductor layer in accordance with a second embodiment of the present invention
  • FIGS. 11 , 12 , 13 , 14 , and 15 are cross-sectional views of an SOI semiconductor wafer illustrating a third set of steps that may be used to form a freestanding semiconductor layer in accordance with a third embodiment of the present invention.
  • FIG. 16 is a plan view of a freestanding semiconductor layer formed as illustrated FIGS. 11 , 12 , 13 , 14 and 15 .
  • FIGS. 1–6 illustrate the steps for forming a freestanding semiconductor layer 26 on a conventional silicon-based bulk-substrate semiconductor wafer (i.e., base structure 20 ) shown in cross-section ( FIGS. 1–5 ) and plan view ( FIG. 6 ), in accordance with a first embodiment of the present invention.
  • the first step 10 a is forming a mandrel 22 on base structure 20 .
  • Base structure 20 in this embodiment is a bulk-substrate silicon wafer that is of a monocrystalline material, such as silicon (Si).
  • Mandrel 22 is formed on base structure 20 through patterning and etching a deposited or grown material on base structure 20 .
  • Mandrel 22 may consist of an amorphous material, or a polycrystalline material, such as silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or other similar materials as known in the art.
  • the second step 10 b includes forming a conformal semiconductor layer 24 on mandrel 22 and base structure 20 .
  • Semiconductor layer 24 is either epitaxially grown or deposited upon base structure 20 and at least one sidewall of mandrel 22 in a conformal manner. If semiconductor layer 24 is epitaxially grown, the microstructure of semiconductor layer 24 , which contacts base structure 20 , will take on the crystal orientation of base structure 20 . Thus, the contact between semiconductor layer 24 and base structure 20 allows for an inexpensive and efficient recrystallization process for sections of semiconductor layer 24 , and thus formation of a freestanding semiconductor layer 26 ( FIG. 4 ) once mandrel 22 is removed.
  • semiconductor layer 24 will initially be made up of a polycrystalline material, such as polysilicon. Semiconductor layer 24 will then take on the crystal orientation of base structure 20 when recrystallized through heat by annealing (around 600 ⁇ ° C.), or through other known recrystallization methods in the art. Recrystallization will, in most cases, occur after step 10 c in reference to FIG. 3 , but may also occur after step 10 d in reference to FIG. 4 .
  • the next step 10 c in forming a freestanding semiconductor layer is selective removal of predetermined sections of semiconductor layer 24 .
  • the sections of semiconductor layer 24 that Were not deposited or grown on the sidewall of mandrel 22 are removed, though the present invention is not limited to such.
  • Semiconductor layer 24 may be selectively anisotropically etched, or planarized and then etched, allowing the formation of a tall, thin freestanding semiconductor layer 26 ( FIG. 4 ).
  • FIG. 4 illustrates the next step 10 d , wherein mandrel 22 is removed from base structure 20 , leaving freestanding semiconductor layer 26 .
  • mandrel 22 does not comprise the same material as freestanding semiconductor layer 26 , the removal of mandrel 22 through etching or similar methods does not affect the structure of freestanding semiconductor layer 26 .
  • an etch stop is not needed to define the boundaries to be removed.
  • the thickness of freestanding semiconductor layer 26 is determined by the epitaxial growth, or deposition of polysilicon, while the height is determined by the thickness of mandrel 22 .
  • freestanding semiconductor layer 26 is uniformly thin and tall and takes on the crystal orientation of base structure 20 .
  • FIGS. 5 and 6 illustrate in step 10 e forming a gate structure 28 of doped polysilicon on base structure 20 , wherein FIG. 5 shows the cross-sectional view of this process and FIG. 6 illustrates the plan view.
  • Gate structure 28 is formed through the patterning and etching of a deposited polysilicon (not shown). Gate structure 28 is also formed across freestanding semiconductor layer 26 ( FIG. 6 ), and thus contacts freestanding semiconductor layer 26 .
  • FIGS. 7–10 illustrate the steps for forming freestanding semiconductor layer 51 ( FIG. 10 ) on a conventional silicon-on-insulator (SOI) semiconductor wafer (including bottom layer 40 and insulating layer 46 ) shown in cross-section, in accordance with a second embodiment of the present invention.
  • SOI silicon-on-insulator
  • the first step 30 a is forming a base structure 44 and mandrel material 42 on insulating layer 46 , wherein mandrel material 42 is also formed on a sidewall of base structure 44 .
  • Base structure 44 is formed on insulating layer 46 through a patterned etch of the active silicon of a SOI wafer, and then patterning and etching the silicon into a predetermined shape.
  • the remaining base structure 44 is a monocrystalline semiconductor.
  • Mandrel material 42 is then formed through depositing or growing an amorphous or polycrystalline material over base structure 44 and insulating layer 46 and planarizing mandrel material 42 to base structure 44 .
  • mandrel material 42 and base structure 44 are patterned and etched to form a second mandrel including both mandrel material 42 and base structure 44 .
  • mandrel material 42 is made up of Si 3 N 4 , but is not limited to such.
  • the second step 30 b includes forming a conformal semiconductor layer 48 on mandrel material 42 , base structure 44 , and insulating layer 46 .
  • Semiconductor layer 48 is either epitaxially grown deposited upon insulating layer 46 , base structure 44 and at least one sidewall of mandrel material 42 in a conformal manner. If deposited, semiconductor layer 48 will initially be of a polycrystalline material, such as polysilicon. If semiconductor layer 48 is epitaxially grown, the sections of semiconductor layer 48 that are not in contact with base structure 44 will initially be polycrystalline and the sections of semiconductor layer 48 contacting base structure 44 will take on the crystal orientation of base structure 44 . In either case, the entire semiconductor layer 48 takes on the crystal orientation of base structure 44 when recrystallized through heat by annealing (around 600 ⁇ ° C.), or other known recrystallization methods in the art.
  • the next step 30 c in forming a freestanding semiconductor layer 51 is through selective removal of semiconductor layer 48 ( FIG. 8 ).
  • Semiconductor layer 48 may be selectively etched by an anisotropic etch, or planarized and then etched, allowing the formation of tall, thin semiconductor layers 52 and 49 .
  • semiconductor layer 48 is epitaxially grown, semiconductor layer 52 , which is in contact with base structure 44 , will take on the crystal orientation of base structure 44 ; and semiconductor layer 49 , which is not in contact with base structure 44 , will continue to be of a polycrystalline material, at least until recrystallized.
  • semiconductor layer 48 is deposited, both semiconductor layer 52 and semiconductor layer 49 will be of a polycrystalline material until recrystallized.
  • FIG. 9 illustrates a cross-section of semiconductor layers 52 and 49 , base structure 44 and mandrel material 42 , in this specific embodiment, it is to be understood that, although not shown, base structure 44 still contacts at least one sidewall of mandrel material 42 and semiconductor layers 52 and 49 still contact the remaining sidewalls of mandrel material 42 after being etched. That is, semiconductor layer 52 and semiconductor layer 49 are one continuous layer, forming a thin, tall rectangular, or similar shape, around mandrel material 42 and base structure 44 . Although in this specific embodiment, semiconductor layer 52 and semiconductor layer 49 are one continuous layer, the present invention is not limited by such, and more than one layer may be formed.
  • FIG. 0 illustrates the next step 30 d , wherein mandrel material 42 is removed from base structure 44 and insulating layer 46 , leaving freestanding semiconductor layer 51 and base structure 44 .
  • mandrel material 42 does not comprise the same material as freestanding semiconductor layer 51 and base structure 44 , the removal of mandrel material 42 through selective etching or similar methods does not affect the structure of freestanding semiconductor layer 51 .
  • an etch stop is not needed to define the boundaries to be removed.
  • the thickness of freestanding semiconductor layer 51 is determined by the epitaxial growth, or deposition of polysilicon, while the height is determined by the thickness of mandrel material 42 . Freestanding semiconductor layer 51 takes on the crystal orientation of base structure 44 .
  • FIGS. 11–16 illustrate the steps for a forming freestanding semiconductor layer 74 ( FIG. 16 ) on a conventional SOI semiconductor wafer (with base structure 70 and insulating layer 64 ) shown in cross-section ( FIGS. 11–15 ) and plan view ( FIG. 16 ) in accordance with a third embodiment of the present invention.
  • the first step 60 a is etching aperture 66 through insulating layer 64 to base structure 70 .
  • Base structure 70 in this embodiment is an SOI semiconductor wafer that is of a monocrystalline material, such as silicon (Si).
  • Si silicon
  • FIG. 12 shows the next step 60 b of forming a mandrel 68 on insulating layer 64 and base structure 70 , wherein mandrel 68 contacts base structure 70 through aperture 66 .
  • aperture 66 is greater in width than mandrel 68 , allowing contact to base structure 70 on either side of mandrel 68 formed on base structure 70 .
  • Mandrel 68 may be formed on insulating layer 64 and base structure 70 through patterning and etching a deposited or grown material on insulating layer 64 and base structure 70 .
  • Mandrel 68 may include an amorphous or polycrystalline material, such as Si 3 N 4 , or other similar materials as known in the art.
  • the third step 60 c includes forming a conformal semiconductor layer 72 on insulating layer 64 , mandrel 68 , and base structure 70 (through aperture 66 ).
  • Semiconductor layer 72 is either epitaxially grown or deposited upon insulating layer 64 , base structure 70 and at least one sidewall of mandrel 68 in a conformal manner. If deposited, semiconductor layer 72 will initially be made up of a polycrystalline material, such as polysilicon. If semiconductor layer 72 is epitaxially grown, the microstructure of semiconductor layer 72 , which contacts base structure 70 on either side of mandrel 68 through aperture 66 , will take on the crystal orientation of base structure 70 .
  • semiconductor layer 72 substantially takes on the crystal orientation of base structure 70 when recrystallized through heat by annealing (around 600 ⁇ ° C.), or through other known recrystallization methods in the art. Recrystallization will, in most cases, occur after step 60 d in reference to FIG. 14 , but may also occur after step 60 e in reference to FIG. 15 .
  • the next step 60 d in forming a freestanding semiconductor layer 74 is through selective removal of semiconductor layer 72 .
  • the sections of semiconductor layer 72 that were not deposited or grown on the sidewall of mandrel 68 are removed, though the present invention is not limited to such.
  • Semiconductor layer 72 may be selectively anistropically etched, or planarized and then etched, allowing the formation of a tall, thin freestanding semiconductor layer 74 ( FIG. 15 ).
  • FIG. 15 illustrates the next step 60 e wherein mandrel 68 is removed from the base structure 70 , leaving freestanding semiconductor layer 74 .
  • mandrel 68 does not comprise the same material as freestanding semiconductor layer 74
  • the removal of mandrel 68 through etching or similar methods does not affect the structure of freestanding semiconductor layer 74 .
  • an etch stop is not needed to define the boundaries to be removed.
  • the thickness of freestanding semiconductor layer 74 is determined by the epitaxial growth, or deposition of polysilicon, while the height is determined by the thickness of mandrel 68 .
  • freestanding semiconductor layer 74 is uniformly thin and tall and takes on the crystal orientation of base structure 70 .
  • FIG. 16 illustrates, in plan view, step 60 f , wherein a gate structure 76 of doped polysilicon is formed on insulating layer 64 and across freestanding semiconductor layer 74 .
  • Gate structure 76 is formed through the patterning and etching of a deposited polysilicon (not shown).
  • a transistor then may be fabricated through the formation of extensions, halos, and source and drain regions (not shown), which process is well known in the art.
  • this invention provides a method of forming a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon wafer that will provide a high degree of control of the thickness and height thereof and maintain uniformity of thickness of the freestanding semiconductor layer.

Abstract

A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

Description

BACKGROUND OF INVENTION
1. Technical Field
The invention relates generally to semiconductor devices and more specifically to a freestanding semiconductor layer formed on a semiconductor device.
2. Related Art
In CMOS technologies, such as in the design and fabrication of field effect transistors (FETs), integrated circuit density has grown and continues to increase at a significant rate. To facilitate the increase in device density, new methods are constantly needed to allow the feature size of these semiconductor devices to be reduced.
Fin FET is currently considered a leading candidate for CMOS technology beyond the 65 nanometer (nm) range. Methods to produce fins, also known as freestanding semiconductor layers, for FinFETs have generally centered around using some form of a mask or etch stop, either e-beam, conventional lithography, or sidewall-image transfer, with which to etch thin silicon freestanding semiconductor layers from a silicon-on-insulator (SOI) or bulk-substrate silicon crystal. The traditional material used for forming a freestanding semiconductor layer and the masking process thereof may be expensive and may still not be accurate enough to provide a uniformity of thickness of the freestanding semiconductor layer, which is important in fabricating an FET with dependable and accurate performance.
Thus, a challenge of this technology is to provide a very thin silicon freestanding semiconductor layer with a high degree of control of the thickness thereof. Another challenge is to maintain uniformity of thickness from the top to the bottom of the freestanding semiconductor layer. Furthermore, a challenge of this technology is to provide for a precise and inexpensive method of forming a thin, uniform freestanding semiconductor layer on conventional SOI or bulk-substrate silicon devices.
Accordingly, a need has developed in the art for a method of forming a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device that will provide a high degree of control of the thickness and height thereof and maintain uniformity of thickness from the top to the bottom of the freestanding semiconductor layer.
SUMMARY OF INVENTION
The present invention provides a method for forming a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device that will provide a high degree of control of the thickness and height thereof and maintain uniformity of thickness of the freestanding semiconductor layer.
Generally, a first aspect of the present invention is directed to a method of forming a freestanding semiconductor layer, comprising the steps of: forming a non-monocrystalline mandrel on a monocrystalline base structure; forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure; and recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure.
In addition, a second aspect of the present invention provides a semiconductor device comprising a monocrystalline base structure; and a conformal monocrystalline freestanding semiconductor layer contacting the monocrystalline base structure, the freestanding semiconductor layer having a crystallinity substantially similar to that of the base structure.
The present invention also provides a method of forming a field-effect transistor having at least one freestanding semiconductor layer comprising the steps of: forming a non-monocrystalline mandrel on a monocrystalline base structure; forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure; recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure; removing the mandrel; and forming a gate structure on the semiconductor layer.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
Embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and wherein:
FIGS. 1, 2, 3, 4, and 5 are cross-sectional views of a bulk-substrate silicon semiconductor wafer illustrating one set of steps that may be used to form a freestanding semiconductor layer in accordance with a first embodiment of the present invention;
FIG. 6 is a plan view of FIG. 5;
FIGS. 7, 8, 9, and 10 are cross-sectional views of a silicon-on-insulator (SOI) semiconductor wafer illustrating a second set of steps that may be used to form a freestanding semiconductor layer in accordance with a second embodiment of the present invention;
FIGS. 11, 12, 13, 14, and 15 are cross-sectional views of an SOI semiconductor wafer illustrating a third set of steps that may be used to form a freestanding semiconductor layer in accordance with a third embodiment of the present invention; and
FIG. 16 is a plan view of a freestanding semiconductor layer formed as illustrated FIGS. 11, 12, 13, 14 and 15.
 DETAILED DESCRIPTION
FIGS. 1–6 illustrate the steps for forming a freestanding semiconductor layer 26 on a conventional silicon-based bulk-substrate semiconductor wafer (i.e., base structure 20) shown in cross-section (FIGS. 1–5) and plan view (FIG. 6), in accordance with a first embodiment of the present invention. As seen in FIG. 1, the first step 10 a is forming a mandrel 22 on base structure 20. Base structure 20 in this embodiment is a bulk-substrate silicon wafer that is of a monocrystalline material, such as silicon (Si). Mandrel 22 is formed on base structure 20 through patterning and etching a deposited or grown material on base structure 20. Mandrel 22 may consist of an amorphous material, or a polycrystalline material, such as silicon oxide (SiO2) or silicon nitride (Si3N4), or other similar materials as known in the art.
In FIG. 2, the second step 10 b includes forming a conformal semiconductor layer 24 on mandrel 22 and base structure 20. Semiconductor layer 24 is either epitaxially grown or deposited upon base structure 20 and at least one sidewall of mandrel 22 in a conformal manner. If semiconductor layer 24 is epitaxially grown, the microstructure of semiconductor layer 24, which contacts base structure 20, will take on the crystal orientation of base structure 20. Thus, the contact between semiconductor layer 24 and base structure 20 allows for an inexpensive and efficient recrystallization process for sections of semiconductor layer 24, and thus formation of a freestanding semiconductor layer 26 (FIG. 4) once mandrel 22 is removed. If deposited, semiconductor layer 24 will initially be made up of a polycrystalline material, such as polysilicon. Semiconductor layer 24 will then take on the crystal orientation of base structure 20 when recrystallized through heat by annealing (around 600° C.), or through other known recrystallization methods in the art. Recrystallization will, in most cases, occur after step 10 c in reference to FIG. 3, but may also occur after step 10 d in reference to FIG. 4.
As seen in FIG. 3, the next step 10 c in forming a freestanding semiconductor layer is selective removal of predetermined sections of semiconductor layer 24. In this specific embodiment, the sections of semiconductor layer 24 that Were not deposited or grown on the sidewall of mandrel 22 are removed, though the present invention is not limited to such. Semiconductor layer 24 may be selectively anisotropically etched, or planarized and then etched, allowing the formation of a tall, thin freestanding semiconductor layer 26 (FIG. 4).
FIG. 4 illustrates the next step 10 d, wherein mandrel 22 is removed from base structure 20, leaving freestanding semiconductor layer 26. Since mandrel 22 does not comprise the same material as freestanding semiconductor layer 26, the removal of mandrel 22 through etching or similar methods does not affect the structure of freestanding semiconductor layer 26. Furthermore, an etch stop is not needed to define the boundaries to be removed. Hence, the thickness of freestanding semiconductor layer 26 is determined by the epitaxial growth, or deposition of polysilicon, while the height is determined by the thickness of mandrel 22. Thus, freestanding semiconductor layer 26 is uniformly thin and tall and takes on the crystal orientation of base structure 20.
FIGS. 5 and 6 illustrate in step 10 e forming a gate structure 28 of doped polysilicon on base structure 20, wherein FIG. 5 shows the cross-sectional view of this process and FIG. 6 illustrates the plan view. Gate structure 28 is formed through the patterning and etching of a deposited polysilicon (not shown). Gate structure 28 is also formed across freestanding semiconductor layer 26 (FIG. 6), and thus contacts freestanding semiconductor layer 26. A transistor, such as an FET, then may be fabricated through the formation of extensions, halos, and source and drain regions (not shown), which process is well known in the art.
FIGS. 7–10 illustrate the steps for forming freestanding semiconductor layer 51 (FIG. 10) on a conventional silicon-on-insulator (SOI) semiconductor wafer (including bottom layer 40 and insulating layer 46) shown in cross-section, in accordance with a second embodiment of the present invention.
As seen in FIG. 7, the first step 30 a is forming a base structure 44 and mandrel material 42 on insulating layer 46, wherein mandrel material 42 is also formed on a sidewall of base structure 44. Base structure 44 is formed on insulating layer 46 through a patterned etch of the active silicon of a SOI wafer, and then patterning and etching the silicon into a predetermined shape. Thus, the remaining base structure 44 is a monocrystalline semiconductor. Mandrel material 42 is then formed through depositing or growing an amorphous or polycrystalline material over base structure 44 and insulating layer 46 and planarizing mandrel material 42 to base structure 44. Both mandrel material 42 and base structure 44 are patterned and etched to form a second mandrel including both mandrel material 42 and base structure 44. In this specific embodiment, mandrel material 42 is made up of Si3N4, but is not limited to such.
In FIG. 8, the second step 30 b includes forming a conformal semiconductor layer 48 on mandrel material 42, base structure 44, and insulating layer 46. Semiconductor layer 48 is either epitaxially grown deposited upon insulating layer 46, base structure 44 and at least one sidewall of mandrel material 42 in a conformal manner. If deposited, semiconductor layer 48 will initially be of a polycrystalline material, such as polysilicon. If semiconductor layer 48 is epitaxially grown, the sections of semiconductor layer 48 that are not in contact with base structure 44 will initially be polycrystalline and the sections of semiconductor layer 48 contacting base structure 44 will take on the crystal orientation of base structure 44. In either case, the entire semiconductor layer 48 takes on the crystal orientation of base structure 44 when recrystallized through heat by annealing (around 600° C.), or other known recrystallization methods in the art.
As seen in FIG. 9, the next step 30 c in forming a freestanding semiconductor layer 51 (FIG. 10) is through selective removal of semiconductor layer 48 (FIG. 8). Semiconductor layer 48 may be selectively etched by an anisotropic etch, or planarized and then etched, allowing the formation of tall, thin semiconductor layers 52 and 49. As aforementioned, if semiconductor layer 48 is epitaxially grown, semiconductor layer 52, which is in contact with base structure 44, will take on the crystal orientation of base structure 44; and semiconductor layer 49, which is not in contact with base structure 44, will continue to be of a polycrystalline material, at least until recrystallized. If semiconductor layer 48 is deposited, both semiconductor layer 52 and semiconductor layer 49 will be of a polycrystalline material until recrystallized.
Furthersmore, ince FIG. 9 illustrates a cross-section of semiconductor layers 52 and 49, base structure 44 and mandrel material 42, in this specific embodiment, it is to be understood that, although not shown, base structure 44 still contacts at least one sidewall of mandrel material 42 and semiconductor layers 52 and 49 still contact the remaining sidewalls of mandrel material 42 after being etched. That is, semiconductor layer 52 and semiconductor layer 49 are one continuous layer, forming a thin, tall rectangular, or similar shape, around mandrel material 42 and base structure 44. Although in this specific embodiment, semiconductor layer 52 and semiconductor layer 49 are one continuous layer, the present invention is not limited by such, and more than one layer may be formed.
1 FIG. 0 illustrates the next step 30 d, wherein mandrel material 42 is removed from base structure 44 and insulating layer 46, leaving freestanding semiconductor layer 51 and base structure 44. Since mandrel material 42 does not comprise the same material as freestanding semiconductor layer 51 and base structure 44, the removal of mandrel material 42 through selective etching or similar methods does not affect the structure of freestanding semiconductor layer 51. Furthermore, an etch stop is not needed to define the boundaries to be removed. As with the first embodiment of the present invention, the thickness of freestanding semiconductor layer 51 is determined by the epitaxial growth, or deposition of polysilicon, while the height is determined by the thickness of mandrel material 42. Freestanding semiconductor layer 51 takes on the crystal orientation of base structure 44.
FIGS. 11–16 illustrate the steps for a forming freestanding semiconductor layer 74 (FIG. 16) on a conventional SOI semiconductor wafer (with base structure 70 and insulating layer 64) shown in cross-section (FIGS. 11–15) and plan view (FIG. 16) in accordance with a third embodiment of the present invention. As seen in FIG. 11, the first step 60 a is etching aperture 66 through insulating layer 64 to base structure 70. Base structure 70 in this embodiment is an SOI semiconductor wafer that is of a monocrystalline material, such as silicon (Si). Although only one aperture 66 shown in FIG. 11, the present invention is not limited to such. Other apertures may be formed through insulating layer 64 for multiple contacts of base structure 70 with either mandrel 68 (FIG. 13) or semiconductor layer 72 (FIG. 13).
FIG. 12 shows the next step 60 b of forming a mandrel 68 on insulating layer 64 and base structure 70, wherein mandrel 68 contacts base structure 70 through aperture 66. In this embodiment, aperture 66 is greater in width than mandrel 68, allowing contact to base structure 70 on either side of mandrel 68 formed on base structure 70. Mandrel 68 may be formed on insulating layer 64 and base structure 70 through patterning and etching a deposited or grown material on insulating layer 64 and base structure 70. Mandrel 68 may include an amorphous or polycrystalline material, such as Si3N4, or other similar materials as known in the art.
In FIG. 13, the third step 60 c includes forming a conformal semiconductor layer 72 on insulating layer 64, mandrel 68, and base structure 70 (through aperture 66). Semiconductor layer 72 is either epitaxially grown or deposited upon insulating layer 64, base structure 70 and at least one sidewall of mandrel 68 in a conformal manner. If deposited, semiconductor layer 72 will initially be made up of a polycrystalline material, such as polysilicon. If semiconductor layer 72 is epitaxially grown, the microstructure of semiconductor layer 72, which contacts base structure 70 on either side of mandrel 68 through aperture 66, will take on the crystal orientation of base structure 70. Thus, the contact between semiconductor layer 72 and base structure 70 allows for an inexpensive and efficient recrystallization process for sections of semiconductor layer 72. In both cases, whether deposited or epitaxially grown, semiconductor layer 72 substantially takes on the crystal orientation of base structure 70 when recrystallized through heat by annealing (around 600° C.), or through other known recrystallization methods in the art. Recrystallization will, in most cases, occur after step 60 d in reference to FIG. 14, but may also occur after step 60 e in reference to FIG. 15.
As seen in FIG. 14, the next step 60 d in forming a freestanding semiconductor layer 74 (FIG. 16) is through selective removal of semiconductor layer 72. In this specific embodiment, the sections of semiconductor layer 72 that were not deposited or grown on the sidewall of mandrel 68 are removed, though the present invention is not limited to such. Semiconductor layer 72 may be selectively anistropically etched, or planarized and then etched, allowing the formation of a tall, thin freestanding semiconductor layer 74 (FIG. 15).
FIG. 15 illustrates the next step 60 e wherein mandrel 68 is removed from the base structure 70, leaving freestanding semiconductor layer 74. Since mandrel 68 does not comprise the same material as freestanding semiconductor layer 74, the removal of mandrel 68 through etching or similar methods does not affect the structure of freestanding semiconductor layer 74. Furthermore, an etch stop is not needed to define the boundaries to be removed. As aforementioned, the thickness of freestanding semiconductor layer 74 is determined by the epitaxial growth, or deposition of polysilicon, while the height is determined by the thickness of mandrel 68. Thus, freestanding semiconductor layer 74 is uniformly thin and tall and takes on the crystal orientation of base structure 70.
FIG. 16 illustrates, in plan view, step 60 f, wherein a gate structure 76 of doped polysilicon is formed on insulating layer 64 and across freestanding semiconductor layer 74. Gate structure 76 is formed through the patterning and etching of a deposited polysilicon (not shown). A transistor then may be fabricated through the formation of extensions, halos, and source and drain regions (not shown), which process is well known in the art.
Thus, this invention provides a method of forming a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon wafer that will provide a high degree of control of the thickness and height thereof and maintain uniformity of thickness of the freestanding semiconductor layer.
While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims (20)

1. A method of forming a freestanding semiconductor layer, comprising the steps of:
a) forming a non-monocrystalline mandrel on a monocrystalline base structure;
b) forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure; and
c) recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure.
2. The method of claim 1, wherein the step of forming a conformal polycrystalline semiconductor layer further comprises the steps of:
b1) depositing the polycrystalline semiconductor layer on the base structure and the mandrel; and
b2) selectively removing a portion of the polycrystalline semiconductor layer, wherein a remaining portion of the polycrystalline layer contacts at least one sidewall of the mandrel and the base structure.
3. The method of claim 1, wherein the step of forming a conformal polycrystalline semiconductor layer further comprises the steps of:
b1) growing the polycrystalline semiconductor layer on the base structure and the mandrel; and
b2) selectively removing a portion of the polycrystalline semiconductor layer.
4. The method of claim 1, wherein the step of recrystallizing the polycrystalline semiconductor layer further comprises the steps of:
c1) removing the mandrel; and
c2) recrystallizing the polycrystalline semiconductor layer through annealing.
5. The method of claim 1, wherein the step of recrystallizing the polycrystalline semiconductor layer further comprises the steps of:
c1) recrystallizing the polycrystalline semiconductor layer through annealing; and
c2) removing the mandrel.
6. The method of claim 1, further comprising the step of:
providing an insulating layer.
7. The method of claim 6, wherein the step of forming a non-monocrystalline mandrel further comprises the steps of:
a1) forming the base structure on the insulating layer;
a2) depositing the mandrel on the insulating layer and the base structure;
a3) planarizing the mandrel to the base structure; and
a4) selectively removing a portion of the mandrel and the base structure from the insulating layer.
8. The method of claim 6, wherein the step of forming a non-monocrystalline mandrel farther comprises the steps of:
a1) forming an insulator material on the monocrystalline base structure;
a2) forming at least one aperture in the insulator material; and
a3) forming the non-monocrystalline mandrel on the insulator material and on the base structure, wherein the mandrel contacts the base structure through the at least one aperture.
9. The method of claim 8, wherein the step of forming a conformal polycrystalline semiconductor layer further comprises the step of:
b1) forming the semiconductor layer on the base structure through the at least one aperture.
10. The method of claim 6, wherein the insulator layer and the base structure form a silicon-on-insulator wafer.
11. A method of forming a field-effect transistor having at least one freestanding semiconductor layer comprising the steps of:
a) forming a non-monocrystalline mandrel on a monocrystalline base structure;
b) forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure;
c) recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure;
d) removing the mandrel; and
e) forming a gate structure on the semiconductor layer.
12. The method of claim 11, wherein the step of forming a conformal polycrystalline semiconductor layer further comprises the steps of:
b1) depositing the polycrystalline semiconductor layer on the base structure and the mandrel; and
b2) selectively removing a portion of the polycrystalline semiconductor layer, wherein a remaining portion of the polycrystalline layer contacts at least one sidewall of the mandrel and the base structure.
13. The method of claim 11, wherein the step of forming a conformal polycrystalline semiconductor layer further comprises the steps of:
b1) growing the polycrystalline semiconductor layer on the base structure and the mandrel; and
b2) selectively removing a portion of the polycrystalline semiconductor layer.
14. The method of claim 11, wherein the step of forming a non-monocrystalline mandrel further comprises the steps of:
a1) providing an insulating layer;
a2) forming the base structure on the insulating layer;
a3) depositing the mandrel on the insulating layer and the base structure;
a4) planarizing the mandrel to the base structure; and
a5) selectively removing a portion of the mandrel and the base structure from the insulating layer.
15. The method of claim 11, wherein the step of forming a non-monocrystalline mandrel further comprises the steps of:
a1) providing an insulator material;
a2) forming the insulator material on the monocrystalline base structure;
a3) forming at least one aperture in the insulator material; and
a4) forming the non-monocrystalline mandrel on the insulator material and on the base structure, wherein the mandrel contacts the base structure through the at least one aperture.
16. A method of forming a freestanding semiconductor layer, comprising the steps of:
a) forming a non-monocrystalline mandrel on a monocrystalline base structure;
b) forming a conformal polycrystalline semiconductor layer on at least one sidewall of the mandrel, the polycrystalline layer contacting the monocrystalline base structure;
c) growing the polycrystalline semiconductor layer on the base structure and the mandrel;
d) selectively removing a portion of the polycrystalline semiconductor layer;
e) recrystallizing the polycrystalline semiconductor layer to have a crystallinity substantially similar to that of the base structure; and
f) removing the mandrel.
17. The method of claim 16, wherein the step of forming a conformal polycrystalline semiconductor layer further comprises the steps of:
b1) depositing the polycrystalline semiconductor layer on the base structure and the mandrel; and
b2) selectively removing a portion of the polycrystalline semiconductor layer, wherein a remaining portion of the polycrystalline layer contacts at least one sidewall of the mandrel and the base structure.
18. The method of claim 16, further wherein the step of recrystallizing the polycrystalline semiconductor layer is via annealing.
19. The method of claim 16, further comprising the step of:
providing an insulating layer.
20. The method of claim 19, wherein the stop of forming a non-monocrystalline mandrel further comprises the steps of:
a1) forming the base structure on the insulating layer;
a2) depositing the mandrel on the insulating layer and the base structure;
a3) planarizing the mandrel to the base structure; and
a4) selectively removing a portion of the mandrel and the base structure from the insulating layer.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080217616A1 (en) * 2007-03-05 2008-09-11 Yong-Hoon Son Semiconductor integrated circuit device and a method of fabricating the same
US20100090197A1 (en) * 2008-10-10 2010-04-15 Electonics And Telecommunications Research Institute Method of manufacturing semiconductor nanowire sensor device and semiconductor nanowire sensor device manufactured according to the method
US8232164B2 (en) 2010-10-29 2012-07-31 International Business Machines Corporation Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
US8753964B2 (en) 2011-01-27 2014-06-17 International Business Machines Corporation FinFET structure having fully silicided fin
US9385050B2 (en) 2011-01-06 2016-07-05 Globalfoundries Inc. Structure and method to fabricate resistor on finFET processes
US9530701B2 (en) 2014-12-18 2016-12-27 International Business Machines Corporation Method of forming semiconductor fins on SOI substrate

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100583452C (en) * 2005-01-28 2010-01-20 Nxp股份有限公司 Method of fabricating a FET
US7381655B2 (en) * 2005-09-14 2008-06-03 International Business Machines Corporation Mandrel/trim alignment in SIT processing
US7265013B2 (en) * 2005-09-19 2007-09-04 International Business Machines Corporation Sidewall image transfer (SIT) technologies
JP2007123827A (en) 2005-09-30 2007-05-17 Seiko Epson Corp Semiconductor device and its manufacturing method
US7569857B2 (en) * 2006-09-29 2009-08-04 Intel Corporation Dual crystal orientation circuit devices on the same substrate
US20090303794A1 (en) * 2008-06-04 2009-12-10 Macronix International Co., Ltd. Structure and Method of A Field-Enhanced Charge Trapping-DRAM
US8021949B2 (en) * 2009-12-01 2011-09-20 International Business Machines Corporation Method and structure for forming finFETs with multiple doping regions on a same chip
US8232198B2 (en) 2010-08-05 2012-07-31 International Business Machines Corporation Self-aligned permanent on-chip interconnect structure formed by pitch splitting
US8890318B2 (en) 2011-04-15 2014-11-18 International Business Machines Corporation Middle of line structures
US9054160B2 (en) 2011-04-15 2015-06-09 International Business Machines Corporation Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
US8900988B2 (en) 2011-04-15 2014-12-02 International Business Machines Corporation Method for forming self-aligned airgap interconnect structures
US8822137B2 (en) 2011-08-03 2014-09-02 International Business Machines Corporation Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
US20130062732A1 (en) 2011-09-08 2013-03-14 International Business Machines Corporation Interconnect structures with functional components and methods for fabrication
US9087753B2 (en) 2012-05-10 2015-07-21 International Business Machines Corporation Printed transistor and fabrication method
US8586455B1 (en) * 2012-05-15 2013-11-19 International Business Machines Corporation Preventing shorting of adjacent devices
US9385131B2 (en) * 2012-05-31 2016-07-05 Globalfoundries Inc. Wrap-around fin for contacting a capacitor strap of a DRAM
US8951870B2 (en) 2013-03-14 2015-02-10 International Business Machines Corporation Forming strained and relaxed silicon and silicon germanium fins on the same wafer
CN104934480B (en) * 2015-06-30 2017-11-24 上海华力微电子有限公司 Fin formula field effect transistor structure and preparation method thereof
US11289487B2 (en) * 2018-02-23 2022-03-29 Micron Technology, Inc. Doped titanium nitride materials for DRAM capacitors, and related semiconductor devices, systems, and methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328813A (en) * 1992-06-30 1994-07-12 The Dow Chemical Company Method for the preparation of optical recording media containing overcoat
EP0721221A2 (en) 1995-01-03 1996-07-10 International Business Machines Corporation FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
US20020181523A1 (en) 2001-05-29 2002-12-05 Pinneo George G. Low cost high integrity diode laser array
US6492212B1 (en) 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5328810A (en) * 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
JP3202223B2 (en) * 1990-11-27 2001-08-27 日本電気株式会社 Method for manufacturing transistor
DE69213539T2 (en) * 1991-04-26 1997-02-20 Canon Kk Semiconductor device with improved insulated gate transistor
JPH09293793A (en) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp Semiconductor device provided with thin film transistor and manufacture thereof
JP4014677B2 (en) * 1996-08-13 2007-11-28 株式会社半導体エネルギー研究所 Insulated gate type semiconductor device
TW441128B (en) * 1998-06-30 2001-06-16 Sharp Kk Semiconductor device and method for producing the same
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6472258B1 (en) * 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6638819B1 (en) * 2000-11-17 2003-10-28 Newport Fab, Llc Method for fabricating interfacial oxide in a transistor and related structure
US6664143B2 (en) * 2000-11-22 2003-12-16 North Carolina State University Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6586311B2 (en) * 2001-04-25 2003-07-01 Advanced Micro Devices, Inc. Salicide block for silicon-on-insulator (SOI) applications
US6365445B1 (en) * 2001-05-01 2002-04-02 Advanced Micro Devices, Inc. Field effect transistor formed in SOI technology with semiconductor material having multiple thicknesses
US6645795B2 (en) * 2001-05-03 2003-11-11 International Business Machines Corporation Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator
US6753216B2 (en) * 2002-10-31 2004-06-22 Freescale Semiconductor, Inc. Multiple gate transistor employing monocrystalline silicon walls
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6872647B1 (en) * 2003-05-06 2005-03-29 Advanced Micro Devices, Inc. Method for forming multiple fins in a semiconductor device
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
US6855583B1 (en) * 2003-08-05 2005-02-15 Advanced Micro Devices, Inc. Method for forming tri-gate FinFET with mesa isolation
US6962843B2 (en) * 2003-11-05 2005-11-08 International Business Machines Corporation Method of fabricating a finfet
US7422946B2 (en) * 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7491594B2 (en) * 2005-10-26 2009-02-17 Freescale Semiconductor, Inc. Methods of generating planar double gate transistor shapes

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328813A (en) * 1992-06-30 1994-07-12 The Dow Chemical Company Method for the preparation of optical recording media containing overcoat
EP0721221A2 (en) 1995-01-03 1996-07-10 International Business Machines Corporation FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
US5581101A (en) * 1995-01-03 1996-12-03 International Business Machines Corporation FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
US5723370A (en) 1995-01-03 1998-03-03 International Business Machines Corporation FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
US20020181523A1 (en) 2001-05-29 2002-12-05 Pinneo George G. Low cost high integrity diode laser array
US6492212B1 (en) 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Doo, V.Y., "Method of Making Submicron Channel MOSFET," IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, pp. 3407-3408.

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080217616A1 (en) * 2007-03-05 2008-09-11 Yong-Hoon Son Semiconductor integrated circuit device and a method of fabricating the same
US7888246B2 (en) 2007-03-05 2011-02-15 Samsung Electronics Co., Ltd. Semiconductor integrated circuit device and a method of fabricating the same
US20110127530A1 (en) * 2007-03-05 2011-06-02 Samsung Electronics Co., Ltd. Semiconductor integrated circuit device
US8101509B2 (en) 2007-03-05 2012-01-24 Samsung Electronics Co., Ltd. Semiconductor integrated circuit device
US8373165B2 (en) 2007-03-05 2013-02-12 Samsung Electronics Co., Ltd. Semiconductor integrated circuit device and a method of fabricating the same
US20100090197A1 (en) * 2008-10-10 2010-04-15 Electonics And Telecommunications Research Institute Method of manufacturing semiconductor nanowire sensor device and semiconductor nanowire sensor device manufactured according to the method
US8119430B2 (en) * 2008-10-10 2012-02-21 Electronics And Telecommunications Research Institute Method of manufacturing semiconductor nanowire sensor device and semiconductor nanowire sensor device manufactured according to the method
US8232164B2 (en) 2010-10-29 2012-07-31 International Business Machines Corporation Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
US8890257B2 (en) 2010-10-29 2014-11-18 International Business Machines Corporation Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
US9385050B2 (en) 2011-01-06 2016-07-05 Globalfoundries Inc. Structure and method to fabricate resistor on finFET processes
US8753964B2 (en) 2011-01-27 2014-06-17 International Business Machines Corporation FinFET structure having fully silicided fin
US9530701B2 (en) 2014-12-18 2016-12-27 International Business Machines Corporation Method of forming semiconductor fins on SOI substrate

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