US7130226B2 - Clock generating circuit with multiple modes of operation - Google Patents
Clock generating circuit with multiple modes of operation Download PDFInfo
- Publication number
- US7130226B2 US7130226B2 US11/054,885 US5488505A US7130226B2 US 7130226 B2 US7130226 B2 US 7130226B2 US 5488505 A US5488505 A US 5488505A US 7130226 B2 US7130226 B2 US 7130226B2
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- 230000003111 delayed effect Effects 0.000 claims abstract description 78
- 230000006870 function Effects 0.000 claims abstract description 16
- 230000000630 rising effect Effects 0.000 claims description 40
- 230000008878 coupling Effects 0.000 claims description 21
- 238000010168 coupling process Methods 0.000 claims description 21
- 238000005859 coupling reaction Methods 0.000 claims description 21
- 230000015654 memory Effects 0.000 claims description 13
- 238000003491 array Methods 0.000 claims description 11
- 230000007423 decrease Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims 7
- 230000007704 transition Effects 0.000 claims 7
- 230000002401 inhibitory effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 13
- 230000004044 response Effects 0.000 description 8
- 230000001934 delay Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
Abstract
Description
Claims (32)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/054,885 US7130226B2 (en) | 2005-02-09 | 2005-02-09 | Clock generating circuit with multiple modes of operation |
US11/542,918 US7336548B2 (en) | 2005-02-09 | 2006-10-03 | Clock generating circuit with multiple modes of operation |
US11/957,333 US7643359B2 (en) | 2005-02-09 | 2007-12-14 | Clock generating circuit with multiple modes of operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/054,885 US7130226B2 (en) | 2005-02-09 | 2005-02-09 | Clock generating circuit with multiple modes of operation |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/542,918 Continuation US7336548B2 (en) | 2005-02-09 | 2006-10-03 | Clock generating circuit with multiple modes of operation |
Publications (2)
Publication Number | Publication Date |
---|---|
US20060176761A1 US20060176761A1 (en) | 2006-08-10 |
US7130226B2 true US7130226B2 (en) | 2006-10-31 |
Family
ID=36779780
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/054,885 Active US7130226B2 (en) | 2005-02-09 | 2005-02-09 | Clock generating circuit with multiple modes of operation |
US11/542,918 Active US7336548B2 (en) | 2005-02-09 | 2006-10-03 | Clock generating circuit with multiple modes of operation |
US11/957,333 Active 2025-04-09 US7643359B2 (en) | 2005-02-09 | 2007-12-14 | Clock generating circuit with multiple modes of operation |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/542,918 Active US7336548B2 (en) | 2005-02-09 | 2006-10-03 | Clock generating circuit with multiple modes of operation |
US11/957,333 Active 2025-04-09 US7643359B2 (en) | 2005-02-09 | 2007-12-14 | Clock generating circuit with multiple modes of operation |
Country Status (1)
Country | Link |
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US (3) | US7130226B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070041253A1 (en) * | 2005-03-22 | 2007-02-22 | Mediatek Inc. | Methods and systems for generating latch clock used in memory reading |
US20070096785A1 (en) * | 2005-10-27 | 2007-05-03 | Nec Electronics Corporation | DLL circuit and test method thereof |
US20080094116A1 (en) * | 2005-02-09 | 2008-04-24 | Micron Technology, Inc. | Clock generating circuit with multiple modes of operation |
US20080172193A1 (en) * | 2007-01-11 | 2008-07-17 | Woogeun Rhee | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
US20100123499A1 (en) * | 2008-11-14 | 2010-05-20 | Elpida Memory, Inc. | Information system, semiconductor device and control method therefor |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100638747B1 (en) * | 2004-12-28 | 2006-10-30 | 주식회사 하이닉스반도체 | Clock generation apparatus in semiconductor memory device and its method |
US20060195288A1 (en) * | 2005-02-12 | 2006-08-31 | International Business Machines Corporation | Method for at speed testing of multi-clock domain chips |
US7475311B2 (en) * | 2005-08-30 | 2009-01-06 | Kabushiki Kaisha Toshiba | Systems and methods for diagnosing rate dependent errors using LBIST |
KR100832021B1 (en) * | 2006-06-29 | 2008-05-26 | 주식회사 하이닉스반도체 | Semiconductor memory device and driving method thereof |
US7849339B2 (en) * | 2007-03-23 | 2010-12-07 | Silicon Image, Inc. | Power-saving clocking technique |
US7876640B2 (en) | 2008-09-23 | 2011-01-25 | Micron Technology, Inc. | Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay |
KR101045072B1 (en) * | 2009-12-28 | 2011-06-29 | 주식회사 하이닉스반도체 | Phase locked loop and method for driving the same |
US8510487B2 (en) | 2010-02-11 | 2013-08-13 | Silicon Image, Inc. | Hybrid interface for serial and parallel communication |
US8760188B2 (en) | 2011-06-30 | 2014-06-24 | Silicon Image, Inc. | Configurable multi-dimensional driver and receiver |
US9071243B2 (en) | 2011-06-30 | 2015-06-30 | Silicon Image, Inc. | Single ended configurable multi-mode driver |
US8885435B2 (en) | 2012-09-18 | 2014-11-11 | Silicon Image, Inc. | Interfacing between integrated circuits with asymmetric voltage swing |
US9306563B2 (en) | 2013-02-19 | 2016-04-05 | Lattice Semiconductor Corporation | Configurable single-ended driver |
US8963646B1 (en) * | 2013-08-19 | 2015-02-24 | Nanya Technology Corporation | Delay line ring oscillation apparatus |
US9786353B2 (en) * | 2016-02-18 | 2017-10-10 | Intel Corporation | Reconfigurable clocking architecture |
RU168355U1 (en) * | 2016-08-19 | 2017-01-30 | Александр Николаевич Беляев | DEVICE FOR COLLECTION, MONITORING AND CONTROL OF EQUIPMENT OF ELECTRICAL SUBSTATION |
KR102268767B1 (en) * | 2017-06-09 | 2021-06-29 | 에스케이하이닉스 주식회사 | Delay circuit and duty cycle controller including the same |
KR20200119669A (en) * | 2019-04-10 | 2020-10-20 | 에스케이하이닉스 주식회사 | Semiconductor device |
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-
2005
- 2005-02-09 US US11/054,885 patent/US7130226B2/en active Active
-
2006
- 2006-10-03 US US11/542,918 patent/US7336548B2/en active Active
-
2007
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080094116A1 (en) * | 2005-02-09 | 2008-04-24 | Micron Technology, Inc. | Clock generating circuit with multiple modes of operation |
US7643359B2 (en) * | 2005-02-09 | 2010-01-05 | Micron Technology, Inc. | Clock generating circuit with multiple modes of operation |
US20070041253A1 (en) * | 2005-03-22 | 2007-02-22 | Mediatek Inc. | Methods and systems for generating latch clock used in memory reading |
US7652938B2 (en) * | 2005-03-22 | 2010-01-26 | Mediatek, Inc. | Methods and systems for generating latch clock used in memory reading |
US20070096785A1 (en) * | 2005-10-27 | 2007-05-03 | Nec Electronics Corporation | DLL circuit and test method thereof |
US7642825B2 (en) * | 2005-10-27 | 2010-01-05 | Nec Electronics Corporation | DLL circuit and test method thereof |
US20080172193A1 (en) * | 2007-01-11 | 2008-07-17 | Woogeun Rhee | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
US8736323B2 (en) * | 2007-01-11 | 2014-05-27 | International Business Machines Corporation | Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops |
US20100123499A1 (en) * | 2008-11-14 | 2010-05-20 | Elpida Memory, Inc. | Information system, semiconductor device and control method therefor |
Also Published As
Publication number | Publication date |
---|---|
US7643359B2 (en) | 2010-01-05 |
US7336548B2 (en) | 2008-02-26 |
US20070035336A1 (en) | 2007-02-15 |
US20080094116A1 (en) | 2008-04-24 |
US20060176761A1 (en) | 2006-08-10 |
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