US7205223B2 - Method of forming an interconnect structure for a semiconductor device - Google Patents
Method of forming an interconnect structure for a semiconductor device Download PDFInfo
- Publication number
- US7205223B2 US7205223B2 US09/982,953 US98295301A US7205223B2 US 7205223 B2 US7205223 B2 US 7205223B2 US 98295301 A US98295301 A US 98295301A US 7205223 B2 US7205223 B2 US 7205223B2
- Authority
- US
- United States
- Prior art keywords
- forming
- layer
- copper
- conductive plug
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (18)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/982,953 US7205223B2 (en) | 2000-04-11 | 2001-10-22 | Method of forming an interconnect structure for a semiconductor device |
US11/710,924 US7679193B2 (en) | 2000-04-11 | 2007-02-27 | Use of AIN as cooper passivation layer and thermal conductor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/547,926 US7061111B2 (en) | 2000-04-11 | 2000-04-11 | Interconnect structure for use in an integrated circuit |
US09/982,953 US7205223B2 (en) | 2000-04-11 | 2001-10-22 | Method of forming an interconnect structure for a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/547,926 Division US7061111B2 (en) | 2000-04-11 | 2000-04-11 | Interconnect structure for use in an integrated circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/710,924 Continuation US7679193B2 (en) | 2000-04-11 | 2007-02-27 | Use of AIN as cooper passivation layer and thermal conductor |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070042596A1 US20070042596A1 (en) | 2007-02-22 |
US7205223B2 true US7205223B2 (en) | 2007-04-17 |
Family
ID=24186702
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/547,926 Expired - Fee Related US7061111B2 (en) | 2000-04-11 | 2000-04-11 | Interconnect structure for use in an integrated circuit |
US09/982,953 Expired - Fee Related US7205223B2 (en) | 2000-04-11 | 2001-10-22 | Method of forming an interconnect structure for a semiconductor device |
US11/710,924 Expired - Fee Related US7679193B2 (en) | 2000-04-11 | 2007-02-27 | Use of AIN as cooper passivation layer and thermal conductor |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/547,926 Expired - Fee Related US7061111B2 (en) | 2000-04-11 | 2000-04-11 | Interconnect structure for use in an integrated circuit |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/710,924 Expired - Fee Related US7679193B2 (en) | 2000-04-11 | 2007-02-27 | Use of AIN as cooper passivation layer and thermal conductor |
Country Status (8)
Country | Link |
---|---|
US (3) | US7061111B2 (en) |
JP (1) | JP2003530694A (en) |
KR (1) | KR100652120B1 (en) |
AU (1) | AU2001251504A1 (en) |
DE (1) | DE10196065B3 (en) |
GB (1) | GB2378040B (en) |
TW (1) | TW520560B (en) |
WO (1) | WO2001078141A2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8912592B2 (en) | 2012-02-22 | 2014-12-16 | Samsung Electronics Co., Ltd. | Non-volatile memory device including etch stop layer pattern |
US20150255329A1 (en) * | 2014-03-07 | 2015-09-10 | Applied Materials, Inc. | Methods for forming passivation protection for an interconnection structure |
US10229876B2 (en) | 2015-05-19 | 2019-03-12 | Samsung Electronics Co., Ltd. | Wiring structures and semiconductor devices |
US11756828B2 (en) | 2018-11-20 | 2023-09-12 | Applied Materials, Inc. | Cluster processing system for forming a transition metal material |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US7061111B2 (en) * | 2000-04-11 | 2006-06-13 | Micron Technology, Inc. | Interconnect structure for use in an integrated circuit |
US7622322B2 (en) * | 2001-03-23 | 2009-11-24 | Cornell Research Foundation, Inc. | Method of forming an AlN coated heterojunction field effect transistor |
JP4316188B2 (en) * | 2002-05-29 | 2009-08-19 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US7153776B2 (en) * | 2002-11-27 | 2006-12-26 | International Business Machines Corporation | Method for reducing amine based contaminants |
US7227257B2 (en) * | 2002-12-09 | 2007-06-05 | Intel Corporation | Cooling micro-channels |
US7825516B2 (en) * | 2002-12-11 | 2010-11-02 | International Business Machines Corporation | Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures |
US7642649B2 (en) * | 2003-12-01 | 2010-01-05 | Texas Instruments Incorporated | Support structure for low-k dielectrics |
US6949457B1 (en) * | 2004-01-21 | 2005-09-27 | Kla-Tencor Technologies Corporation | Barrier enhancement |
KR100549014B1 (en) * | 2004-07-21 | 2006-02-02 | 삼성전자주식회사 | Semiconductor Devices Having A Spacer Pattern And Methods Of Forming The Same |
KR100632658B1 (en) * | 2004-12-29 | 2006-10-12 | 주식회사 하이닉스반도체 | Method of forming metal line in semiconductor device |
US8148822B2 (en) * | 2005-07-29 | 2012-04-03 | Megica Corporation | Bonding pad on IC substrate and method for making the same |
US8399989B2 (en) * | 2005-07-29 | 2013-03-19 | Megica Corporation | Metal pad or metal bump over pad exposed by passivation layer |
JP5120913B2 (en) | 2006-08-28 | 2013-01-16 | 国立大学法人東北大学 | Semiconductor device and multilayer wiring board |
DE102007004867B4 (en) * | 2007-01-31 | 2009-07-30 | Advanced Micro Devices, Inc., Sunnyvale | A method of increasing the reliability of copper-based metallization structures in a microstructure device by using aluminum nitride |
US7538398B2 (en) * | 2007-06-21 | 2009-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for forming a semiconductor device source/drain contact |
TWI380452B (en) * | 2008-03-27 | 2012-12-21 | Au Optronics Corp | Thin film transistor, active array substrate and method for manufacturing the same |
US8274101B2 (en) * | 2009-10-20 | 2012-09-25 | Omnivision Technologies, Inc. | CMOS image sensor with heat management structures |
DE102011002769B4 (en) * | 2011-01-17 | 2013-03-21 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | A semiconductor device and method of making a hybrid contact structure having small aspect ratio contacts in a semiconductor device |
JP5909852B2 (en) * | 2011-02-23 | 2016-04-27 | ソニー株式会社 | Manufacturing method of semiconductor device |
US8461043B2 (en) * | 2011-04-11 | 2013-06-11 | Micron Technology, Inc. | Barrier layer for integrated circuit contacts |
US8610280B2 (en) | 2011-09-16 | 2013-12-17 | Micron Technology, Inc. | Platinum-containing constructions, and methods of forming platinum-containing constructions |
US8846513B2 (en) * | 2011-09-23 | 2014-09-30 | Globalfoundries Inc. | Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill |
CN104347476B (en) * | 2013-07-23 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
US9601431B2 (en) * | 2014-02-05 | 2017-03-21 | Applied Materials, Inc. | Dielectric/metal barrier integration to prevent copper diffusion |
US9362198B2 (en) | 2014-04-10 | 2016-06-07 | Freescale Semiconductor, Inc. | Semiconductor devices with a thermally conductive layer and methods of their fabrication |
US11101218B2 (en) * | 2018-08-24 | 2021-08-24 | Micron Technology, Inc. | Integrated assemblies having metal-containing regions coupled with semiconductor regions |
US11404345B2 (en) * | 2020-06-10 | 2022-08-02 | Qualcomm Incorporated | Advanced integrated passive device (IPD) with thin-film heat spreader (TF-HS) layer for high power handling filters in transmit (TX) path |
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US4611745A (en) | 1984-02-24 | 1986-09-16 | Kabushiki Kaisha Toshiba | Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same |
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-
2000
- 2000-04-11 US US09/547,926 patent/US7061111B2/en not_active Expired - Fee Related
-
2001
- 2001-04-10 WO PCT/US2001/011636 patent/WO2001078141A2/en active Application Filing
- 2001-04-10 AU AU2001251504A patent/AU2001251504A1/en not_active Abandoned
- 2001-04-10 KR KR1020027013548A patent/KR100652120B1/en not_active IP Right Cessation
- 2001-04-10 GB GB0223484A patent/GB2378040B/en not_active Expired - Fee Related
- 2001-04-10 DE DE10196065.4T patent/DE10196065B3/en not_active Expired - Lifetime
- 2001-04-10 JP JP2001574897A patent/JP2003530694A/en active Pending
- 2001-04-11 TW TW090108691A patent/TW520560B/en not_active IP Right Cessation
- 2001-10-22 US US09/982,953 patent/US7205223B2/en not_active Expired - Fee Related
-
2007
- 2007-02-27 US US11/710,924 patent/US7679193B2/en not_active Expired - Fee Related
Patent Citations (28)
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US4611745A (en) | 1984-02-24 | 1986-09-16 | Kabushiki Kaisha Toshiba | Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same |
US4987750A (en) | 1986-07-08 | 1991-01-29 | Gershon Meckler | Air conditioning apparatus |
EP0260906A2 (en) | 1986-09-17 | 1988-03-23 | Fujitsu Limited | Method of producing semiconductor device and semiconductor device |
US5447599A (en) | 1991-11-12 | 1995-09-05 | Cornell Research Foundation, Inc. | Self-aligned process for capping copper lines |
US5270263A (en) * | 1991-12-20 | 1993-12-14 | Micron Technology, Inc. | Process for depositing aluminum nitride (AlN) using nitrogen plasma sputtering |
US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
US5739579A (en) | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
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US20150255329A1 (en) * | 2014-03-07 | 2015-09-10 | Applied Materials, Inc. | Methods for forming passivation protection for an interconnection structure |
US9299605B2 (en) * | 2014-03-07 | 2016-03-29 | Applied Materials, Inc. | Methods for forming passivation protection for an interconnection structure |
US10229876B2 (en) | 2015-05-19 | 2019-03-12 | Samsung Electronics Co., Ltd. | Wiring structures and semiconductor devices |
US11756828B2 (en) | 2018-11-20 | 2023-09-12 | Applied Materials, Inc. | Cluster processing system for forming a transition metal material |
Also Published As
Publication number | Publication date |
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DE10196065T1 (en) | 2003-04-03 |
JP2003530694A (en) | 2003-10-14 |
DE10196065B3 (en) | 2015-04-16 |
AU2001251504A1 (en) | 2001-10-23 |
KR100652120B1 (en) | 2006-11-30 |
US7061111B2 (en) | 2006-06-13 |
KR20030030989A (en) | 2003-04-18 |
US20070164442A1 (en) | 2007-07-19 |
US20020175362A1 (en) | 2002-11-28 |
US7679193B2 (en) | 2010-03-16 |
US20070042596A1 (en) | 2007-02-22 |
GB0223484D0 (en) | 2002-11-13 |
WO2001078141A3 (en) | 2002-06-06 |
GB2378040B (en) | 2004-10-13 |
TW520560B (en) | 2003-02-11 |
WO2001078141A2 (en) | 2001-10-18 |
GB2378040A (en) | 2003-01-29 |
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