US7279946B2 - Clock controller with integrated DLL and DCC - Google Patents
Clock controller with integrated DLL and DCC Download PDFInfo
- Publication number
- US7279946B2 US7279946B2 US11/215,779 US21577905A US7279946B2 US 7279946 B2 US7279946 B2 US 7279946B2 US 21577905 A US21577905 A US 21577905A US 7279946 B2 US7279946 B2 US 7279946B2
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- US
- United States
- Prior art keywords
- clock
- delay
- data
- delayed
- host
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- Pulse Circuits (AREA)
Abstract
Description
N*Tcyc=T1+Tc+T2+T3 Equation I
-
- T1=clock receiver propagation delay;
- Tc=duty restore circuit propagation delay;
- T2=delay time of first delay element;
- T3=off-chip driver propagation delay;
- Tcyc=cycle time of host clock; and
- N=integer value.
Based on I/D1 from DLL-PD 156,CNT1 158 solves Equation I and provides ADJ1 with a coded value that is translated to a desired delay time T2 byfirst delay element 110.
T2′=T2−δ Equation II
-
- T2′=delay time of second delay element;
- T2=delay time of first delay element (phase adjustment); and
- δ=duty cycle delay adjustment.
T2′=T2+½(Tcyc)−δ Equation II
-
- T2′=adjustable delay time of second delay element;
- T2=delay time of first delay element (phase adjustment);
- Tcyc=cycle time of reference clock; and
- δ=duty cycle delay adjustment.
In Equation II above, the value of δ is based on the output I/D2 of DCC-PD 160.
Claims (29)
Priority Applications (1)
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US11/215,779 US7279946B2 (en) | 2005-08-30 | 2005-08-30 | Clock controller with integrated DLL and DCC |
Applications Claiming Priority (1)
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US11/215,779 US7279946B2 (en) | 2005-08-30 | 2005-08-30 | Clock controller with integrated DLL and DCC |
Publications (2)
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US20070046346A1 US20070046346A1 (en) | 2007-03-01 |
US7279946B2 true US7279946B2 (en) | 2007-10-09 |
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US11/215,779 Expired - Fee Related US7279946B2 (en) | 2005-08-30 | 2005-08-30 | Clock controller with integrated DLL and DCC |
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US (1) | US7279946B2 (en) |
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US20060197565A1 (en) * | 2005-03-02 | 2006-09-07 | Hynix Semiconductor Inc. | Delay locked loop for controlling duty rate of clock |
US20070210843A1 (en) * | 2006-03-09 | 2007-09-13 | Yasuhiro Takai | Dll circuit and semiconductor device having the same |
US20070277071A1 (en) * | 2006-04-21 | 2007-11-29 | Altera Corporation | Write-Side Calibration for Data Interface |
US20080164922A1 (en) * | 2007-01-10 | 2008-07-10 | Hynix Semiconductor Inc. | Data output strobe signal generating circuit and semiconductor memory apparatus having the same |
US20080191768A1 (en) * | 2007-02-08 | 2008-08-14 | Kabushiki Kaisha Toshiba | Semiconductor Integrated Circuit Device Operating in Synchronism with Clock and Method for Controlling Duty of Clock |
US20080191751A1 (en) * | 2007-02-13 | 2008-08-14 | Hynix Semiconductor Inc. | Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including the same |
US20080191921A1 (en) * | 2007-02-14 | 2008-08-14 | Markus Scholz | Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal |
US20090115480A1 (en) * | 2007-11-02 | 2009-05-07 | Hynix Semiconductor Inc. | Clock control circuit and data alignment circuit including the same |
US20090231006A1 (en) * | 2008-03-14 | 2009-09-17 | Hynix Semiconductor, Inc. | Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same |
US20090243677A1 (en) * | 2008-03-25 | 2009-10-01 | Micron Technology, Inc. | Clock generator and methods using closed loop duty cycle correction |
US20090295433A1 (en) * | 2006-01-11 | 2009-12-03 | Keith Aelwyn Jenkins | Method and apparatus for measuring and compensating for static phase error in phase locked loops |
US20090303827A1 (en) * | 2008-06-05 | 2009-12-10 | Hynix Semiconductor, Inc | Semiconductor memory device |
US20100117702A1 (en) * | 2008-11-12 | 2010-05-13 | Jae Min Jang | Duty cycle correction apparatus and semiconductor integrated circuit having the same |
US7746134B1 (en) * | 2007-04-18 | 2010-06-29 | Altera Corporation | Digitally controlled delay-locked loops |
CN101667450B (en) * | 2008-09-02 | 2013-05-22 | 海力士半导体有限公司 | Data input/output circuit |
US9692403B2 (en) * | 2015-10-30 | 2017-06-27 | Texas Instruments Incorporated | Digital clock-duty-cycle correction |
US9780766B1 (en) | 2016-05-12 | 2017-10-03 | Infineon Technologies Austria Ag | Phase shift clock for digital LLC converter |
US20180048319A1 (en) * | 2016-08-12 | 2018-02-15 | Samsung Electronics Co., Ltd. | Delay locked loop circuit and integrated circuit including the same |
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US7716510B2 (en) | 2006-12-19 | 2010-05-11 | Micron Technology, Inc. | Timing synchronization circuit with loop counter |
US7865756B2 (en) * | 2007-03-12 | 2011-01-04 | Mosaid Technologies Incorporated | Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices |
US7656745B2 (en) | 2007-03-15 | 2010-02-02 | Micron Technology, Inc. | Circuit, system and method for controlling read latency |
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US8552776B2 (en) | 2012-02-01 | 2013-10-08 | Micron Technology, Inc. | Apparatuses and methods for altering a forward path delay of a signal path |
US9166579B2 (en) * | 2012-06-01 | 2015-10-20 | Micron Technology, Inc. | Methods and apparatuses for shifting data signals to match command signal delay |
US9054675B2 (en) | 2012-06-22 | 2015-06-09 | Micron Technology, Inc. | Apparatuses and methods for adjusting a minimum forward path delay of a signal path |
KR101331442B1 (en) * | 2012-06-29 | 2013-11-21 | 포항공과대학교 산학협력단 | Delay locked loop with a loop-embedded duty cycle corrector |
US9001594B2 (en) | 2012-07-06 | 2015-04-07 | Micron Technology, Inc. | Apparatuses and methods for adjusting a path delay of a command path |
US9329623B2 (en) | 2012-08-22 | 2016-05-03 | Micron Technology, Inc. | Apparatuses, integrated circuits, and methods for synchronizing data signals with a command signal |
US9508417B2 (en) | 2014-02-20 | 2016-11-29 | Micron Technology, Inc. | Methods and apparatuses for controlling timing paths and latency based on a loop delay |
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US9601170B1 (en) | 2016-04-26 | 2017-03-21 | Micron Technology, Inc. | Apparatuses and methods for adjusting a delay of a command signal path |
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US10224938B2 (en) | 2017-07-26 | 2019-03-05 | Micron Technology, Inc. | Apparatuses and methods for indirectly detecting phase variations |
US10367493B1 (en) | 2018-06-14 | 2019-07-30 | Sandisk Technologies Llc | Duty cycle and skew correction for output signals generated in source synchronous systems |
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US7142026B2 (en) * | 2003-11-20 | 2006-11-28 | Hynix Semiconductor Inc. | Delay locked loop and its control method for correcting a duty ratio of a clock signal |
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JP3355900B2 (en) * | 1995-12-21 | 2002-12-09 | マックス株式会社 | Staple driver |
-
2005
- 2005-08-30 US US11/215,779 patent/US7279946B2/en not_active Expired - Fee Related
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Cited By (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7372311B2 (en) * | 2005-03-02 | 2008-05-13 | Hynix Semiconductor Inc. | Delay locked loop for controlling duty rate of clock |
US20060197565A1 (en) * | 2005-03-02 | 2006-09-07 | Hynix Semiconductor Inc. | Delay locked loop for controlling duty rate of clock |
US20090295433A1 (en) * | 2006-01-11 | 2009-12-03 | Keith Aelwyn Jenkins | Method and apparatus for measuring and compensating for static phase error in phase locked loops |
US7880518B2 (en) * | 2006-01-11 | 2011-02-01 | International Business Machines Corporation | Method and apparatus for measuring and compensating for static phase error in phase locked loops |
US7642826B2 (en) * | 2006-03-09 | 2010-01-05 | Elpida Memory, Inc. | DLL circuit and semiconductor device having the same |
US20070210843A1 (en) * | 2006-03-09 | 2007-09-13 | Yasuhiro Takai | Dll circuit and semiconductor device having the same |
US20070277071A1 (en) * | 2006-04-21 | 2007-11-29 | Altera Corporation | Write-Side Calibration for Data Interface |
US7706996B2 (en) * | 2006-04-21 | 2010-04-27 | Altera Corporation | Write-side calibration for data interface |
US20080164922A1 (en) * | 2007-01-10 | 2008-07-10 | Hynix Semiconductor Inc. | Data output strobe signal generating circuit and semiconductor memory apparatus having the same |
US7633324B2 (en) * | 2007-01-10 | 2009-12-15 | Hynix Semiconductor Inc. | Data output strobe signal generating circuit and semiconductor memory apparatus having the same |
US7724056B2 (en) * | 2007-02-08 | 2010-05-25 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device operating in synchronism with clock and method for controlling duty of clock |
US20080191768A1 (en) * | 2007-02-08 | 2008-08-14 | Kabushiki Kaisha Toshiba | Semiconductor Integrated Circuit Device Operating in Synchronism with Clock and Method for Controlling Duty of Clock |
US7616038B2 (en) * | 2007-02-13 | 2009-11-10 | Hynix Semiconductor Inc. | Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including the same |
US20080191751A1 (en) * | 2007-02-13 | 2008-08-14 | Hynix Semiconductor Inc. | Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including the same |
US7804925B2 (en) * | 2007-02-14 | 2010-09-28 | Infineon Technologies Ag | Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal |
US20080191921A1 (en) * | 2007-02-14 | 2008-08-14 | Markus Scholz | Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal |
US7746134B1 (en) * | 2007-04-18 | 2010-06-29 | Altera Corporation | Digitally controlled delay-locked loops |
US20090115480A1 (en) * | 2007-11-02 | 2009-05-07 | Hynix Semiconductor Inc. | Clock control circuit and data alignment circuit including the same |
US8248126B2 (en) * | 2007-11-02 | 2012-08-21 | Hynix Semiconductor Inc. | Clock control circuit and data alignment circuit including the same |
US7863957B2 (en) * | 2008-03-14 | 2011-01-04 | Hynix Semiconductor Inc. | Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same |
US20090231006A1 (en) * | 2008-03-14 | 2009-09-17 | Hynix Semiconductor, Inc. | Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same |
US8018261B2 (en) * | 2008-03-25 | 2011-09-13 | Micron Technology, Inc. | Clock generator and methods using closed loop duty cycle correction |
US8324946B2 (en) | 2008-03-25 | 2012-12-04 | Micron Technology, Inc. | Clock generator and methods using closed loop duty cycle correction |
US20090243677A1 (en) * | 2008-03-25 | 2009-10-01 | Micron Technology, Inc. | Clock generator and methods using closed loop duty cycle correction |
US7881148B2 (en) * | 2008-06-05 | 2011-02-01 | Hynix Semiconductor Inc. | Semiconductor memory device |
US20090303827A1 (en) * | 2008-06-05 | 2009-12-10 | Hynix Semiconductor, Inc | Semiconductor memory device |
CN101667450B (en) * | 2008-09-02 | 2013-05-22 | 海力士半导体有限公司 | Data input/output circuit |
US7915939B2 (en) * | 2008-11-12 | 2011-03-29 | Hynix Semiconductor Inc. | Duty cycle correction apparatus and semiconductor integrated circuit having the same |
US20100117702A1 (en) * | 2008-11-12 | 2010-05-13 | Jae Min Jang | Duty cycle correction apparatus and semiconductor integrated circuit having the same |
US9692403B2 (en) * | 2015-10-30 | 2017-06-27 | Texas Instruments Incorporated | Digital clock-duty-cycle correction |
US9780766B1 (en) | 2016-05-12 | 2017-10-03 | Infineon Technologies Austria Ag | Phase shift clock for digital LLC converter |
US10374587B2 (en) | 2016-05-12 | 2019-08-06 | Infineon Technologies Austria Ag | Phase shift clock for digital LLC converter |
US20180048319A1 (en) * | 2016-08-12 | 2018-02-15 | Samsung Electronics Co., Ltd. | Delay locked loop circuit and integrated circuit including the same |
US10128853B2 (en) * | 2016-08-12 | 2018-11-13 | Samsung Electronics Co., Ltd. | Delay locked loop circuit and integrated circuit including the same |
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