US7342278B2 - Non-volatile two-transistor programmable logic cell and array layout - Google Patents
Non-volatile two-transistor programmable logic cell and array layout Download PDFInfo
- Publication number
- US7342278B2 US7342278B2 US11/750,650 US75065007A US7342278B2 US 7342278 B2 US7342278 B2 US 7342278B2 US 75065007 A US75065007 A US 75065007A US 7342278 B2 US7342278 B2 US 7342278B2
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- United States
- Prior art keywords
- transistor
- memory
- switch
- well
- type well
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Definitions
- mirrored pairs of memory transistors and switch transistors are shown in p-type well 12 in FIGS. 1A and 1B .
- Contacts 20 - 1 , 20 - 2 , and 20 - 3 form the common source connections for each pair of memory transistors and contacts 22 - 1 , 22 - 2 , and 22 - 3 form the common source connections for each pair of switch transistors.
- Contacts 24 - 1 , 24 - 2 , and 24 - 3 connect to the drains of the first of the memory transistors in each pair of cells and contacts 26 - 1 , 26 - 2 , and 26 - 3 connect to the drains of the second of the memory transistors in each pair of cells.
- a two-transistor non-volatile memory cell is formed in a semiconductor body.
- a memory-transistor well is disposed within the semiconductor body.
- a switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory-transistor well.
- a memory transistor through which the cell may be programmed and erased is formed within the memory-transistor well and includes spaced-apart source and drain regions.
- a switch transistor that may be used to make interconnections between circuit elements is formed within the switch-transistor well region and includes spaced-apart source and drain regions.
- a floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and the switch transistor.
- a control gate is disposed above and self aligned with respect to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
- a memory-transistor p-type well 42 is disposed in the n-type well 40 .
- P-type wells 42 may have depths of between about 0.5 to about 5 microns and may typically be about 30% deeper than the switch n-type wells 40 .
- N-type wells 42 may be doped to from between about 1e16 and about 1e18.
- Active n-type regions 44 and 46 are formed in memory-transistor p-type well 42 and may have doping concentrations of from between about 1e19 and about 1e18.
- a mirrored memory-transistor structure is depicted in FIG.
- contact 72 makes contact to a portion of active region 64 that acts the common source for two separate switch transistors.
- Contact 74 makes contact to the drain region of a first (upper) one of the memory transistors in active region 64 and contact 76 makes contact to the drain region of a second (lower) one of the memory transistors in active region 64 .
- four separate transistors are shown disposed within switch-transistor p-type well 60 .
- a second switch-transistor p-type well 80 is disposed in n-type well 40 and is spaced apart from memory-transistor p-type well 42 on the side opposite from first switch-transistor p-type well 60 .
- mirrored switch transistors may be employed in second switch-transistor p-type well 80 .
- active regions 82 and 84 are formed in switch-transistor p-type well 80 .
- a contact 86 makes contact to a portion of active region 82 that acts as the common source for two separate switch transistors.
- Contact 88 makes contact to the drain region of a first (upper) one of the switch transistors in active region 82 and contact 90 makes contact to the drain region of a second (lower) one of the switch transistors in active region 82 .
- contact 92 makes contact to a portion of active region 84 that acts as the common source for two separate switch transistors.
- Contact 94 makes contact to the drain region of a first (upper) one of the memory transistors in active region 84 and contact 96 makes contact to the drain region of a second (lower) one of the memory transistors in active region 84 .
- four separate transistors are shown disposed within switch-transistor p-type well 80 .
- the n-type well 40 acts to advantageously provide electrical isolation of the memory transistor in each two-transistor non-volatile memory cell from its switch transistor.
- This isolation combined with the grouping of the memory transistors in a memory-transistor well and the switch transistors in a switch-transistor well, not only allows for advantageously programming and erasing of the memory cells, but also advantageously allows the wells, the memory transistors, and the switch transistors to be separately optimized for desired characteristics.
- the memory-well depth, doping and diffusion parameters and switch-well depth, doping and diffusion parameters can be separately optimized for desired characteristics of the memory transistors (e.g., programming and erase method and efficiency) and the switch transistors (e.g., speed, current handling capability).
- FIGS. 3A and 3B top and cross-sectional views, respectively, are shown of a layout of a group of two-transistor non-volatile memory cells according to another aspect of the present invention employing common n-type well isolation and other n-type well isolation.
- the cross section of FIG. 3B is taken through the dashed line 3 B- 3 B of FIG. 3A .
- n-type well 110 surrounds each of the memory-transistor p-type well 12 and the switch-transistor p-type well regions 60 and 80 .
- the outer edges of n-type well 110 are preferably spaced apart from the edges of the memory-transistor p-type well region 42 and the switch-transistor p-type well regions 60 and 80 .
- a deep n-type well region 112 is formed under n-type well region 110 .
- Deep n-type well region 112 may be formed to a depth of between about 0.3 microns and about 3 microns deeper than the p-wells containing the transistors.
- FIGS. 5A and 5B The layout of the group of two-transistor non-volatile memory cells shown in FIGS. 5A and 5B is similar to that depicted in FIGS. 4A and 4B . Elements of the layout of FIGS. 5A and 5B that correspond to elements of the layout depicted in FIGS. 4A and 4B are designated in FIGS. 5A and 5B using the same reference numerals as their counterparts in FIGS. 4A and 4B .
- the enhanced p-type regions 114 are areas of higher p-type dopant concentration. Persons of ordinary skill in the art will appreciate that, by adding the enhanced p-type regions and placing the deep n-type well regions 112 adjacent to the devices, the space-charge regions are significantly reduced. Since the space-charge regions are simply lost area, this geometry allows closer spacing of the devices and thus permits a more closely-spaced layout.
- the n-type well regions are the most heavily doped.
- the deep n-type well regions 112 are doped to about 25% of the concentration of the n-type well regions 110 .
- the n-type well regions 42 are doped to a concentration that is about an order of magnitude lower than that of the n-type well regions 110 .
- the enhanced p-type well regions are doped to a higher than the other p-type well regions to reduce depletion regions.
- FIGS. 6A and 6B top and cross-sectional views, respectively, are shown of a layout of a group of two-transistor non-volatile memory cells according to another aspect of the present invention employing deep-trench isolation.
- the cross section of FIG. 6B is taken through the dashed line 6 B- 6 B of FIG. 6A .
Abstract
Description
Claims (20)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/750,650 US7342278B2 (en) | 2005-06-15 | 2007-05-18 | Non-volatile two-transistor programmable logic cell and array layout |
US11/962,615 US7501681B2 (en) | 2005-06-15 | 2007-12-21 | Non-volatile two-transistor programmable logic cell and array layout |
US12/359,481 US7898018B2 (en) | 2005-06-15 | 2009-01-26 | Non-volatile two-transistor programmable logic cell and array layout |
US13/037,507 US8258567B2 (en) | 2005-06-15 | 2011-03-01 | Non-volatile two-transistor programmable logic cell and array layout |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/155,005 US7285818B2 (en) | 2005-06-15 | 2005-06-15 | Non-volatile two-transistor programmable logic cell and array layout |
US11/750,650 US7342278B2 (en) | 2005-06-15 | 2007-05-18 | Non-volatile two-transistor programmable logic cell and array layout |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/155,005 Division US7285818B2 (en) | 2005-06-15 | 2005-06-15 | Non-volatile two-transistor programmable logic cell and array layout |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/962,615 Division US7501681B2 (en) | 2005-06-15 | 2007-12-21 | Non-volatile two-transistor programmable logic cell and array layout |
Publications (2)
Publication Number | Publication Date |
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US20070215935A1 US20070215935A1 (en) | 2007-09-20 |
US7342278B2 true US7342278B2 (en) | 2008-03-11 |
Family
ID=37570957
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/155,005 Active 2025-07-19 US7285818B2 (en) | 2005-06-15 | 2005-06-15 | Non-volatile two-transistor programmable logic cell and array layout |
US11/750,650 Expired - Fee Related US7342278B2 (en) | 2005-06-15 | 2007-05-18 | Non-volatile two-transistor programmable logic cell and array layout |
US11/927,265 Active US7473960B1 (en) | 2005-06-15 | 2007-10-29 | Non-volatile two-transistor programmable logic cell and array layout |
US11/962,615 Active US7501681B2 (en) | 2005-06-15 | 2007-12-21 | Non-volatile two-transistor programmable logic cell and array layout |
US12/359,481 Active US7898018B2 (en) | 2005-06-15 | 2009-01-26 | Non-volatile two-transistor programmable logic cell and array layout |
US13/037,507 Expired - Fee Related US8258567B2 (en) | 2005-06-15 | 2011-03-01 | Non-volatile two-transistor programmable logic cell and array layout |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US11/155,005 Active 2025-07-19 US7285818B2 (en) | 2005-06-15 | 2005-06-15 | Non-volatile two-transistor programmable logic cell and array layout |
Family Applications After (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/927,265 Active US7473960B1 (en) | 2005-06-15 | 2007-10-29 | Non-volatile two-transistor programmable logic cell and array layout |
US11/962,615 Active US7501681B2 (en) | 2005-06-15 | 2007-12-21 | Non-volatile two-transistor programmable logic cell and array layout |
US12/359,481 Active US7898018B2 (en) | 2005-06-15 | 2009-01-26 | Non-volatile two-transistor programmable logic cell and array layout |
US13/037,507 Expired - Fee Related US8258567B2 (en) | 2005-06-15 | 2011-03-01 | Non-volatile two-transistor programmable logic cell and array layout |
Country Status (4)
Country | Link |
---|---|
US (6) | US7285818B2 (en) |
EP (1) | EP1889299A4 (en) |
JP (1) | JP2008547198A (en) |
WO (1) | WO2006138086A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080093654A1 (en) * | 2005-06-15 | 2008-04-24 | Actel Corporation | Non-volatile two-transistor programmable logic cell and array layout |
US7538382B1 (en) * | 2005-06-15 | 2009-05-26 | Actel Corporation | Non-volatile two-transistor programmable logic cell and array layout |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7368789B1 (en) * | 2005-06-13 | 2008-05-06 | Actel Corporation | Non-volatile programmable memory cell and array for programmable logic array |
US7495279B2 (en) * | 2005-09-09 | 2009-02-24 | Infineon Technologies Ag | Embedded flash memory devices on SOI substrates and methods of manufacture thereof |
US7808055B2 (en) * | 2007-06-21 | 2010-10-05 | Gigadevice Semiconductor Inc. | Methods and apparatus for semiconductor memory devices manufacturable using bulk CMOS process manufacturing |
US9530495B1 (en) | 2015-08-05 | 2016-12-27 | Adesto Technologies Corporation | Resistive switching memory having a resistor, diode, and switch memory cell |
US9922973B1 (en) * | 2017-06-01 | 2018-03-20 | Globalfoundries Inc. | Switches with deep trench depletion and isolation structures |
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-
2005
- 2005-06-15 US US11/155,005 patent/US7285818B2/en active Active
-
2006
- 2006-06-01 WO PCT/US2006/021569 patent/WO2006138086A2/en active Application Filing
- 2006-06-01 JP JP2008516919A patent/JP2008547198A/en active Pending
- 2006-06-01 EP EP06772035A patent/EP1889299A4/en not_active Withdrawn
-
2007
- 2007-05-18 US US11/750,650 patent/US7342278B2/en not_active Expired - Fee Related
- 2007-10-29 US US11/927,265 patent/US7473960B1/en active Active
- 2007-12-21 US US11/962,615 patent/US7501681B2/en active Active
-
2009
- 2009-01-26 US US12/359,481 patent/US7898018B2/en active Active
-
2011
- 2011-03-01 US US13/037,507 patent/US8258567B2/en not_active Expired - Fee Related
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US5510730A (en) | 1986-09-19 | 1996-04-23 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5587603A (en) | 1995-01-06 | 1996-12-24 | Actel Corporation | Two-transistor zero-power electrically-alterable non-volatile latch |
US5625211A (en) | 1995-01-12 | 1997-04-29 | Actel Corporation | Two-transistor electrically-alterable switch employing hot electron injection and fowler nordheim tunneling |
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US20080093654A1 (en) * | 2005-06-15 | 2008-04-24 | Actel Corporation | Non-volatile two-transistor programmable logic cell and array layout |
US7501681B2 (en) * | 2005-06-15 | 2009-03-10 | Actel Corporation | Non-volatile two-transistor programmable logic cell and array layout |
US7538382B1 (en) * | 2005-06-15 | 2009-05-26 | Actel Corporation | Non-volatile two-transistor programmable logic cell and array layout |
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US7898018B2 (en) | 2005-06-15 | 2011-03-01 | Actel Corporation | Non-volatile two-transistor programmable logic cell and array layout |
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Also Published As
Publication number | Publication date |
---|---|
US7473960B1 (en) | 2009-01-06 |
US20110147821A1 (en) | 2011-06-23 |
US20070215935A1 (en) | 2007-09-20 |
US7501681B2 (en) | 2009-03-10 |
US7898018B2 (en) | 2011-03-01 |
US20090159954A1 (en) | 2009-06-25 |
US20080093654A1 (en) | 2008-04-24 |
JP2008547198A (en) | 2008-12-25 |
EP1889299A4 (en) | 2010-06-09 |
EP1889299A2 (en) | 2008-02-20 |
US20060284238A1 (en) | 2006-12-21 |
WO2006138086A3 (en) | 2009-04-30 |
US7285818B2 (en) | 2007-10-23 |
US8258567B2 (en) | 2012-09-04 |
WO2006138086A2 (en) | 2006-12-28 |
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