US7413956B2 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
US7413956B2
US7413956B2 US11/181,577 US18157705A US7413956B2 US 7413956 B2 US7413956 B2 US 7413956B2 US 18157705 A US18157705 A US 18157705A US 7413956 B2 US7413956 B2 US 7413956B2
Authority
US
United States
Prior art keywords
film
oxidation film
forming
source
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/181,577
Other versions
US20070026592A1 (en
Inventor
Yong Wook SHIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sk Keyfoundry Inc
Original Assignee
MagnaChip Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MagnaChip Semiconductor Ltd filed Critical MagnaChip Semiconductor Ltd
Priority to US11/181,577 priority Critical patent/US7413956B2/en
Assigned to MAGNACHIP SEMICONDUCTOR, LTD. reassignment MAGNACHIP SEMICONDUCTOR, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIN, YONG WOOK
Publication of US20070026592A1 publication Critical patent/US20070026592A1/en
Application granted granted Critical
Publication of US7413956B2 publication Critical patent/US7413956B2/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Assignors: MAGNACHIP SEMICONDUCTOR, LTD.
Assigned to MAGNACHIP SEMICONDUCTOR LTD. reassignment MAGNACHIP SEMICONDUCTOR LTD. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION
Assigned to MAGNACHIP SEMICONDUCTOR LTD. reassignment MAGNACHIP SEMICONDUCTOR LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Assignors: US BANK NATIONAL ASSOCIATION
Assigned to KEY FOUNDRY CO., LTD. reassignment KEY FOUNDRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MAGNACHIP SEMICONDUCTOR, LTD.
Assigned to SK KEYFOUNDRY INC. reassignment SK KEYFOUNDRY INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: KEY FOUNDRY CO., LTD.
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a salicide process in which silicide is formed simultaneously on a gate and source/drain regions.
  • silicide is formed on a polysilicon substrate using tungsten, and is used as a gate electrode of a metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • FIGS. 1A to 1D are sectional views illustrating a conventional method for manufacturing a semiconductor device.
  • a field oxidation film 110 for insulating unit complementary metal oxide semiconductor field effect transistors (CMOSFETs) from each other is formed on a silicon substrate 100 .
  • CMOSFETs complementary metal oxide semiconductor field effect transistors
  • a gate oxidation film 140 for forming a gate is grown on the silicon substrate 100 .
  • a polysilicon gate is formed by stacking a polysilicon film 150 doped with impurities serving as an electrode of the gate on the gate oxidation film 140 and forming a pattern using a mask.
  • source/drain junctions 170 are formed by injecting impurities two to four times into regions used as source and drains of a transistor using a spacer oxidation films 160 interposed between.
  • a blank oxidation film 180 is formed on the field oxidation film 110 , and is removed from places other than regions, in which silicide is not formed, by etching.
  • a silicide film 190 is formed by a salicide process.
  • the silicide film is formed or remains through the side wall of the transistor even by a small error in the process, thereby generating short between a gate and the drains or between the gate and the source, or increasing parasitic capacitor, thus exerting a negative influence upon yield and characteristics of products.
  • the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device, in which the height of the side wall of a polysilicon gate is increased to solve problems generated from the formation of silicide along the side wall of a transistor, and a method for manufacturing the same.
  • a semiconductor device comprising: a semiconductor substrate, in which active regions and inactive regions are separated from each other by a field oxidation film; source/drain junctions contacting the field oxidation film and formed in the active regions of the semiconductor substrates; a buffer oxidation film formed at designated portions of the source/drain junctions, and a gate electrode formed on the semiconductor substrate adjacent to the buffer oxidation film; and a silicide film formed at designated portions of the source/drain junctions and the upper surface of the gate electrode.
  • a blank oxidation film may be formed at regions at which the silicide film is not formed.
  • the blank oxidation film protects portions of the silicon substrate, at which the silicide film is not formed.
  • the buffer oxidation film may be formed on designated portions of the source/drain junctions opposite to the field oxidation film.
  • the buffer oxidation film which is present under the gate electrode, increases the height of the side wall of the gate electrode, thereby assuring a process margin in etching a spacer oxidation film or the blank oxidation film.
  • the designated portions of the source/drain junctions on which the silicide film is formed may be regions in which the blank oxidation film and the buffer oxidation film are not formed.
  • the silicide film may be made of any kind of silicide.
  • the silicide film is made of Ti silicide.
  • a method for manufacturing a semiconductor device comprising: forming a field oxidation film on inactive regions of a silicon substrate; forming buffer oxidation film impurity junctions on source and drain regions of the silicon substrate provided with the field oxidation film, and forming a buffer oxidation film thereon; forming a gate electrode on the above structure, and forming a spacer oxidation film on the side wall of the gate electrode; forming source/drain junctions on the silicon substrate under both sides of the gate electrode; and forming a blank oxidation film on regions of the structure other than regions in which a silicide film is formed, and forming the silicide film by performing a salicide process.
  • the buffer oxidation film may be selectively formed only in the source and drain regions using a nitride film. Further, preferably, the buffer oxidation film may be used, when impurities are injected to form the source/drain junctions, without using an additional oxidation film for protecting the silicon substrate. Thereby, it is possible to simplify the process of manufacturing the semiconductor device, and to shorten the overall time of the process.
  • designated portions of the buffer oxidation film may be removed when the blank oxidation film is etched after impurities are injected into the silicon substrate to form the source/drain junctions. More preferably, the removed portions of the buffer oxidation film may be not included by the gate electrode. Thereby, the buffer oxidation film remains only at the ends of the lower portion of the gate.
  • the silicide film may be made of any kind of silicide formed by the salicide process.
  • the silicide film is made of Ti silicide.
  • the silicide film is formed by bonding titanium and silicon. The titanium located on the oxidation film is not reacted with the silicon and is selectively removed in the etching step.
  • FIGS. 1A to 1D are sectional views illustrating a conventional method for manufacturing a semiconductor device.
  • FIGS. 2A to 2E are sectional views illustrating a method for manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
  • FIGS. 2A to 2E are sectional views illustrating a method for manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
  • a field oxidation film 210 for insulating unit transistors from each other is formed on a silicon substrate 200 .
  • a nitride film (not shown) for forming a buffer oxidation film 230 is stacked on the silicon substrate 200 .
  • Buffer oxidation film impurity junctions 220 are formed by forming a pattern using an oxidation film mask and injecting impurities for reducing a hot carrier effect and activating a channel. Then, a thermal process for forming a field oxidation film is performed, thereby forming an active region of a transistor, in which a gate electrode is not formed, and forming the buffer oxidation film 230 at end portions of the field oxidation films 210 .
  • a gate oxidation film 240 of the transistor is formed, and a polysilicon film 250 is stacked on the gate oxidation film 240 .
  • the polysilicon film 250 is patterned using a mask, thereby producing a gate electrode.
  • the buffer oxidation film 230 is present under the side wall of the polysilicon gate, the side wall of the polysilicon gate has a large height. Further, a process margin for the etching of a spacer oxidation film and a blank oxidation film is obtained.
  • a gate spacer oxidation film 260 is formed on the side wall of the gate electrode.
  • source/drain junctions 270 are formed by injecting impurities into regions in which a source and drains of a transistor will be formed.
  • the buffer oxidation film 230 remaining in source and drain regions prevents the damage to the silicon substrate 200 . Accordingly, a separate oxidation film for protecting the silicon substrate 200 is not required.
  • a blank oxidation film 280 is stacked on the silicon substrate 200 , and a necessary portion of the blank oxidation film 280 is removed by patterning using a mask and etching.
  • the buffer oxidation film 230 remaining in the source and drain regions is removed together with the removal of the blank oxidation film 280 .
  • silicide is formed by stacking titanium (not shown) on the silicon substrate 200 and performing a thermal process.
  • a titanium silicide film 290 is formed in regions, in which silicon and titanium are bonded, and titanium, which is not bonded to the silicon and located on the oxidation film, is selectively etched at a subsequent step.
  • an insulating film for a metal serving as an electrode and a metal process are the same as those of a general CMOS logic process.
  • the present invention provides a semiconductor device, in which the height of the side wall of a polysilicon gate is increased by a buffer oxidation film so that a process margin, when a spacer oxidation film or a blank oxidation film is etched, is assured, and a method for manufacturing the same.
  • impurities for reducing a hot carrier effect and activating a channel when buffer oxidation film impurity junctions are formed, are injected into a silicon substrate, thereby decreasing an electric field effect generated from the drain regions, thus increasing the deterioration of the semiconductor device due to the hot carrier effect.

Abstract

Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, in which active and inactive regions are separated by a field oxidation film; source/drain junctions contacting the field oxidation film and formed in the active regions of the semiconductor substrates; a buffer oxidation film formed at designated portions of the source/drain junctions, and a gate electrode formed on the semiconductor substrate adjacent to the buffer oxidation film; and a silicide film formed at designated portions of the source/drain junctions and the upper surface of the gate electrode.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a salicide process in which silicide is formed simultaneously on a gate and source/drain regions.
2. Description of the Related Art
In a conventional method for manufacturing a semiconductor device having a size of less than 1.2 μm, silicide is formed on a polysilicon substrate using tungsten, and is used as a gate electrode of a metal oxide semiconductor field effect transistor (MOSFET). However, as semiconductor devices become increasingly high-integrated to have a size less then 0.35 μm, various methods for forming electrodes using titanium in MOS transistors are widely used.
FIGS. 1A to 1D are sectional views illustrating a conventional method for manufacturing a semiconductor device.
As shown in FIG. 1A, a field oxidation film 110 for insulating unit complementary metal oxide semiconductor field effect transistors (CMOSFETs) from each other is formed on a silicon substrate 100.
Thereafter, as shown in FIG. 1B, a gate oxidation film 140 for forming a gate is grown on the silicon substrate 100. Then, a polysilicon gate is formed by stacking a polysilicon film 150 doped with impurities serving as an electrode of the gate on the gate oxidation film 140 and forming a pattern using a mask.
As shown in FIG. 1C, source/drain junctions 170 are formed by injecting impurities two to four times into regions used as source and drains of a transistor using a spacer oxidation films 160 interposed between.
Thereafter, a blank oxidation film 180 is formed on the field oxidation film 110, and is removed from places other than regions, in which silicide is not formed, by etching.
Then, a silicide film 190 is formed by a salicide process.
In the conventional method for forming silicide using the conventional technique, since a process margin does not exist when the etching of the spacer oxidation film or the blank oxidation film is performed during the formation of the source and drains, the silicide film is formed or remains through the side wall of the transistor even by a small error in the process, thereby generating short between a gate and the drains or between the gate and the source, or increasing parasitic capacitor, thus exerting a negative influence upon yield and characteristics of products.
Accordingly, a method for manufacturing a semiconductor device, in which a process margin for etching is assured to solve various problems generated from the formation of silicide, has been increasingly required.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device, in which the height of the side wall of a polysilicon gate is increased to solve problems generated from the formation of silicide along the side wall of a transistor, and a method for manufacturing the same.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a semiconductor device comprising: a semiconductor substrate, in which active regions and inactive regions are separated from each other by a field oxidation film; source/drain junctions contacting the field oxidation film and formed in the active regions of the semiconductor substrates; a buffer oxidation film formed at designated portions of the source/drain junctions, and a gate electrode formed on the semiconductor substrate adjacent to the buffer oxidation film; and a silicide film formed at designated portions of the source/drain junctions and the upper surface of the gate electrode.
Preferably, a blank oxidation film may be formed at regions at which the silicide film is not formed. The blank oxidation film protects portions of the silicon substrate, at which the silicide film is not formed.
Further, preferably, the buffer oxidation film may be formed on designated portions of the source/drain junctions opposite to the field oxidation film. The buffer oxidation film, which is present under the gate electrode, increases the height of the side wall of the gate electrode, thereby assuring a process margin in etching a spacer oxidation film or the blank oxidation film.
Preferably, the designated portions of the source/drain junctions on which the silicide film is formed may be regions in which the blank oxidation film and the buffer oxidation film are not formed.
The silicide film may be made of any kind of silicide. Preferably, the silicide film is made of Ti silicide.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a field oxidation film on inactive regions of a silicon substrate; forming buffer oxidation film impurity junctions on source and drain regions of the silicon substrate provided with the field oxidation film, and forming a buffer oxidation film thereon; forming a gate electrode on the above structure, and forming a spacer oxidation film on the side wall of the gate electrode; forming source/drain junctions on the silicon substrate under both sides of the gate electrode; and forming a blank oxidation film on regions of the structure other than regions in which a silicide film is formed, and forming the silicide film by performing a salicide process.
Preferably, the buffer oxidation film may be selectively formed only in the source and drain regions using a nitride film. Further, preferably, the buffer oxidation film may be used, when impurities are injected to form the source/drain junctions, without using an additional oxidation film for protecting the silicon substrate. Thereby, it is possible to simplify the process of manufacturing the semiconductor device, and to shorten the overall time of the process.
Preferably, designated portions of the buffer oxidation film may be removed when the blank oxidation film is etched after impurities are injected into the silicon substrate to form the source/drain junctions. More preferably, the removed portions of the buffer oxidation film may be not included by the gate electrode. Thereby, the buffer oxidation film remains only at the ends of the lower portion of the gate.
The silicide film may be made of any kind of silicide formed by the salicide process. Preferably, the silicide film is made of Ti silicide. Here, the silicide film is formed by bonding titanium and silicon. The titanium located on the oxidation film is not reacted with the silicon and is selectively removed in the etching step.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIGS. 1A to 1D are sectional views illustrating a conventional method for manufacturing a semiconductor device; and
FIGS. 2A to 2E are sectional views illustrating a method for manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
Now, a preferred embodiment of the present invention will be described in detail with reference to the annexed drawings.
The embodiment does not limit the scope and spirit of the invention, but has been disclosed for illustrative purposes.
Preferred Embodiment
FIGS. 2A to 2E are sectional views illustrating a method for manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
First, as shown in FIG. 2A, a field oxidation film 210 for insulating unit transistors from each other is formed on a silicon substrate 200.
Thereafter, as shown in FIG. 2B, a nitride film (not shown) for forming a buffer oxidation film 230 is stacked on the silicon substrate 200. Buffer oxidation film impurity junctions 220 are formed by forming a pattern using an oxidation film mask and injecting impurities for reducing a hot carrier effect and activating a channel. Then, a thermal process for forming a field oxidation film is performed, thereby forming an active region of a transistor, in which a gate electrode is not formed, and forming the buffer oxidation film 230 at end portions of the field oxidation films 210.
Subsequent steps are the same as those of the conventional process for manufacturing a salicide logic CMOS transistor.
That is, as shown in FIG. 2C, a gate oxidation film 240 of the transistor is formed, and a polysilicon film 250 is stacked on the gate oxidation film 240. Then, the polysilicon film 250 is patterned using a mask, thereby producing a gate electrode. Here, since the buffer oxidation film 230 is present under the side wall of the polysilicon gate, the side wall of the polysilicon gate has a large height. Further, a process margin for the etching of a spacer oxidation film and a blank oxidation film is obtained. Accordingly, it is possible to prevent the formation of silicide along the side wall of the gate, thereby preventing the generation of short between the gate and the source or between the gate and the drains and the generation of parasitic capacitance, thus assuring the safety of the semiconductor device.
Thereafter, a gate spacer oxidation film 260 is formed on the side wall of the gate electrode.
Then, as shown in FIG. 2D, source/drain junctions 270 are formed by injecting impurities into regions in which a source and drains of a transistor will be formed. When the impurity injection for forming the source and drains is performed, the buffer oxidation film 230 remaining in source and drain regions prevents the damage to the silicon substrate 200. Accordingly, a separate oxidation film for protecting the silicon substrate 200 is not required.
Thereafter, in order to protect the spacer oxidation film 260 formed on the side wall of the polysilicon gate and a specific circuit not requiring silicide, a blank oxidation film 280 is stacked on the silicon substrate 200, and a necessary portion of the blank oxidation film 280 is removed by patterning using a mask and etching. Here, the buffer oxidation film 230 remaining in the source and drain regions is removed together with the removal of the blank oxidation film 280.
As shown in FIG. 2E, silicide is formed by stacking titanium (not shown) on the silicon substrate 200 and performing a thermal process. Here, a titanium silicide film 290 is formed in regions, in which silicon and titanium are bonded, and titanium, which is not bonded to the silicon and located on the oxidation film, is selectively etched at a subsequent step.
Thereafter, an insulating film for a metal serving as an electrode and a metal process are the same as those of a general CMOS logic process.
As apparent from the above description, the present invention provides a semiconductor device, in which the height of the side wall of a polysilicon gate is increased by a buffer oxidation film so that a process margin, when a spacer oxidation film or a blank oxidation film is etched, is assured, and a method for manufacturing the same. Thereby, it is possible to prevent problems, such as shorts between a gate and drains or between the gate and a source generated due to the formation or remaining of silicide along the side wall of a transistor, and to greatly reduce parasitic capacitor, thus improving yield and characteristics of the semiconductor device.
Further, impurities, for reducing a hot carrier effect and activating a channel when buffer oxidation film impurity junctions are formed, are injected into a silicon substrate, thereby decreasing an electric field effect generated from the drain regions, thus increasing the deterioration of the semiconductor device due to the hot carrier effect.
Although the preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (7)

1. A method for manufacturing a semiconductor device comprising:
forming a field oxidation film on inactive regions of a silicon substrate;
forming buffer oxidation films on active regions of the semiconductor substrate, wherein the buffer oxidation films expose the semiconductor substrate where a gate electrode is to be formed;
forming an insulating film on the exposed semiconductor substrate and the buffer oxidation films;
depositing a gate conductive film on the insulating film;
patterning the gate conductive film and the insulating film to form a gate electrode and a gate insulating film, wherein both ends of the gate insulating film and the gate electrode overlap the end of the buffer oxidation films;
forming a spacer insulating film for preventing a silicide film from being formed at the sidewalls of the gate electrode;
forming source/drain junctions on the silicon substrate adjacent to, but not directly under, the gate electrode; and
forming a silicide film at designated portions of the source/drain junctions and on the upper surface of the gate electrode.
2. The method as set forth in claim 1, wherein the buffer oxidation film is selectively formed only in the source/drain junctions using a nitride film as a mask.
3. The method as set forth in claim 1, wherein the buffer oxidation film is used, when impurities are injected into the silicon substrate to form the source/drain junctions, without using an additional oxidation film for protecting the silicon substrate.
4. The method as set forth in claim 1, wherein designated portions of the buffer oxidation film are removed when the blank oxidation film is etched after impurities are injected into the silicon substrate to form the source/drain junctions.
5. The method as set forth in claim 1, comprising forming a blank oxidation film on regions of the structure other than regions in which the silicide film is formed prior to the step of forming the silicide film.
6. The method as set forth in claim 1, wherein the silicide film is made of Ti silicide.
7. The method as set forth in claim 2, comprising implanting impurities into the source/drain junctions of the semiconductor substrate to form buffer oxidation film impurity junctions prior to forming the buffer oxidation film using the nitride film as a mask.
US11/181,577 2005-07-13 2005-07-13 Semiconductor device manufacturing method Active 2026-01-20 US7413956B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/181,577 US7413956B2 (en) 2005-07-13 2005-07-13 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/181,577 US7413956B2 (en) 2005-07-13 2005-07-13 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
US20070026592A1 US20070026592A1 (en) 2007-02-01
US7413956B2 true US7413956B2 (en) 2008-08-19

Family

ID=37694889

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/181,577 Active 2026-01-20 US7413956B2 (en) 2005-07-13 2005-07-13 Semiconductor device manufacturing method

Country Status (1)

Country Link
US (1) US7413956B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7904500B1 (en) * 2007-03-22 2011-03-08 Google Inc. Advertising in chat system without topic-specific rooms

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084280A (en) 1998-10-15 2000-07-04 Advanced Micro Devices, Inc. Transistor having a metal silicide self-aligned to the gate
US6335550B1 (en) * 1999-02-26 2002-01-01 Sharp Kabushiki Kaisha Fet with ferroelectric gate
US6503833B1 (en) 2000-11-15 2003-01-07 International Business Machines Corporation Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084280A (en) 1998-10-15 2000-07-04 Advanced Micro Devices, Inc. Transistor having a metal silicide self-aligned to the gate
US6335550B1 (en) * 1999-02-26 2002-01-01 Sharp Kabushiki Kaisha Fet with ferroelectric gate
US6503833B1 (en) 2000-11-15 2003-01-07 International Business Machines Corporation Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby

Also Published As

Publication number Publication date
US20070026592A1 (en) 2007-02-01

Similar Documents

Publication Publication Date Title
US7485508B2 (en) Two-sided semiconductor-on-insulator structures and methods of manufacturing the same
JP7298852B2 (en) Warpage reduction trench capacitor
KR100278273B1 (en) A method for forming contact holes in semiconductor device
WO2017104396A1 (en) Method for manufacturing columnar semiconductor apparatus
JP2009026955A (en) Semiconductor device and process for producing the same
US10868017B2 (en) Memory structure and manufacturing method thereof
JPH05865B2 (en)
US7932142B2 (en) Transistor in a wiring interlayer insulating film
US7413956B2 (en) Semiconductor device manufacturing method
US7432163B2 (en) Method of manufacturing semiconductor device that includes forming adjacent field regions with a separating region therebetween
KR100305402B1 (en) Manufacturing method of semiconductor device
JP4565847B2 (en) Semiconductor device and manufacturing method thereof
JP2003124338A (en) Semiconductor device and its manufacturing method
US5620911A (en) Method for fabricating a metal field effect transistor having a recessed gate
KR100519508B1 (en) Method for forming semiconductor device by using salicide process
JP2689710B2 (en) Method for manufacturing semiconductor device
KR100552592B1 (en) Method of manufacturing the semiconductor device
KR100372820B1 (en) Double silicon mosfet and method of manufacturing the same
US6200905B1 (en) Method to form sidewall polysilicon capacitors
JP3277434B2 (en) Method for manufacturing transistor
JPS62224077A (en) Semiconductor integrated circuit device
KR0150671B1 (en) Manufacturing method of semiconductor having a different isolation structure between peripheral circuit area and cell area
KR100240096B1 (en) Method for manufacturing semiconductor device
JP3919473B2 (en) Semiconductor device and manufacturing method thereof
TW579577B (en) Manufacturing method for MOS transistor of embedded memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: MAGNACHIP SEMICONDUCTOR, LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHIN, YONG WOOK;REEL/FRAME:016944/0560

Effective date: 20050513

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUS

Free format text: AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:022277/0133

Effective date: 20090217

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: MAGNACHIP SEMICONDUCTOR LTD.,KOREA, DEMOCRATIC PEO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION;REEL/FRAME:024563/0807

Effective date: 20100527

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: MAGNACHIP SEMICONDUCTOR LTD., KOREA, REPUBLIC OF

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY;ASSIGNOR:US BANK NATIONAL ASSOCIATION;REEL/FRAME:034469/0001

Effective date: 20100527

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12

AS Assignment

Owner name: KEY FOUNDRY CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:053703/0227

Effective date: 20200828

AS Assignment

Owner name: SK KEYFOUNDRY INC., KOREA, REPUBLIC OF

Free format text: CHANGE OF NAME;ASSIGNOR:KEY FOUNDRY CO., LTD.;REEL/FRAME:066794/0290

Effective date: 20240130